A4983SETTR-T

A4983 DMOS Microstepping Driver with Translator Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Very thin profile QFN package Thermal shutdown circuitry Description The A4983 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A4983 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A4983. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4983 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A4983 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A4983 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a Continued on the next page… Package: 28-pin QFN (suffix ET) Approximate size Typical Application Diagram VDD 0.22 μF VREG VDD Microcontroller or Controller Logic MS1 MS2 MS3 SLEEP STEP DIR RESET ENABLE REF ROSC VCP CP1 0.1 μF CP2 0.1 μF VBB VBB VBB OUT1A OUT1B RS1 A4983 OUT2A OUT2B RS2 4983DS A4983 DMOS Microstepping Driver with Translator lockout (UVLO), and crossover-current protection. Special poweron sequencing is not required. The A4983 is supplied in a 5 mm × 5 mm × 0.90 nominal surface mount QFN package with exposed thermal pad (suffix ET). The package is lead (Pb) free (suffix –T), with 100% matte tin plated leadframe. Description (continued) slow decay for the remainder of the off-time). This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage Selection Guide Part Number A4983SET-T A4983SETTR-T Pb-free Yes Yes Package 28-pin QFN with exposed thermal pad 28-pin QFN with exposed thermal pad 73 pieces per tube 1500 pieces per 7-in. reel Packing Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Input Voltage Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature Symbol VBB IOUT VIN VSENSE VREF TA TJ(max) Tstg Range S Duty Cycle < 20% Notes Rating 35 ±2 ±2.5 –0.3 to 7 0.5 4 –20 to 85 150 –55 to 150 Units V A A V V V ºC ºC ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A4983 DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 F VREG ROSC CP1 0.1 F CP2 VDD Current Regulator OSC Charge Pump VCP 0.1 F DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay Gate Drive Control Logic DMOS Full Bridge STEP DIR RESET MS1 MS2 MS3 ENABLE SLEEP DAC Translator SENSE1 VBB2 RS1 OUT2A OUT2B PWM Latch Blanking Mixed Decay SENSE2 RS2 VREF Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A4983 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Min. 8 0 3.0 – – – – – – – – – – VDD×0.7 VIN = VDD×0.7 – –20 –20 – – 150 0.7 20 23 0 –3 – – – 100 – – 2.35 0.05 Typ.2 – – – 0.350 0.300 – – – – – – – – – – 3 V, then tOFF defaults to 30 μs. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of tOFF (μs) is approximately tOFF ≈ ROSC ⁄ 825 Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4983 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A4983 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4983 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. If the SLEEP pin is pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to the pin, should an overvoltage event occur. Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μs), is approximately tBLANK ≈ 1 μs Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side FET gates. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 through 6. As the trip point is reached, the A4983 initially goes into a fast decay mode for 31.25% of the off-time. tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing dagram for this feature appears on the next page. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation Enable Input (ENABLE). This input turns on or off all of the significantly, and can eliminate the need for external Schottky FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal required. The translator inputs STEP, DIR, MS1, MS2, and MS3, as well as the internal sequencing logic, all remain active, indepen- of the load current. A timing dagram for this feature appears on dent of the ENABLE input state. the next page. VREG (VREG). This internally-generated voltage is used to operate the sink-side FET outputs. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the FET outputs of the A4983 are disabled. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A4983 DMOS Microstepping Driver with Translator Current Decay Modes Timing Chart VPHASE + IOUT See Enlargement A 0 – Enlargement A toff IPEAK tFD tSD Slow Decay IOUT Mixed Decay Fa st De ca y t Symbol toff IPEAK tSD tFD IOUT Device fixed off-time Maximum output current Slow decay interval Fast decay interval Device output current Characteristic Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A4983 DMOS Microstepping Driver with Translator Application Layout Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4983 must be soldered directly onto the board. On the underside of the A4983 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. Thermal vias should not have any thermal relief and should be connected to internal layers, if available, to maximize the dissipation area. Grounding In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A4983, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. A4983 Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.) PCB Thermal Vias RS1 C7 OUT2A SENSE2 OUT1A SENSE1 VBB2 RS2 C9 VBB1 NC VBB C2 1 OUT2B ENABLE GND CP1 CP2 VCP NC RESET SLEEP ROSC VREG MS1 MS2 MS3 OUT1B A4983 PAD NC DIR GND REF STEP VDD C3 C4 R3 R2 VDD C1 C8 C6 R6 R1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 A4983 DMOS Microstepping Driver with Translator STEP 100.00 70.71 STEP 100.00 70.71 Slow Slow Mixed Slow Mixed Home Microstep Position Home Microstep Position –70.71 –100.00 100.00 70.71 Home Microstep Position –70.71 –100.00 100.00 70.71 Slow Slow Mixed Mixed Slow Mixed Slow Phase 2 IOUT2A Direction = H (%) 0.00 Slow –70.71 Phase 2 IOUT2B Direction = H (%) 0.00 –70.71 –100.00 –100.00 Figure 2. Decay Mode for Full-Step Increments STEP 100.00 92.39 70.71 Figure 3. Decay Modes for Half-Step Increments –38.27 –70.71 –92.39 –100.00 100.00 92.39 70.71 38.27 Phase 2 IOUT2B Direction = H (%) Slow Mixed Slow Mixed Slow Mixed 0.00 –38.27 –70.71 –92.39 –100.00 Figure 4. Decay Modes for Quarter-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 Slow 0.00 Mixed Slow Mixed Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) Slow 0.00 Phase 1 IOUT1A Direction = H (%) Mixed 0.00 11 A4983 DMOS Microstepping Driver with Translator STEP 100.00 92.39 83.15 70.71 55.56 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 Phase 2 IOUT2B Direction = H (%) 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 Mixed Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 19.51 0.00 –19.51 Slow Mixed Slow Mixed Mixed Slow Figure 5. Decay Modes for Eighth-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 12 A4983 DMOS Microstepping Driver with Translator STEP 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Phase 1 IOUT1A Direction = H (%) 9.8 0.00 –9.8 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Slow Mixed Slow Mixed Phase 2 IOUT2B Direction = H (%) 9.8 0.00 –9.8 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 Slow Mixed Slow Mixed Slow Figure 6. Decay Modes for Sixteenth-Step Increments Home Microstep Position Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 13 A4983 DMOS Microstepping Driver with Translator Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step # Half Step # 1 1/4 Step # 1 1/8 Step # 1 2 1/16 Step # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Phase 1 Current [% ItripMax] Phase 2 Current [% ItripMax] (%) 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 –9.80 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –92.39 –95.69 –98.08 –99.52 (%) 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 Step Angle (º) 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4 Full Step # Half Step # 5 1/4 Step # 9 1/8 Step # 17 18 1/16 Step # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Phase 1 Current [% ItripMax] Phase 2 Current [% ItripMax] Step Angle (º) (%) –100.00 –99.52 –98.08 –95.69 –92.39 –88.19 –83.15 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 (%) 0.00 –9.80 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –92.39 –95.69 –98.08 –99.52 –100.00 –99.52 –98.08 –95.69 –92.39 –88.19 –83.15 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.80 180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4 2 3 4 10 19 20 1 2 3 5 6 3 6 11 21 22 4 7 8 12 23 24 3 5 9 10 7 13 25 26 6 11 12 14 27 28 2 4 7 13 14 4 8 15 29 30 8 15 16 16 31 32 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 14 A4983 DMOS Microstepping Driver with Translator Pin-out Diagram 27 SENSE2 23 SENSE1 26 OUT2A 24 OUT1A 28 VBB2 22 VBB1 21 OUT1B 20 NC 19 DIR PAD 18 GND 17 REF 16 STEP 15 VDD MS2 10 RESET 12 ROSC 13 SLEEP 14 MS3 11 8 9 OUT2B ENABLE GND CP1 CP2 VCP NC 1 2 3 4 5 6 7 Terminal List Table Name CP1 CP2 VCP VREG MS1 MS2 MS3 RESET ROSC SLEEP VDD STEP REF GND DIR OUT1B VBB1 SENSE1 OUT1A OUT2A SENSE2 VBB2 OUT2B ENABLE NC PAD Number 4 5 6 8 9 10 11 12 13 14 15 16 17 3, 18 19 21 22 23 24 26 27 28 1 2 7, 20, 25 – Description Charge pump capacitor terminal Charge pump capacitor terminal Reservoir capacitor terminal Regulator decoupling terminal Logic input Logic input Logic input Logic input Timing set Logic input Logic supply Logic input Gm reference voltage input Ground* Logic input DMOS Full Bridge 1 Output B Load supply Sense resistor terminal for Bridge 1 DMOS Full Bridge 1 Output A DMOS Full Bridge 2 Output A Sense resistor terminal for Bridge 2 Load supply DMOS Full Bridge 2 Output B Logic input No connection Exposed pad for enhanced thermal dissipation* *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. VREG MS1 25 NC Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 15 A4983 DMOS Microstepping Driver with Translator ET Package, 28-Pin QFN with Exposed Thermal Pad 5.15 .203 4.85 .191 All dimensions reference, not for tooling use (reference JEDEC MO-220VHHD except contact length and exposed pad length and width) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V3M) except heel extended; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 28 1 2 A B A 5.15 .203 4.85 .191 28X 0.08 [.003] C 28X 0.30 .012 0.18 .007 0.10 [.004] M C A B 0.05 [.002] M C 0.50 .020 SEATING PLANE 1.00 .039 0.80 .031 0.20 .008 REF 0.05 .002 0.00 .000 C 0.30 .012 NOM 28 4X0.20 .008 MIN 24X0.20 .008 MIN 0.50 .020 NOM 4X0.20 .008 MIN 1 2 3.15 .124 NOM 4.96 .195 NOM 0.56 .022 REF R0.25 REF .010 2 1 28 B C 3.15 .124 NOM 5.0 .197 NOM 1.09 .043 REF 3.15 .124 NOM 4.96 .195 NOM 3.15 .124 NOM 5.0 .197 NOM The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright ©2007, Allegro MicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 16