A5979GLPTR-T

A5979 Microstepping DMOS Driver with Translator FEATURES AND BENEFITS • • • • • • • • • • • • ±2.8 A, 40 V output rating Low RDS(on) outputs, 0.22 Ω source, 0.15 Ω sink typical Automatic current decay mode detection/selection 3 to 5.5 V logic supply voltage range Mixed, fast, and slow current decay modes Home output Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Short-to-ground protection Short-to-VBB protection Shorted load protection Package: 28-lead TSSOP (suffix LP) with exposed thermal pad DESCRIPTION The A5979 is a complete microstepping motor driver with built-in translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with output drive capability of 40 V and ±2.8 A. The A5979 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A5979. Simply inputting one pulse on the STEP input drives the motor one step (two logic inputs determine if it is a full-, half-, quarter-, or sixteenth-step). There are no phase sequence tables, high-frequency control lines, or complex interfaces to program. The A5979 interface is an ideal fit for applications where a complex microprocessor is unavailable or overburdened. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-up sequencing is not required. The A5979 is supplied in a thin ( 30 ns –0.3 to VDD + 0.3 V Pulsed, tW < 30 ns –1 to VDD + 1 V VSENSE 0.5 V Reference Voltage VREF VDD V Output Current IOUT ±2.8 A –40 to 105 °C Operating Ambient Temperature TA Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Range G Junction Temperature TJ(max) 150 °C Storage Temperature Tstg –55 to 150 °C THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol Package Thermal Resistance RθJA Test Conditions* Package LP, on 4-layer PCB based on JEDEC standard Value Units 28 ºC/W *Additional thermal information available on Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A5979 Microstepping DMOS Driver with Translator PINOUT DIAGRAM AND TERMINAL LIST TABLE Terminal List Table Number Name 1 SENSE1 Sense resistor for bridge 1 25 OUT1B 2 HOMEn Logic output PFD 5 24 CP2 3 DIR RC1 6 23 CP1 4 OUT1A 28 VBB1 SENSE1 1 27 SLEEPn HOMEn 2 26 ENABLEn DIR 3 OUT1A 4 AGND 7 PAD 22 VCP Description Logic input DMOS full-bridge 1, output A REF 8 21 PGND 5 PFD Analog input for mixed-decay setting RC2 9 20 VREG 6 RC1 Analog input for fixed off-time, bridge 1 VDD 10 19 STEP 7 AGND* 8 REF Gm reference input Analog input for fixed off-time, bridge 2 OUT2A 11 18 OUT2B MS2 12 17 RESETn MS1 13 16 SR SENSE2 14 15 VBB2 Package LP, 28-Pin TSSOP Analog ground 9 RC2 10 VDD 11 OUT2A 12 MS2 Logic input 13 MS1 Logic input 14 SENSE2 15 VBB2 Logic supply voltage DMOS full-bridge 2, output A Sense resistor for bridge 2 Load supply for bridge 2 16 SR Logic input 17 RESETn Logic input 18 OUT2B DMOS full-bridge 2, output B 19 STEP Logic input 20 VREG Regulator decoupling 21 PGND* Power ground 22 VCP Reservoir capacitor 23 CP1 Charge pump capacitor 24 CP2 Charge pump capacitor 25 OUT1B 26 ENABLEn DMOS full-bridge 1, output B Logic input 27 SLEEPn Logic input 28 VBB1 Load supply for bridge 1 – PAD* Thermal pad * GND, PGND, and thermal pad must be connected together externally under the device. Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A5979 Microstepping DMOS Driver with Translator FUNCTIONAL BLOCK DIAGRAM CP1 VREG Logic Supply VDD UVLO Charge Pump Regulator SENSE1 Reference Supply REF CP2 VCP Load Supply VBB1 DAC ÷8 RC1 DMOS H-BRIDGE 4 STEP DIR PWM Timer PWM Latch Blanking Mixed Decay RESETn MS1 Translator OUT1A OUT1B SENSE1 MS2 HOMEn 4 SLEEPn Control Logic SR Gate Drive SENSE1 VBB2 ENABLEn DMOS H-BRIDGE RC2 PWM Timer PWM Latch Blanking Mixed Decay VDD OUT2A OUT2B DAC SENSE2 PFD AGND PGND Exposed Thermal Pad (Required) Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A5979 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS1: Valid at TA = 25°C, VBB = 40 V, unless otherwise noted Characteristics Symbol Load Supply Voltage Range VBB Output Leakage Current IDSS Output On-Resistance Body Diode Forward Voltage VBB Supply Current VDD Supply Current RDS(On) VF IBB IDD Test Conditions Min. Typ.2 Max. Units Operating 8 – 40 V During sleep mode 0 – 40 V VOUT = VBB –