A6273KLW

6273 ADVANCE INFORMATION (Subject to change without notice) January 24, 2000 CLEAR IN 1 IN 2 OUT 1 OUT 2 OUT 3 OUT 4 IN 3 IN 4 GROUND 1 2 3 4 VDD 20 19 18 17 LOGIC SUPPLY IN 8 IN 7 OUT 8 OUT 7 OUT 6 OUT 5 IN 6 IN 5 STROBE 8-BIT LATCHED DMOS POWER DRIVER The A6273KA and A6273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. The DMOS output inverts the DATA input. All of the output drivers are disabled (the DMOS sink drivers turned OFF) with the CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are capable of sinking up to 750 mA. Similar devices with reduced rDS(on) will be available as the A6A273. The A6273KA is furnished in a 20-pin dual in-line plastic package. The A6273KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surface-mount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C. Data Sheet 26180.120 LATCHES LATCHES 5 6 7 8 9 10 16 15 14 13 12 11 Dwg. PP-015-2 Note that the A6273KA (DIP) and the A6273KLW (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Voltage, VO ............................. 50 V Output Drain Current, Continuous, IO ....................... 250 mA* Peak, IOM .............................. 750 mA*† Peak, IOM ..................................... 2.0 A† Single-Pulse Avalanche Energy, EAS .............................................. 75 mJ Logic Supply Voltage, VDD ................ 7.0 V Input Voltage Range, VI ................................. -0.3 V to +7.0 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA .............................. -40°C to +125°C Storage Temperature Range, TS .............................. -55°C to +150°C * Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. FEATURES I 50 V Minimum Output Clamp Voltage I 250 mA Output Current (all outputs simultaneously) I 1.3 Ω Typical rDS(on) I Low Power Consumption I Replacements for TPIC6273N and TPIC6273DW Always order by complete part number: Part Number Package A6273KA 20-pin DIP A6273KLW 20-lead SOIC RθJA 55°C/W 70°C/W RθJC 25°C/W 17°C/W 6273 8-BIT LATCHED DMOS POWER DRIVER LOGIC SYMBOL ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 1 11 SU FF IX R C1 1D 1D 1D 1D 1D 1D 1D 1D 4 5 6 7 14 15 16 17 2.0 2 'A ', R 1.5 SU FF IX θJ 3 A= 'LW ', R 55 °C /W 8 9 12 13 18 1.0 θJ A =7 0° C/ W 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 19 Dwg. GS-004A Dwg. FP-046-1 VDD IN OUT Dwg. EP-010-16 Dwg. EP-063 LOGIC INPUTS DMOS POWER DRIVER OUTPUT FUNCTION TABLE CLEAR L H H H Inputs STROBE X INX X H L X OUTX H L H R L L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. 6273 8-BIT LATCHED DMOS POWER DRIVER FUNCTIONAL BLOCK DIAGRAM IN 1 STROBE D C1 CLR IN2 LOGIC SUPPLY IN 3 V DD D C1 CLR D C1 CLR IN 4 D C1 CLR IN5 D C1 CLR IN6 D C1 CLR IN 7 D C1 CLR IN8 D C1 CLEAR (ACTIVE LOW) Dwg. FP-016-2 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 GROUND CLR www.allegromicro.com 6273 8-BIT LATCHED DMOS POWER DRIVER RECOMMENDED OPERATING CONDITIONS over operating temperature range Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ ≥ 0.85VDD Low-level input voltage, VIL ................................. ≤0.15VDD ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). Limits Characteristic Logic Supply Voltage Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Symbol VDD V(BR)DSX IDSX Test Conditions Operating I O = 1 mA VO = 40 V VO = 40 V TA = 125°C Min. 4.5 50 — — — — — — — — — — — — — — Typ. 5.0 — 0.05 0.15 1.3 2.0 1.3 250 — — 625 150 675 400 15 150 Max. 5.5 — 1.0 5.0 2.0 3.2 2.0 — 1.0 -1.0 — — — — 100 300 Units V V µA µA Ω Ω Ω mA µA µA ns ns ns ns µA µA rDS(on) IO = 250 mA, VDD = 4.5 V IO = 250 mA, VDD = 4.5 V, TA = 125°C IO = 500 mA, VDD = 4.5 V (see note) Nominal Output Current Logic Input Current IO(nom) IIH IIL VDS(on) = 0.5 V, TA = 85°C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF VDD = 5.5 V, Outputs OFF VDD = 5.5 V, Outputs ON Prop. Delay Time tPLH tPHL Output Rise Time Output Fall Time Supply Current tr tf IDD(off) IDD(on) Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6273 8-BIT LATCHED DMOS POWER DRIVER TIMING REQUIREMENTS INx 50% 50% t su(D) STROBE t h(D) 50% t su(D) t h(D) t PLH OUTPUTx 10% t PHL 90% tr tf Dwg. WP-036-1 Input Active Time Before Strobe (Data Set-Up Time), tsu(D) .............................................. 20 ns Input Active Time After Strobe (Data Hold Time), th(D) ................................................... 20 ns Input Pulse Width, tw(D) ...................................................... 40 ns Input Logic High, VIH ................................................ ≥ 0.85VDD Input Logic Low, VIL ................................................. ≤ 0.15VDD www.allegromicro.com 6273 8-BIT LATCHED DMOS POWER DRIVER TEST CIRCUITS INPUT +15 V 0.11 Ω tav IAS = 1.0 A IO DUT OUT VO V(BR)DSX VO(ON) Dwg. EP-066-1 EAS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 100 mH 6273 8-BIT LATCHED DMOS POWER DRIVER TERMINAL DESCRIPTIONS Terminal No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name CLEAR Function When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF). CMOS data input to a latch. When strobed, the output then inverts the data input (IN1 = HIGH, OUT1 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN2 = HIGH, OUT2 = LOW). Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. CMOS data input to a latch. When strobed, the output then inverts the data input (IN3 = HIGH, OUT3 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN4 = HIGH, OUT4 = LOW). Reference terminal for all voltage measurements. A CMOS dynamic input to all latches. Data on each INx terminal is loaded into its associated latch on a low-to-high STROBE transition. CMOS data input to a latch. When strobed, the output then inverts the data input (IN5 = HIGH, OUT5 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN6 = HIGH, OUT6 = LOW). Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. Current-sinking, open-drain DMOS output. CMOS data input to a latch. When strobed, the output then inverts the data input (IN7 = HIGH, OUT7 = LOW). CMOS data input to a latch. When strobed, the output then inverts the data input (IN8 = HIGH, OUT8 = LOW). (VDD) The logic supply voltage (typically 5 V). IN1 IN2 OUT1 OUT2 OUT3 OUT4 IN3 IN4 GROUND STROBE IN5 IN6 OUT5 OUT6 OUT7 OUT8 IN7 IN8 LOGIC SUPPLY www.allegromicro.com 6273 8-BIT LATCHED DMOS POWER DRIVER A6273KA Dimensions in Inches (controlling dimensions) 20 11 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 BSC 10 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 0.355 0.204 20 11 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-20 mm NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6273 8-BIT LATCHED DMOS POWER DRIVER A6273KLW Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.5118 0.4961 0.050 BSC 0° TO 8° 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-20 in Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 13.00 12.60 1.27 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 6273 8-BIT LATCHED DMOS POWER DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000