A6281EESTR-T

A6281 3-Channel Constant Current LED Driver with Programmable PWM Control Features and Benefits Description ▪ ▪ ▪ ▪ ▪ ▪ ▪ The A6281 is a 3-channel constant current LED driver that has a wide range of output currents. The A6281 controls LED brightness with a Pulse Width Modulation (PWM) scheme that gives the application the capability of displaying a billion colors in an RGB cluster. The maximum current is set by an external resistor. 3 × 10-bit PWM brightness settings 3 × 7-bit dot correction current settings 5 to 17 V operation Wide output current range, 10 to 150 mA per channel Internally generated PWM clock Serial port operates at up to 5 MHz Data and clock logic architecture allows single microcontroller control of large quantities of seriallyconnected A6281s at fast data transfer rate ▪ Buffered logic outputs to drive cables ▪ Thermal shutdown and UVLO protection ▪ Power-On Reset Package: 16-terminal QFN (suffix ES) The LED brightness is controlled by performing PWM control on the outputs. The brightness data of the PWM signal for each LED is stored in three 10-bit registers. The peak value for each LED can be adjusted (dot-corrected) to compensate for mismatch, aging, and temperature effects. All the internal latched registers are loaded by a 32-bit shift register. One address bit controls whether dot correction/clock divider ratio or brightness data is loaded into the registers. The remaining bits are used for the data. The A6281 is designed to minimize the number of components needed to drive LEDs with large pixel spacing. A large number of A6281s can be daisy chained together and controlled by just four control signals (clock, serial data, latch, and output enable). Each of these inputs is buffered to drive the next chip in the chain. Also, VIN can be tied to the LED voltage supply 3 mm x 3 mm footprint Continued on the next page… Application Diagram Power Supply Bus VLED Clock Data Latch Output Enable Microprocessor Control Board Cat5 UTP VIN OutR OutG OutB Clock In Clock Out Data In Data Out Latch In Latch Out OE In OE Out VREG A6281 REXT Pixel Board #1 VLED Cat5 UTP VIN OutR OutG OutB Clock Out Clock In Data Out Data In Latch In Latch Out OE Out OE In VREG A6281 REXT Cat5 UTP Pixel Board #2 Figure 1. Functional drawing of daisy chained display application. Additional pixel boards with A6281 ICs can be applied. A6281-DS, Rev. 1 Pixel Board #N 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 Description (continued) bus, thus eliminating the need for a separate chip supply bus or an ▪ Architectural lighting external regulator. ▪ High intensity monochrome displays ▪ Large video and graphic displays Applications include: The A6281 is supplied in a 3 mm × 3 mm 16-terminal QFN (suffix ‘ES’) package, with 0.75 mm nominal overall height. The package is lead (Pb) free with 100% matte-tin leadframe plating. ▪ Colored, large-character LED signs ▪ Scrolling, colored marquees Selection Guide Part Number A6281EESTR-T Packing* Mounting 1500 pieces/reel 16 terminal QFN *Contact Allegro for additional packing options. Absolute Maximum Ratings Characteristic Load Supply Voltage Output Voltage Symbol Notes VIN OUT0, OUT1, OUT2 VOUT Rating Units 17 V –0.5 to 17 V Output Current IOUT 170 mA Ground Current IGND 600 mA VREG Pin VREG 6 V 7 V Logic Outputs VO CO, LO, OEO, SDO Logic Input Voltage Range VI CI, LI, OEI, SDI –0.3 to 7 V Operating Ambient Temperature TA Range E –40 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Thermal Characteristics Characteristic Symbol RθJA Package Thermal Resistance Test Conditions* 4-layer PCB based on JEDEC standard Rating Units 47 ºC/W *For additional information, refer to the Allegro website. Power Dissipation versus Ambient Temperature 4500 4000 Power Dissipation, PD (mW) 3500 3000 2500 4l a (R yer PC QJ A = 47 B ºC / 2000 1500 W) 1000 500 0 25 50 75 100 125 150 Temperature (°C) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 Functional Block Diagram SDI SDO Shift Register CI LI CO 100 ns One-Shot To PWM Counters LO Latched Registers 800 kHz Clock To PWM Counters OEI REXT REXT VIN OEO Current Regulator 0 Current Regulator 1 Current Regulator 2 Regulator VREG To logic OUT0 OUT1 OUT2 PGND LGND 13 SDO 14 LO 8 9 SDI 4 10 PGND 7 VIN 11 OUT1 PAD LI 3 6 LGND 12 OUT0 5 2 CI 1 OEI REXT VREG 15 OEO 16 CO Pin-out Drawings OUT2 Terminal List Table Number 1 Name REXT 2 VREG Regulator decoupling 3 LGND Logic ground 4 VIN 5 CI 6 OEI 7 LI 8 SDI Description An external resistor at this terminal establishes maximum output current Chip power supply voltage; connect to VREG externally if 4.75 V < VIN < 5.5 V Serial clock input; PWM clock if external clock is selected Output enable input; when low (active), the output drivers are enabled; when high (inactive), all output drivers are turned off (blanked) Latch input terminal; serial data is latched with high-level input Serial data input to shift register 9 OUT2 Sinking output terminal 10 PGND Power ground 11 OUT1 Sinking output terminal 12 OUT0 Sinking output terminal 13 SDO 14 LO 15 OEO 16 CO Buffered clock output – PAD Exposed thermal pad, not internally connected; connect externally to LGND and PGND. Buffered serial data output after shift register Buffered latch output Buffered output enable output Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 OPERATING CHARACTERISTICS, valid at TA = 25°C, VIN = 4.75 to 17.0 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Units ELECTRICAL CHARACTERISTICS Quiescent Supply Current IDD fCLKIN = 0.0 Hz – – 5.0 mA Operating Supply Current IDD fCLKIN = 5 MHz – – 15.0 mA Load Supply Voltage Undervoltage Lockout VIN(UV) VREG Voltage Range1 VREG Output Current (any single output) Output to Output Matching 4.75 – 17 V VIN rising – – 4.5 V VIN falling 3.0 – – V IOUT =15 mA, VIN = 17 V 4.6 – 5.4 V REXT = 5 kΩ, scalar = 100% 135 150.0 165 mA REXT = 15 kΩ, scalar = 100% 45 51 57 mA % VIN Error2 Output Voltage Range IOUT Err Load Regulation (I%Diff / ∆VDS) Output Leakage Current Logic Input Voltage REXT = 5 kΩ, VDS = 1 to 3 V Input Resistance Logic Output Voltage VOH = 17 V –7 – 7 1.0 – 3.0 V – ±1 ±3 %/V – – 1.0 μA VIH 2.0 – – V VIL – – 0.8 V – 150 – mV IDSX Logic Input Voltage Hysteresis CI and SDI Pins Logic Input Current Output to output variation—all outputs on, REXT = 5 kΩ VDS(min) All digital inputs IIN RI VOL VIN = 0 to 5 V –20 – 20 μA OEI pin, pull-up 150 300 600 kΩ LI pin, pull-down 100 200 400 kΩ – – 0.4 V 3.8 – – V VIN ≥ 5.0 V, IO = ±2 mA VOH Output Dot Correction Error REXT = 5 kΩ; LSB PWM Oscillator fPWM Thermal Shutdown Temperature TJTSD Thermal Shutdown Hysteresis TJhys Temperature increasing – ±1 – bit – 800 – kHz – 165 – °C – 15 – °C SWITCHING CHARACTERISTICS Clock Hold Time tH(CLK) 20 – – ns Data Setup Time tSU(D) 20 – – ns Data Hold Time tH(D) 20 – – ns Latch Setup Time3 tSU(LI) 20 – – ns Latch Hold Time tH(LI) 20 – – ns tSU(OE) 40 – – ns tP(OE) – 200 – ns – – 200 50 – 100 ns ns Output Enable Set Up Time Output Enable Falling to Outputs Turning On Propagation Delay Time Clock to Output Propagation Delay Time Logic Output Fall Time Logic Output Rise Time Output Fall Time (Turn Off) Output Rise Time (Turn On) Clock Falling Edge to Serial Data Out Propagation Delay Time Logic In to Output Propagation Delay Clock Out Pulse Duration Maximum Clock In Frequency tP(OUT) tBF tBR tf tr External clock selected, VDS = 1.0 V, IO = 150 mA COB = 50 pF, 4.5 to 0.5 V COB = 50 pF, 0.5 to 4.5 V – 30 60 ns COUT = 10 pF, 90% to 10% of IOUT = 10 mA – 10 – ns COUT = 10 pF, 90% to 10% of IOUT = 150 mA – 10 – ns COUT = 10 pF, 10% to 90% of IOUT = 10 mA – 50 – ns COUT = 10 pF, 10% to 90% of IOUT = 150 mA – 100 – ns – 50 – ns tP(SDO) tP(IO) – 50 – ns tw(CLK) LI→LO, CI→CO, OEI→OEO 70 100 130 ns fCI – – 6 MHz 1If VIN is a 4.75 to 5.5 V supply, connect VIN to VREG externally 2Err = [I (min or max) – I (av)] / I (av), where I (av) = average of 3 output current values. O O O O 3In daisy-chained applications, t SU(LI) must be increased for the quantity of pixels in the chain (see Application Information section). Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 CI (External Clock) tSU (D ) SDI (Serial Data In) 0 1 2 3 4 5 6 7 15 8 tw(C L K) tH( D) D31 D30 D29 D28 D27 D26 D25 D24 D23 16 31 D16 D15 D0 tP(SD O) SDO (Serial Data Out) Don’t Care D31 tSU (L I ) LI (Latch In) tH (L I ) tP(IO) LO (Latch Out) Figure 2. Serial Port Timing T1 T2 1 2 TN Internal Oscillator or CI (External Clock) PWM Counter 0 1023 0 1 2 X 0 IOUT0 Brightness Data = 0 IOUT1 Brightness Data = 1 tP(OE) tP(OUT) tP(OUT) tP(OUT) IOUT2 Brightness Data = 1022 Outputs Off OEI (Output Enable Input) Outputs On tP(IO) t w (OE) OEO (Output Enable Output) Figure 3. PWM Counter and Output Timing Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 Functional Description Shift Register The A6281 has a 32-bit shift register that loads data through the SDI (serial data in) pin. The shift register operates by a first-in first-out (FIFO) method. The most significant bit (MSB, bit 31) is the first bit shifted in and the least significant bit (LSB, bit 0) is shifted in last. The serial data is clocked by a rising edge of the CI (clock in) pin. The SDO (serial data out) pin is updated to the state of bit 31 on the falling edge of the CI pin. This will prevent any race conditions and erroneous data that might occur while propagating information through multiple A6281s that are daisy chained together. The contents of the shift register will continue to propagate on every rising edge of the CI pin. The information in the shift register is latched on a low-to-high transition of the LI (Latch In) pin. The LI pin must be brought low before the rising edge of the next clock pulse, to avoid latching erroneous data. The latched data remains latched on a rising signal on the OEI (output enable in) pin. Output Buffers The A6281 is designed to allow daisy chaining many A6281s together. It can pass the clock, data, latch, and output enable signals from one A6821 to the next without any loss of data due to duty cycle skewing or signal degradation. these signals to TTL levels. Each of the A6281 inputs has a corresponding buffered output: • CI (clock in) pin to CO (clock out) pin • LI (latch in) pin to LO (latch out) pin • OEI (output enable in) pin to OEO (output enable out) pin • SDI (serial data in) pin to SDO (serial data out) pin The CO (clock out) pin is driven by an internal one-shot circuit. When the CI pin detects an edge rising through the input threshold, the one-shot circuitry drives the CO pin high for 100 ns. The CI pin input threshold has hysteresis to prevent false triggering of the CO signal. The implementation of the one-shot solution allows many A6281s to be daisy chained together with a consistent clock signal throughout the entire chain without degradation or loss of synchronicity to the data line. PWM Brightness Control The A6281 controls the intensity of each LED by pulse width modulating the current of each output. The A6281 has three 10-bit brightness registers, one for each output. These brightness registers set the PWM count value at which the outputs switch off during each PWM cycle. Each 10-bit brightness register gives 1023 levels of light intensity. The duty cycle, DC, can be determined by the following equation: DC = [(PWMn + 1) / 1024] ×100 (%) , The A6821 is equipped with output buffers that allow the data signals to travel over long distances through strings of A6281s without the need for extra driving hardware. The A6281 drives where PWMn is the PWM value greater than zero that is stored in the brightness register. Shift Register SDI 0 to 6 7 to 8 9 10 to 16 17 to 19 20 to 26 27 28 to 29 CI 30 31 CO 100 ns One-Shot LI LO Latched Registers Current Clock Scalar 0 Mode Unused 7 Bits 2 Bits 1 Bit 800 kHz PWM Counter 0 10 Bits Current Scalar 1 7 Bits Unused 3 Bits PWM Counter 1 10 Bits Current Scalar 2 Unused 7 Bits 1 Bit Test Bits ‘’00” PWM Counter 2 10 Bits Address Unused Bit 1 Bit “1” Address Unused Bit 1 Bit “0” OEI OEO REXT Current Regulator 0 REXT VIN SDO Current Regulator 1 Current Regulator 2 +5V Regulator VREG OUT0 OUT1 OUT2 PGND LGND Figure 4. Functional Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 The relationship of the PWMn value to the output duty cycle is given in the following table: PWMn Output Current Selection The overall maximum current is set by the external resistor, REXT , connected between the REXT and LGND pins. After being set, the maximum current remains constant regardless of the LED voltage variation, supply voltage variation, temperature, or other circuit parameters. The maximum output current can be calculated using the following equation: Duty Cycle 0 1 2 ... 0/1024 (0 %) 2/1024 3/1024 ... 1023 1024/1024 (100 %) When the brightness register is set to zero, the outputs remain off for the duration of the PWM cycle for a 0% DC. When a brightness register is set to 1023, the LED for that output remains on (100% DC) when OEI is active and begins the PWM cycle. The output remains on when the PWM counter rolls over and begins a new count. The PWM counter begins counting at zero and increments only when the OEI pin is held low. When the PWM counter reaches the count of 1024, the counter resets to zero and continues incrementing. The counter resets to zero on a rising edge of OEI, upon recovery from UVLO, or when powering up. Latching new data into the brightness registers will not reset the PWM counter. Bits 7 0 1 8 0 0 0 1 1 1 The relationship of the value selected for REXT and IOUT is shown in figure 6. Internal Linear Regulator The A6281 has a built-in linear regulator. The regulator operates from a supply voltage of 5.5 to 17 V. It allows the VIN pin of the A6281 to connect to the same supply as the LEDs. This simplifies board design by eliminating the need for a chip supply bus and external voltage regulators. For 5 V supplies, connect VIN to VREG externally. Note: When using 5 V supplies, ensure that VIN does not exceed the absolute maximum rating of the VREG pin (6 V). The VREG pin is used by the internal linear regulator to connect to a bypass capacitor. This pin is for internal use only and is not IOUT (mA) A free-running internal 800 kHz oscillator is the master clock for the PWM counter. A programmable clock divider frequency allows the PWM to be set at approximately at 200 kHz, 400 kHz, or 800 kHz, or the PWM can be set to count on the rising edge of the external CI signal. Bit assignments for the programmable clock divider are shown in the following table: IOUT(max) = 753.12 / REXT. Clock Mode 800 kHz 400 kHz External (count on rising edge of CI signal) 200 kHz The total number of possible colors of an RGB pixel is over 1 billion. Refer to figure 4 for the mapping of shift register bits to latches. 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 5 15 25 35 45 REXT (kΩ) 55 65 75 Figure 6. Output Current versus External Resistor, REXT Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PWM Counter 0 Dot Correction Register 0 aSelects cAllegro Clock Mode PWM Counter 1 X Dot Correction Register 1 X X X PWM Counter 2 Dot Correction Register 2 28 29 30a 31 Address “0” Xb X ATBc ATBc Address “1” X which word is written to: Dot Correction/Clock Mode selection or PWM counter. bX indicates “Don’t Care.” Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application. Figure 5. Register Configuration Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 intended as an external power source. There should be a 1.0 μF, 10 V ceramic capacitor connected between the VREG pin and LGND. The capacitor should be located as close to the VREG pin as possible. The actual package power dissipation is: Dot Correction Control where DCi is the PWM duty cycle for channel i, and IOUTi is the output current for channel i, determined by the dot correction current for that channel and REXT. The A6281 can further control the maximum output current for each output by setting the three 7-bit dot correction registers with scale data that ranges from 36.5% to 100% of the overall maximum output current that is set by the REXT resistor. This feature is useful because not every type of LED (red, green, or blue, for example) has the same level of brightness for a given current, and the brightness could be different even from LED to LED of the same type. By scaling the output currents so that all the LEDs have matched intensities, the application will have full color depth when using the PWM counters. The dot correction current can be calculated by the following equation: IOUTn = IOUTn(max) × (Scalen / 2 + 36.5) / 100 Where Scalen is in the range 0 to 127, as shown in the following table: Scale IOUT/IOUT(max) (%) 0 1 36.5 37.0 2 ... 37.5 ... 127 100 Refer to figure 5 for the bit configurations for the scalar registers. The dot correction data in the shift register is latched on a rising edge of the LI pin. The dot correction data remains latched on a rising OEI signal. The default output current when the A6281 is powered-up or recovers from a UVLO is 36.5% of the current set by the REXT resistor. Package Power Dissipation The maximum allowable package power dissipation is determined as: PD(max) = (150 – TA) / RJA . PD(act) = DC0 × VDS0 × IOUT0 + DC1 × VDS1 × IOUT1 + DC2 × VDS2 × IOUT2 + VIN × IIN , When calculating power dissipation, the total number of available device outputs is usually used for the worst-case situation (3 LEDs at 100% duty cycle). Thermal Shutdown (TSD) When the junction temperature of the A6281 reaches the thermal shutdown temperature threshold, TJTSD (165°C typical), the outputs will shut off until the junction temperature cools down below the recovery threshold, TJTSD –∆TJ ( 15°C typical). The shift register and output latches will remain active during the TSD event. Therefore there is no need to reload the data into the output latches. Undervoltage Lockout The A6281 includes an internal undervoltage lockout (UVLO) circuit that disables the driver outputs in the event of the logic supply voltage dropping below a minimum acceptable level. This prevents the display of erroneous information, a necessary function for some critical applications. The shift register will not shift any data in a UVLO condition. Upon recovery of the logic supply voltage and on power up, the internal shift register and all latches will be set to zero. Ballast Resistors The voltage on the outputs should be kept in the range 1 to 3 V. If the voltage goes below 1V, the current will begin to rolloff as the driver runs out of headroom. At VOUT above 3 V, the power dissipation may become a problem, as each output contributes VOUT × ILED of power loss in the output sink driver. Typically the power supply nominal voltage is chosen to keep the output voltage in this range. Alternatively, series resistors can be added to dissipate the extra power and keep the output voltage within the recommended range. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 Application Information Timing Considerations A6281s can be used in large numbers to drive many LEDs with the control signals connected serially together using short cables between each pixel (see figure 8). Because the clock negative edge drives the data to the SDO pin, and the CO pin is driven by a 100 ns one-shot function, the clock and data signals remain synchronized with each other from the first pixel in the chain to the last. After all of the data is written to each A6281 in the chain, the data is latched into each A6281 via a low-to-high transition on the LI pin. The LO pin of pixel #1 drives the LI pin of pixel #2, and so on down the chain. These signals are buffered and are driven asynchronously relative to the CI and SDI pins. Therefore the mismatch in delays between CO and LO must be taken into consideration. Although the mismatches in delays are quite small, they must be considered when creating the timing pattern for driving the chain. The key parameter is the setup time from the last CI clock rising edge to the rising edge of LI. The minimum A6281 setup time from CI to LI is 20 ns. There may be a 5 ns per pixel mismatch in the propagation delays of the CI and LI signals (the delay from CI to CO compared to the delay from LI to LO). As a rule of thumb, use a setup time, tsu , at the first A6281 in the chain as calculated below: tsu = 20 ns + n × 5 ns , where n is the number of pixels in the chain. This will ensure that the setup time at the last pixel in the chain is at least 20 ns. tsu CI(1) to CI(n) CI(1) LI(1) to LI(n) CO(1) = CI(2) CO(2) = CI(3) CO(n-1) = CI(n) LI (1) LO (1) = LI (2) LO (2) = LI (3) LO (n -1) = LI (n ) Figure 7. Signal Delay Mismatch Timing Diagram. tsu is the setup time for signals (CI to LI) applied to the first pixel in the chain. Note the difference in delay for CI(1) to CI(n) compared to the delay for LI(1) to LI(n). This must be compensated by increasing tsu. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 Applications Drawings + CI OEI LI SDI VIN Output Enable PAD LGND Latch Tie LGND and PGND to PAD externally CO OEO LO SDO A6281 A6281 REXT Clock Data VREG System Logic VOn 1 to 3 V OUT0 OUT2 – Red LEDs Green LEDs OUT1 Blue LEDs 10 μF PGND 8.5 V 1 μF X5R Maximum of 250 pixels 10 kΩ Figure 8. Application driving 3 RGB LED strings, each at 75 mA maximum 10 V + 10 μF 2Ω 0.5 W VOn 1 to 3 V SDI Tie LGND and PGND to PAD externally OUT0 OUT1 PAD CO OEO LO SDO A6281 REXT Output Enable A6281 VREG Latch CI OEI LI LGND Clock Data VIN System Logic PGND OUT2 – 1 μF 10 V 5 kΩ Maximum of 250 pixels Figure 9. Application driving high power LEDs at 450 mA total Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 3-Channel Constant Current LED Driver with Programmable PWM Control A6281 ES Package, 16 Pin QFN 0.30 3.00 ±0.15 0.90 16 1 2 A 0.50 16 1 3.00 ±0.15 1.70 3.10 1.70 17X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 C 3.10 C PCB Layout Reference View 0.75 ±0.05 0.50 For reference only (reference JEDEC MO-220WEED) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown +0.15 0.40 –0.10 A Terminal #1 mark area B 1.70 2 1 16 1.70 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P300X300X80-17W4M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2006-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11