A6595KLWTR

A6595 8-Bit Serial Input DMOS Power Driver Discontinued Product These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available. Date of status change: May 3, 2010 Recommended Substitutions: For existing customer transition, and for new customers or new applications, refer to your Allegro sales representative. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A6595 8-Bit Serial Input DMOS Power Driver Features and Benefits Description ▪ 50 V minimum output clamp voltage ▪ 250 mA output current (all outputs simultaneously) ▪ 1.3 Ω typical rDS(on) ▪ Low power consumption ▪ Replacements for TPIC6595N and TPIC6595DW The A6595 combines an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serialdata input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. The A6595 DMOS open-drain outputs are capable of sinking up to 750 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. Package: 20-pin DIP (suffix A) The A6595 is furnished in a 20-pin dual in-line plastic package that is lead (Pb) free, with 100% matte tin leadframe plating. Copper leadframe base material, reduced supply current requirements, and low on-state resistance allow the device to sink 150 mA from all outputs continuously, to ambient temperatures to 125°C. Not to scale Pin-out Diagram 26185.120a POWER GROUND 1 LOGIC SUPPLY 2 SERIAL DATA IN 20 POWER GROUND 19 LOGIC GROUND 3 18 SERIAL DATA OUT OUT 0 4 17 OUT 7 OUT 1 5 16 OUT 6 OUT 2 6 15 OUT 5 OUT 3 7 14 OUT 4 CLK 13 CLOCK ST 12 STROBE 11 POWER GROUND 8 CLR OUTPUT ENABLE 9 OE POWER GROUND 10 LATCHES REGISTER LATCHES REGISTER CLEAR REGISTER V DD A6595 8-Bit Serial Input DMOS Power Driver Selection Guide Part Number A6595KA-T Packing 18 pieces per tube Absolute Maximum Ratings* Characteristic Symbol Notes Rating Units Logic Supply Voltage VDD 7.0 V Input Voltage Range VI –0.3 to 7.0 V Output Voltage VO Output Drain Current Single-Pulse Avalanche Energy 50 V IO Continuous, each output, all outputs on 250 mA IOM Pulsed tw ≤100 μs, duty cycle ≤ 2%; each output, all outputs on 750 mA Pulsed tw ≤100 μs, duty cycle ≤ 2%; 2.0 A 75 mJ EAS Operating Ambient Temperature TA –40 to 125 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Range K *These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol RθJA Package Thermal Resistance Test Conditions* On 4-layer PCB based on JEDEC standard Value Units 32 ºC/W ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS *Additional thermal information available on the Allegro website. 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 50 75 100 AMBIENT TEMPERATURE 125 oC) 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A6595 8-Bit Serial Input DMOS Power Driver Functional Block Diagram REGISTER CLEAR (ACTIVE LOW) V DD CLOCK SERIAL DATA IN SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER STROBE LOGIC SUPPLY D-TYPE LATCHES OUTPUT ENABLE (ACTIVE LOW) LOGIC GROUND POWER GROUND POWER GROUND OUT 0 OUT N Dwg. FP-013-5 Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally. Device Logic Diagram 9 12 G3 C2 SRG8 8 13 R 3 1D C1 2 4 5 6 7 14 15 16 2 17 18 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A6595 8-Bit Serial Input DMOS Power Driver OU T V DD IN Dwg. EP-063-3 Dwg. EP-010-1 5 LOGIC INPUTS DMOS POWER DRIVER OUTPUT V DD RECOMMENDED OPERATING CONDITIONS OU T over operating temperature range Logic Supply Voltage Range, V DD ............... 4.5 V to 5.5 V High-Level Input Voltage, V IH ............................ ≥ 0.85VDD Low-level input voltage, V IL ................................. ≤0.15VDD Dw g. EP-063-2 SERIAL DATA OUT TRUTH TABLE Shift Register Contents Data Clock Input Input I0 I1 I2 ... I6 H H R0 R1 … R5 R6 R6 L L R0 R1 … R5 R6 R6 R0 R1 R2 … R6 R7 R7 X X … X X X P0 P1 P2 … P6 P7 P7 X L = Low Logic Level X I7 Serial Data Output Strobe H = High Logic Level — X = Irrelevant Latch Contents I0 I1 ... I6 R0 R1 R2 … R6 R7 P0 P1 P2 … P6 P7 L P0 P1 P2 … P6 P7 X … X H H … H X I2 Output Contents X P = Present State I7 Output Enable X I0 I1 H I2 H … I6 I7 H R = Previous Stat e Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A6595 8-Bit Serial Input DMOS Power Driver ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). Limits Characteristic Symbol Test Conditions Output Breakdown Voltage V(BR)DSX IDSX Off-State Output Current Static Drain-Source On-State Resistance rDS(on) Min. Typ. Max. Units I O = 1 mA 50 — — V VO = 40 V — 0.05 1.0 μA VO = 40 V, T A = 125°C — 0.15 5.0 μA IO = 250 mA, V DD = 4.5 V — 1.3 2.0 Ω IO = 250 mA, V DD = 4.5 V, TA = 125°C — 2.0 3.2 Ω IO = 500 mA, V DD = 4.5 V (see note) — 1.3 2.0 Ω Nominal Output Current ION VDS(on) = 0.5 V, TA = 85°C — 250 — mA Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 μA IIL VI = 0, VDD = 5.5 V — — -1.0 μA — 1.3 — V IOH = -20 μA, VDD = 4.5 V 4.4 4.49 — V IOH = -4 mA, V DD = 4.5 V 4.1 4.3 — V IOL = 20 μA, VDD = 4.5 V — 0.002 0.1 V IOL = 4 mA, V DD = 4.5 V — 0.2 0.4 V tPLH IO = 250 mA, C L = 30 pF — 650 — ns tPHL IO = 250 mA, C L = 30 pF — 150 — ns Output Rise Time tr IO = 250 mA, C L = 30 pF — 7500 — ns Output Fall Time tf IO = 250 mA, C L = 30 pF — 425 — ns IDD(OFF) All inputs low — 15 100 μA IDD(ON) VDD = 5.5 V, Outputs on — 150 300 μA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs off — 0.6 5.0 mA Logic Input Hysteresis SERIAL-DATA Output Voltage VI(hys) VOH VOL Prop. Delay Time Supply Current TypicalDataisatV DD = 5 V andisfordesign information only . NOTE — Pulse duration ≤100 duty cycle ≤2% . Typical Datatest, is at VDD = 5μs, V and is for design information only. NOTE — Pulse test, duration ≤100 μs, duty cycle ≤2%. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A6595 8-Bit Serial Input DMOS Power Driver TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA NI B DATA 50% tp SERIAL DATA OUT DATA 50% D E STROBE 50% OUTPUT ENABLE LOW = ALL OUTPUTS ENABLED tp HI GH = OUTPUTOFF DATA 50% OU T N LOW = OUTPUTN O Dwg. WP-029-2 HIGH = ALL OUTPUTS DISABLED OUTPUT ENABLE 50% tPLH tPHL tf tr 90% OU T N DATA 10% Dwg. WP-030-2 A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 10 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 10 ns C. Clock Pulse Width, tw(CLK) ............................................. 20 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) ............................................... 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 μs NOTE – Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A6595 8-Bit Serial Input DMOS Power Driver TEST CIRCUITS +15 V 0.11Ω INPUT 100 mH tav IAS = 1.0 A IO DUT OU T VO V (BR)DS X V O(ON) Dwg. EP-066-1 EAS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A6595 8-Bit Serial Input DMOS Power Driver TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 POWER GROUND 2 LOGIC SUPPLY 3 SERIAL DATA IN 4-7 OUT0-3 Current-sinking, open-drain DMOS output terminals. 8 CLEAR When (active) low, the registers are cleared (set low). 9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 10 POWER GROUND Reference terminal for output voltage measurements (OUT0-3). 11 POWER GROUND Reference terminal for output voltage measurements (OUT0-7). 12 STROBE Data strobe input terminal; shift register data is latched on rising edge. 13 CLOCK Clock input terminal for data shift on rising edge. 14-17 OUT4-7 Current-sinking, open-drain DMOS output terminals. 18 SERIAL DATA OUT 19 LOGIC GROUND Reference terminal for input voltage measurements. 20 POWER GROUND Reference terminal for output voltage measurements (OUT4-7). Reference terminal for output voltage measurements (OUT0-3). (VDD) The logic supply voltage (typically 5 V). Serial-data input to the shift-register. CMOS serial-data output to the following shift register. NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A6595 8-Bit Serial Input DMOS Power Driver Package A, 20-Pin DIP +0.76 26.16 –1.27 20 +0.10 0.38 –0.05 +0.76 6.35 –0.25 +0.38 10.92 –0.25 7.62 A 1 2 5.33 MAX SEATING PLANE C +0.51 3.30 –0.38 2.54 +0.25 1.52 –0.38 0.46 ±0.12 Preliminary dimensions, for reference only Dimensions in inches Metric dimensions (mm) in brackets, for reference only (reference JEDEC MS-001 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Copyright ©2000-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9