A6810EEP

6809 AND 6810 A6810xA DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS The A6809– and A6810– devices combine 10-bit CMOS shift registers, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6809– and A6810– feature an increased data input rate (compared with the older UCN/UCQ5810-F) and a controlled output slew rate. The A6809xLW and A6810xLW are identical except for pinout. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are avail-able as the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits). The A6809– and A6810– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. All devices are available in two temperature ranges for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. The A6810– is provided in three package styles for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). The A6809– is provided in the SOIC (suffix -LW) only. Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow all devices to source 25 mA from all outputs continuously over the maximum operating temperature range. Data Sheet 26182.124B OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES 18 17 16 VBB 15 14 BLNK 13 12 11 10 OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3 Dwg. PP-029 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix ‘E–’) .................. -40°C to +85°C (Suffix ‘S–’) .................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +125°C FEATURES I Controlled Output Slew Rate I Low Output-Saturation Voltages I High-Speed Data Storage I Low-Power CMOS Logic I 60 V Minimum and Latches Output Breakdown I Improved Replacements I High Data Input Rate for TL4810–, UCN5810–, I PNP Active Pull-Downs and UCQ5810– Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6810SLW . Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. 6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS TYPICAL OUTPUT DRIVER V BB TYPICAL INPUT CIRCUIT VDD OUTN IN Dwg. EP-021-19 A6809xLW Dwg. EP-010-5 OUT 8 OUT 7 OUT 6 CLOCK GROUND NO CONNECTION LOGIC SUPPLY STROBE OUT 5 OUT 4 1 2 3 LATCHES 4 5 6 7 8 9 10 NC VDD ST REGISTER LATCHES CLK REGISTER V 20 19 NC 18 17 16 15 BLNK 14 13 12 11 OUT 9 OUT 10 NO CONNECTION SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3 CLOCK NC GROUND LOGIC SUPPLY STROBE 4 5 6 7 8 V DD ST CLK A6810xEP OUT10 20 19 2 1 OUT 6 3 18 LATCHES REGISTER V BB 17 16 REGISTER 15 LATCHES BLNK 14 BB SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKING 12 10 11 OUT 5 OUT1 13 9 Dwg. PP-029-9 Dwg. PP-059 A6810xLW ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 SUFFIX 'EP', R θJA = 59°C/W OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 NO CONNECTION 1 2 3 LATCHES 4 5 6 7 8 9 10 NC VDD ST CLK REGISTER REGISTER LATCHES 20 19 18 VBB 17 16 BLNK 15 14 13 12 NC 11 OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3 NO CONNECTION 2.0 SUFFIX 'A', R θJA = 60°C/W 1.5 1.0 0.5 SUFFIX 'LW', R θJA = 70°C/W 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. PP-029-2 Dwg. GP-024-1 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2000 Allegro MicroSystems, Inc. 6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER LATCHES BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State www.allegromicro.com 6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C (A6809SLW & A6810S-) or over operating temperature range (A6809ELW & A6810E-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) ten(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF IOUT = ±200 µA VIN = VDD VIN = 0 V IIN = -200 µA IOUT = -200 µA IOUT = 200 µA Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. — 57.5 — 2.5 2.2 — — — — 2.8 — 10 — — — — — — — — 2.4 2.4 4.0 — Typ.