A6812SA

Data Sheet 26182.126A 6812 A6812xA LOAD SUPPLY SERIAL DATA OUT OUT 20 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 BLANKING GROUND 1 2 3 4 5 6 VBB VDD 28 27 26 25 24 23 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK DABiC-IV, 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER The A6812– devices combine a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6812– features an increased data input rate (compared with the older UCN/UCQ5812-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, they will operate to at least 10 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32 bits). The A6812– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these drivers to source 25 mA from all outputs continuously to more than +43°C (suffix -LW), +61°C (suffix -EP), or +77°C (suffix -A). REGISTER REGISTER LATCHES LATCHES 7 8 9 10 11 12 13 14 BLNK 22 21 20 19 18 17 ST CLK 28 16 27 15 Dwg. PP-029-7 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix ‘E–’) .................. -40°C to +85°C (Suffix ‘S–’) .................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +125°C Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. FEATURES I Controlled Output Slew Rate I Low Output-Saturation Voltages I High-Speed Data Storage I Low-Power CMOS Logic I 60 V Minimum and Latches Output Breakdown I Improved Replacements I High Data Input Rate for TL5812–, UCN5812–, I PNP Active Pull-Downs and UCQ5812– Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6812SLW . 6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6812xEP SERIAL DATA OUT LOGIC SUPPLY LOAD SUPPLY SERIAL DATA IN OUT20 OUT19 OUT 1 LOAD SUPPLY SERIAL DATA OUT OUT 20 1 2 3 4 5 6 REGISTER REGISTER LATCHES LATCHES 7 8 9 10 11 12 13 14 BLNK ST CLK VBB A6812xLW VDD 28 27 26 25 24 23 22 21 20 19 18 17 28 16 27 15 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK V DD 28 VBB 27 26 4 3 2 1 OUT18 5 6 25 24 OUT 2 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 REGISTER LATCHES LATCHES 7 8 9 10 OUT12 11 REGISTER 23 22 21 20 19 OUT 8 OUT 13 OUT 12 CLK 12 14 ST 17 13 15 16 18 OUT11 GROUND BLANKING STROBE CLOCK OUT 10 OUT9 OUT 11 BLANKING Dwg. PP-059-1 GROUND TYPICAL INPUT CIRCUIT Dwg. PP-029-8 VDD ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 SU FF IX IN 2.0 'E P' ,R 1.5 SU FF IX IX FF SU ', R 'A θJ θJ A = 55 °C /W A = /W °C 45 Dwg. EP-010-5 'LW ', R θJ TYPICAL OUTPUT DRIVER V BB 1.0 A= 66 °C /W 0.5 OUTN 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. EP-021-19 Dwg. GP-024-2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. 6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER LATCHES BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State www.allegromicro.com 6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature range (A6812E-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) ten(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF IOUT = ±200 µA VIN = VDD VIN = 0 V IIN = -200 µA IOUT = -200 µA IOUT = 200 µA Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. — 57.5 — 2.5 2.2 — — — — 2.8 — 10* — — — — — — — — 2.4 2.4 4.0 — Typ.