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A6818KEP-T

A6818KEP-T

  • 厂商:

    ALLEGRO(埃戈罗)

  • 封装:

  • 描述:

    A6818KEP-T - DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER - Allegro MicroSystems

  • 数据手册
  • 价格&库存
A6818KEP-T 数据手册
6818 A6818xEP DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER The A6818– devices combine a 32-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and 40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6818– features an increased data input rate (compared with the older UCN/UCQ5818–F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6810– (10 bits) and A6812– (20 bits). The A6818– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (E-), and extended industrial (K-) applications. The package style provided is the minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. The lead (Pb) free versions have 100% matte tin leadframe plating. Data Sheet 26182.128D 44 43 42 41 7 8 9 10 11 12 13 14 15 16 17 21 22 23 24 25 26 27 18 19 20 28 40 6 5 4 3 2 1 39 38 37 36 35 34 33 32 31 30 29 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD .................. 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix ‘E–’) .................. -40°C to +85°C (Suffix ‘K–’) ................ -40°C to +125°C (Suffix ‘S–’) .................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +125°C Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. FEATURES ■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818– Always order by complete part number: Part Number A6818EEP A6818EEP-T A6818EEPTR A6818EEPTR-T A6818KEP A6818KEP-T A6818KEPTR A6818KEPTR-T A6818SEP A6818SEP-T A6818SEPTR A6818SEPTR-T Pb-free – Yes – Yes – Yes – Yes – Yes – Yes Packing 27 pieces/tube –40 to 85 450 pieces/13-in. reel 27 pieces/tube –40 to 125 450 pieces/13-in. reel 27 pieces/tube –20 to 85 450 pieces/13-in. reel Ambient Temperature, TA (°C) 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER TYPICAL INPUT CIRCUIT OUT30 OUT31 A6818xEP SERIAL DATA OUT LOAD SUPPLY LOGIC SUPPLY SERIAL DATA IN OUT 1 V DD 44 43 OUT 2 41 NC VBB 42 40 6 3 5 4 2 1 OUT3 VDD OUT32 OUT29 7 8 9 10 REGISTER REGISTER LATCHES 2 39 38 37 36 OUT 4 IN LATCHES 11 12 Dwg. EP-010-5 35 34 33 19 32 31 30 OUT13 NC 13 14 15 16 OUT19 17 OUT 8 BLNK 29 CLK ST 20 27 OUT14 18 19 23 24 25 BLANKING 21 GROUND 22 OUT17 STROBE OUT15 26 NC OUT18 OUT 16 CLOCK NC 28 Dwg. PP-059-2 TYPICAL OUTPUT DRIVER V BB 3.0 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 OUTN 2.0 Dwg. EP-021-19 1.5 SUFFIX 'EP', RθJA = 54°C/W 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-025B 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2003 Allegro MicroSystems, Inc. 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER LATCHES BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) ten(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF IOUT = ± 200 µA VIN = VDD VIN = 0.8 V IIN = -200 µA IOUT = -200 µA IOUT = 200 µA Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. — 57.5 — 2.5 2.2 — — — — 2.8 — 10 — — — — — — — — 2.4 2.4 4.0 — Typ.
A6818KEP-T 价格&库存

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