A6832SEP-T

A6832 DABiC-5 32-Bit Serial Input Latched Sink Drivers Last Time Buy This part is in production but has been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and notice has been given. Sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Date of status change: November 1, 2010 Deadline for receipt of LAST TIME BUY orders: April 30, 2011 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A6832 DABiC-5 32-Bit Serial Input Latched Sink Drivers Features and Benefits Description ▪ 3.3 to 5 V logic supply range ▪ To 10 MHz data input rate ▪ Schmitt trigger inputs for improved noise immunity ▪ Low-power CMOS logic and latches ▪ 40 V current sink outputs ▪ Low saturation voltage ▪ –40°C operation available Intended originally to drive thermal printheads, the A6832 has been optimized for low output-saturation voltage, high-speed operation, and pin configurations that are the most convenient for the tight space requirements of high-resolution printheads. These integrated circuits can also be used to drive multiplexed LED displays or incandescent lamps at up to 125 mA peak current. The combination of bipolar and MOS technologies gives the A6832 arrays an interface flexibility beyond the reach of standard buffers and power driver circuits. Applications: ▪ Thermal printheads ▪ Multiplexed LED displays ▪ Incandescent lamps The devices each have 32 bipolar NPN open-collector saturated drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS shift registers, and CMOS control circuitry. The highspeed CMOS shift registers and latches allow operation with most microprocessor-based systems. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high. MOS serial data outputs permit cascading for interface applications requiring additional drive lines. 40 41 42 1 43 44 2 3 4 5 6 Package: 44-pin PLCC (suffix EP) 7 39 8 38 9 37 The A6832 is supplied in a 44-lead plastic leaded chip carrier, for surface-mount applications requiring minimum area. These devices are lead (Pb) free, with 100% matte tin plated leadframes. 28 27 29 26 30 17 25 31 16 24 15 23 32 22 33 14 21 34 13 20 35 19 36 12 18 10 11 Not to scale Functional Block Diagram V DD C LOC K S E R IAL DATA IN S E R IAL DATA OUT 32-B IT S HIF T R E G IS T E R S T R OB E LAT C HE S OUT P UT E NAB LE MOS B IP OLAR OUT1 26185.110G OUT 2 OUT3 G R OUND OUT 30 OUT31 OUT32 A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Selection Guide Part Number Packing Operating Temperature (ºC) A6832EEPTR-T 450 pieces per reel –20 to 85 A6832SEPTR-T 450 pieces per reel –40 to +85 Package 44-pin PLCC Absolute Maximum Ratings Characteristic Symbol Logic Supply Voltage VDD Input Voltage Range VIN Notes Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. Rating Unit 7 V –0.3 to VDD + 0.3 V Output Voltage VOUT 40 V Continuous Output Current IOUT 125 mA Package Power Dissipation PD See Allowable Power Dissipation chart. – – Range E –40 to 85 ºC Range S Operating Ambient Temperature TA –20 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Storage Temperature Tstg –55 to 150 ºC Allowable Power Dissipation, PD* 4.5 PACKAGE POWER DISSIPATION (W) 4.0 3.5 3.0 A6832EP, RθJA = 30 °C/W 2.5 2.0 1.5 1.0 A6832EP, RθJA = 54 °C/W 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE (º C) 150 *Additional thermal information is available on the Allegro Web site. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Vdd = 3.3 V Characteristic Typ. Max. Min. Typ. Max. VOUT = 40 V – – 10 – – 10 μA IOUT = 50 mA – – 275 – – 275 mV Symbol Output Leakage Current ICEX Collector–Emitter Saturation Voltage VCE(SAT) Input Voltage Input Current Serial Data Output Voltage Test Conditions IOUT = 100 mA – – 550 – – 550 mV 2.2 – – 3.3 – – V VIN(0) – – 1.1 – – 1.7 V – < 0.01 1.0 – < 0.01 1.0 μA IIN(1) VIN = VDD IIN(0) VIN = 0 V – < –0.01 –1.0 – < –0.01 –1.0 μA VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V 10 – – 10 – – MHz fc Output Enable-to-Output Delay Units VIN(1) Maximum Clock Frequency2 Logic Supply Current Vdd = 5 V Min. IDD(1) One output on, IOUT = 100 mA – – 6.0 – – 6.0 mA IDD(0) All outputs off – – 100 – – 100 μA tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time tf VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Rise Time tr VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs IOUT = ±200 μA – 50 – – 50 – ns Strobe-to-Output Delay Clock-to-Serial Data Out Delay 1Positive tp(CH-SQX) (negative) current is defined as conventional current going into (coming out of) the specified device pin. at a clock frequency greater than the specified minimum value is possible but not warranteed. 2Operation Truth Table Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Input Output Contents I1 I2 I3 ... IN-1 I N H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN H P1 P2 P3 ... PN-1 PN X X L H H H ... H X X ... P1 P2 P3 ... X PN-1 PN X X ... X H L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) C 50% C LOC K A S E R IAL DAT A IN B DAT A 50% t p(C H-S QX) S E R IAL DAT A OUT DAT A 50% D E 50% S T R OB E OUT P UT E NAB LE HIG H = ALL OUT P UT S E NAB LE D t p(S TH-QH) t p(S T H-QL) 90% DAT A OUT N 10% LOW = ALL OUT P UT S B LANK E D (DIS AB LE D) OUT P UT E NAB LE 50% t en(B Q) tr tf t dis (B Q) OUT N 90% 10% Key Description A Data Active Time Before Clock Pulse (Data Set-Up Time) B DAT A 50% Symbol tsu(D) Time (ns) Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50 NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The 25 latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input high, the outputs are controlled by the state of their respective latches. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers OUTPUT ENABLE OUT32 NC 41 40 LOGIC SUPPLY VDD 1 42 SERIAL DATA IN 2 CLOCK GROUND 3 SERIAL DATA OUT32 STROBE 43 NC 5 4 44 OUT1 7 39 OUT31 8 38 9 37 13 36 LATCHES 12 SHIFT REGISTER 11 LATCHES 10 SHIFT REGISTER OUT 2 6 Pin-out Diagram 35 34 33 14 32 15 31 16 30 29 OUT21 NC 28 OUT 20 27 26 25 OUT 17 24 23 NC OUT 16 22 21 20 OUT 13 19 NC 18 OUT12 17 Typical Output Driver Typical Input Circuit VDD VDD OUT IN Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Package EP, 44-pin PLCC 17.53 ±0.13 16.59 ±0.08 0.51 2 1 44 7.75 ±0.36 A 17.53 ±0.13 16.59 ±0.08 7.75 ±0.36 0.74 ±0.08 4.57 MAX 44X SEATING PLANE 0.10 C 0.43 ±0.10 C 1.27 7.75 ±0.36 For Reference Only (reference JEDEC MS-018 AC) Dimensions in millimeters 7.75 ±0.36 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Copyright ©2003-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6