A6B595KLWTR-T

A6B595 8-Bit Serial-Input DMOS Power Driver Last Time Buy This part is in production but has been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and notice has been given. Sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Date of status change: May 3, 2010 Deadline for receipt of LAST TIME BUY orders: October 29, 2010 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A6B595 8-Bit Serial-Input DMOS Power Driver Features and Benefits ▪ 50 V minimum output clamp voltage ▪ 150 mA output current (all outputs simultaneously) ▪ 5  typical rDS(on) ▪ Low power consumption ▪ Replacement for TPIC6B595N and TPIC6B595DW Description The A6B595 combines an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serialdata input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. Similar devices with reduced rDS(on) are available as the A6595. Packages: 18-pin DIP (A package) Not to scale 20-pin SOICW (LW package) The A6B595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C. The A6B595 is furnished in a 20-pin dual in-line plastic package and a 20-pin wide-body, small-outline plastic package (SOICW) with gull-wing leads. The Pb (lead) free versions (suffix -T) have 100% matte tin leadframe plating. Functional Block Diagram Grounds (terminals 10, 11, and 19) must be connected together externally. 26185.122G A6B595 8-Bit Serial-Input DMOS Power Driver Selection Guide Part Number A6B595KA-T A6B595KLWTR-T Package Packing 18-pin DIP 20-pin SOICW 18 pieces per tube 1000 pieces per reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Logic Supply Voltage VDD 7 V Output Voltage VO 50 V Input Voltage Range VI Output Drain Current –0.3 to 7.0 V IO Continuous; each output, all outputs on 150 mA IOM Peak; pulse duration 100 μs, duty cycle 2% 500 mA Single-Pulse Avalanche Energy EAS Operating Ambient Temperature TA Maximum Junction Temperature 30 mJ –40 to 85 ºC TJ(max) 150 ºC Tstg –65 to 150 ºC Storage Temperature Range K Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Thermal Characteristics Characteristic Symbol RθJA Package Thermal Resistance Test Conditions* Value Units Package A, 1-layer PCB with copper limited to solder pads 65 ºC/W Package LW, 1-layer PCB with copper limited to solder pads 90 ºC/W ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS *Additional thermal information available on the Allegro website 2.5 2.0 SU FF IX 1.5 'A ', R QJ SU FF IX 'LW ', R 1.0 QJ A A = 65 oC /W =9 0oC /W 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN oC 150 Dwg. GS-004A Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A6B595 8-Bit Serial-Input DMOS Power Driver PIN-OUT DIAGRAM NO CONNECTION 1 NC LOGIC SUPPLY 2 VDD 19 GROUND SERIAL DATA IN 3 18 SERIAL DATA OUT OUT 0 4 17 OUT 7 OUT 1 5 16 OUT 6 OUT 2 6 15 OUT 5 OUT 3 7 REGISTER CLEAR 8 CLR OUTPUT ENABLE 9 OE GROUND 10 NC CLK ST 20 NO CONNECTION 14 OUT 4 13 CLOCK 12 STROBE 11 GROUND Dwg. PP-029-12 Note that the A package (DIP) and the LW package (SOIC) are electrically identical and share a common terminal number assignment. TERMINAL DESCRIPTIONS Terminal No. 1 Terminal Name NC Function No internal connection. 2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V). 3 SERIAL DATA IN Serial-data input to the shift-register. 4-7 OUT0-3 Current-sinking, open-drain DMOS output terminals. 8 CLEAR When (active) low, the registers are cleared (set low). 9 OUTPUT ENABLE 10 GROUND Reference terminal for output voltage measurements (OUT0-3). 11 GROUND Reference terminal for output voltage measurements (OUT0-7). 12 STROBE Data strobe input terminal; shift register data is latched on rising edge. 13 CLOCK Clock input terminal for data shift on rising edge. 14-17 OUT4-7 Current-sinking, open-drain DMOS output terminals. 18 SERIAL DATA OUT 19 GROUND 20 NC When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). CMOS serial-data output to the following shift register. Reference terminal for input voltage measurements. No internal connection. NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A6B595 8-Bit Serial-Input DMOS Power Driver LOGIC INPUTS DMOS POWER DRIVER OUTPUT SERIAL DATA OUT RECOMMENDED OPERATING CONDITIONS over operating temperature range Logic Supply Voltage Range, VDD ................ 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ ≥ 0.85VDD Low-level input voltage, VIL ................................. ≤ 0.15VDD TRUTH TABLE Shift Register Contents Data Clock Input Input Serial Data Output Strobe I0 I1 I2 ... H H R 0 R1 … R5 R6 R6 L L R0 R1 … R5 R6 R6 R0 R1 R2 … R6 R7 R7 X X … X X X P0 P1 P2 … P6 P7 P7 X L = Low Logic Level X I6 I7 H = High Logic Level — X = Irrelevant Latch Contents I0 I1 ... I6 R0 R1 R2 … R6 R7 P0 P1 P2 … P6 P7 L P0 P1 P2 … P6 P7 X … X H H … H X I2 Output Contents X P = Present State I7 Output Enable X I0 I1 H I2 H … I6 I7 H R = Previous State Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A6B595 8-Bit Serial-Input DMOS Power Driver ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified). Limits Characteristic Symbol Test Conditions Output Breakdown Voltage V(BR)DSX Off-State Output Current Static Drain-Source On-State Resistance IDSX rDS(on) Min. Typ. Max. Units IO = 1 mA 50 — — V VO = 40 V, VDD = 5.5 V — 0.1 5.0 μA VO = 40 V, VDD = 5.5 V, TA = 125°C — 0.15 8.0 μA IO = 100 mA, VDD = 4.5 V — 4.2 5.7 Ω IO = 100 mA, VDD = 4.5 V, TA = 125°C — 6.8 9.5 Ω IO = 350 mA, VDD = 4.5 V (see note) — 5.5 8.0 Ω Nominal Output Current ION VDS(on) = 0.5 V, TA = 85°C — 90 — mA Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 μA IIL VI = 0, VDD = 5.5 V — — -1.0 μA IOH = -20 μA, VDD = 4.5 V 4.4 4.49 — V IOH = -4 mA, VDD = 4.5 V 4.0 4.2 — V IOL = 20 μA, VDD = 4.5 V — 0.005 0.1 V IOL = 4 mA, VDD = 4.5 V — 0.3 0.5 V tPLH IO = 100 mA, CL = 30 pF — 150 — ns tPHL IO = 100 mA, CL = 30 pF — 90 — ns Output Rise Time tr IO = 100 mA, CL = 30 pF — 200 — ns Output Fall Time tf IO = 100 mA, CL = 30 pF — 200 — ns IDD(OFF) VDD = 5.5 V, Outputs OFF — 20 100 μA IDD(ON) VDD = 5.5 V, Outputs ON — 150 300 μA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs OFF — 0.4 5.0 mA SERIAL-DATA Output Voltage VOH VOL Prop. Delay Time Supply Current Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration 100 μs, duty cycle 2%. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A6B595 8-Bit Serial-Input DMOS Power Driver TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 20 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CLK) ............................................. 40 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) ............................................... 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 μs NOTE – Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A6B595 8-Bit Serial-Input DMOS Power Driver TEST CIRCUITS LOGIC SYMBOL EAS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A6B595 8-Bit Serial-Input DMOS Power Driver Package A, 18-Pin DIP 22.86 ±0.51 18 +0.10 0.25 –0.05 +0.76 6.35 –0.25 +0.38 10.92 –0.25 7.62 A 1 2 5.33 MAX +0.51 3.30 –0.38 2.54 +0.25 1.52 –0.38 0.46 ±0.12 SEATING PLANE C All dimensions nominal, not for tooling use (reference JEDEC MS-001 AC) Dimensions in inches Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Package LW, 20-Pin SOICW 12.80±0.20 4° ±4 20 20 +0.07 0.27 –0.06 7.50±0.10 10.30±0.33 A 1 2.25 9.50 +0.44 0.84 –0.43 2 1 2 0.65 0.25 20X SEATING PLANE 0.10 C 0.41 ±0.10 1.27 C SEATING PLANE GAUGE PLANE 1.27 B PCB Layout Reference View 2.65 MAX 0.20 ±0.10 For Reference Only Dimensions in millimeters (Reference JEDEC MS-013 AC) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-20M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A6B595 8-Bit Serial-Input DMOS Power Driver Copyright ©1999-2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9