A80603KESJSR-1

A80603 and A80603-1 LED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple FEATURES AND BENEFITS DESCRIPTION • Automotive AEC-Q100 qualified • Enhanced fault handling for ASIL B system compliance • Wide input voltage range of 4.5 to 40 V for start/stop, cold crank, and load dump requirements • Fully integrated LED current sinks and boost converter with internal power MOSFET • Operate in Boost or SEPIC mode for flexible output • Drives up to 11 series white LED in 4 parallel strings, at up to 120 mA per string (VF = 3.3 V max). • Boost switching frequency synced externally or programmed from 200 kHz to 2.3 MHz • Clock-Out feature for internal switching frequency • Adjustable boost frequency dithering to reduce EMI • Advanced control allows minimum PWM on-time down to 0.3 µs, and avoids MLCC audible noises • LED contrast ratio: 15,000:1 at 200 Hz using PWM dimming alone, 150,000:1 when combining PWM and analog dimming The A80603 and A80603-1 are multi-output LED drivers that integrate a current-mode boost converter with an internal power switch and four current sinks. The boost converter can drive four strings of LEDs at up to 120 mA, or LED sinks can be paralleled together to achieve higher currents up to 480 mA total. The devices operate from single power supply from 4.5 to 40 V; once started, they can continue to operate down to 3.9 V. This allows the parts to withstand stop/start, cold crank, and load dump conditions encountered in automotive systems. By using patented Pre-Emptive Boost control, an LED brightness contrast ratio of 15,000:1 can be achieved using PWM-only dimming at 200 Hz. Higher ratios are possible when using a combination of PWM and analog dimming. Switching frequency can be either above or below the AM band, set by either a resistor or the synchronization pin to between 200 kHz and 2.3 MHz. A programmable dithering feature further reduces EMI. The Clock-Out pin allows other converters to be fed the clock frequency, including programmed dithering—even when the LED output is turned off. Continued on next page... PACKAGE: The A80603 provides protection against application faults and external component open/short. Current sense/gate drive functions allow optional use of an input supply disconnect FET in case of output to ground short fault in boost configuration. The A80603-1 is identical to the A80603 except for soft start timer and FAULT pin behavior (see Fault Table section for details). 24-Pin 4 mm × 4 mm QFN with Wettable Flank Not to scale VIN VOUT *optional L1 RSC Cin D1 Q1 RADJ ROVP SW GATE Vsense Vc CVDD RPU Vin LED1 A80603 LED2 EN LED4 APWM CLKOUT APWM 100 kHz 0-90% AGND Up to 11 WLEDs in series Up to 120 mA/channel LED3 PWM PWM tON ≥ 0.3 µs COUT2 PGND VDD FAULT Enable COUT1 OVP ISET FSET DITH COMP PEB RZ CP RISET RFSET RDITH CDITH RPEB CZ Figure 1: Typical application diagram showing A80603 in Boost mode A80603-DS MCO-0000619 March 4, 2019 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple FEATURES AND BENEFITS (continued) APPLICATIONS • Excellent input voltage transient response even at lowest PWM duty cycle • Gate driver for optional PMOS input disconnect switch • Extensive protection against: □□ Shorted boost switch, inductor or output capacitor □□ Shorted FSET or ISET resistor □□ Open or shorted LED pins and LED strings □□ Open boost Schottky diode □□ Overtemperature • • • • Automotive infotainment backlighting Automotive cluster Automotive center stack Automotive exterior lighting SELECTION GUIDE [1] Part Number Soft Start Timer Package Packing Leadframe Plating A80603KESJSR 8 ms A80603KESJSR-1 [2] 16 ms 24-pin 4 × 4 mm wettable flank QFN with exposed thermal pad and sidewall plating 6000 pieces per reel 100% matte tin [1] Contact Allegro [2] Contact Allegro for additional packing options. factory for availability of A80603KESJSR-1. ABSOLUTE MAXIMUM RATINGS [3] Characteristic Symbol Rating Unit –0.3 to 40 V VOVP –0.3 to 40 V VIN –0.3 to 40 V VSENSE, VGATE Higher of –0.3 and (VIN – 7.4) to VIN +0.4 V Continuous –0.6 to 50 V t < 50 ns (repetitious, 60 V VIN D1 L1 CC L1 & L2 may be either separate or integrated CIN SW GATE Vsense Vc RPU ROVP OVP VDD VDD LED1 A80603 LED3 PWM LED4 APWM COMP CLKOUT AGND Up to 4 WLEDs in series (VOUT < 15 V) Up to 120 mA/ch LED2 EN APWM 100 kHz 0-90% COUT2 Vin CVDD FAULT PWM tON ≥ 0.3 µs COUT1 ISET FSET DITH PEB CP RISET RFSET RDITH CDITH RPEB RZ CZ Figure 2: Typical application showing SEPIC configuration for flexible input/output voltage ratio Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple GATE DITH Oscillator CLKOUT active as long as EN=H Frequency dithering Clock Out Buffer COMP CCOMP VLED ref VDD Rsense Current sense 1 MHz 4 MHz OCP2 System Oscillator TSD VOUT FSET or ISET pin Open/Short Internal VDD (4.25 V) CVDD Rovp VIN Regulator UVLO Block 1.235 V REF OVP sense Vref Enable Open/Short LED Detect + VSENSE Input current sense amp iADJ Chopping Frequency 4 MHz VIN GATE Boost Enable PMOS Driver LED1 LED Driver Block On/Off GATE OFF Current level LED2 LED3 LED4 AGND Enable Int VDD EN 1 MHz 100 kΩ OVP Fault Block AGND RSC External PWM PGND PGND ÷4 LED1 . . LED4 Multi-input Error Amp NMOS FET NMOS Gate Drive Boost Enable Comparator COMP SW VDD fSW Soft Start Ramp (8/16 ms) L1 CDITH RDITH RFSET FSET/SYNC CLKOUT VOUT VSENSE External SYNC Keep-Alive Timer Vref ISET Block APWM ISET RISET VDD PWM RPU LED Enable PEB 100 kΩ start Pre-Emptive Boost Internal FAULT delay RPEB A80603 FAULT AGND Figure 3: Functional Block Diagram Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple FAULT 19 OVP 21 SW 20 SW 22 GATE 23 VSENSE 24 VIN PINOUT DIAGRAM AND TERMINAL LIST 1 18 PGND CLKOUT 2 17 PGND VDD 3 16 LED4 AGND 4 COMP 5 14 LED2 ISET 6 13 LED1 EN 12 9 FSET 15 LED3 PWM 11 8 APWM 10 7 PEB DITH PAD Package ES, 24-Pin QFN Pinouts Terminal List Table Number Name Function 1 FAULT The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 10 kΩ resistor between this pin and desired logic level voltage. 2 CLKOUT Logic output representing the switching frequency of internal boost oscillator. This allows other converters to be synchronized to the same fSW with the same dithering modulation, if applicable. Output is active as long as EN = H. Output of internal LDO (bias regulator). Connect a 1 µF decoupling capacitor between this pin and GND. 3 VDD 4 AGND LED current ground. Also serves as ‘quiet’ ground for analog signals. 5 COMP Output of the error amplifier and compensation node. Connect a series RZ-CZ network from this pin to GND for control loop compensation. 6 ISET Connect RISET resistor between this pin and GND to set the 100% LED current. 7 PEB Connect resistor to GND to adjust delay time (~2 to 9 µs) for Pre-Emptive Boost. Leave pin open for minimum PEB delay of 1 µs. 8 DITH Dithering control: connect a capacitor to GND to set the dithering modulation frequency (typically 1 to 3 kHz). Connect a resistor between DITH and FSET pins to set the dithering range (such as ±5% of fSW). 9 FSET/SYNC 10 APWM Analog dimming. Apply APWM clock (40 kHz to 1 MHz) to this pin and the duty cycle of this clock determines the LED current. Leave open or connect to GND for 100%. 11 PWM Controls the on/off state of LED current sinks to reduce the light intensity by using pulse-width modulation. Typical PWM dimming frequency is in the range of 200 Hz to 2 kHz. EN and PWM pins may be tied together to allow single-wire dimming control. 12 EN Enables the IC when this pin is pulled high. If EN goes low, the IC remains in standby mode for up to 16 ms, then shuts down completely. 13-16 LED1-4 LED current sinks #1 to 4. Connect the cathode of each LED string to pin. Unused LED pin must be terminated to GND through a 6.19 kΩ resistor. 17-18 PGND Power ground for internal NMOS switching device. 19 OVP Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the over voltage protection level. 20-21 SW The drain of the internal NMOS switching device of the boost converter. 22 GATE Frequency/synchronization pin. A resistor RFSET from this pin to GND sets the switching frequency fSW (with dithering super-imposed) between 200 kHz and 2.3 MHz. It can also be used to synchronize fSW to an external frequency between 260 kHz and 2.3 MHz (dithering is disabled in this case). Output gate driver pin for external P-channel FET control. Connect this pin to the negative sense side of the current sense resistor RSC. The threshold voltage is measured as VIN – VSENSE. There is also a fixed ~20 µA current sink to allow for trip threshold adjustment. 23 VSENSE 24 VIN Input power to the IC as well as the positive input used for current sense resistor. – PAD Exposed pad of the package providing enhanced thermal dissipation. Must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple ELECTRICAL CHARACTERISTICS [1]: Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indicates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT VOLTAGE SPECIFICATIONS ● 4.5 − 40 V VUVLO(rise) VIN rising ● − – 4.35 V VIN UVLO Stop Threshold VUVLO(fall) VIN falling ● − – 3.95 V UVLO Hysteresis [2] VUVLO_HYS 300 450 600 mV Operating Input Voltage Range [3] VIN UVLO Start Threshold VIN INPUT CURRENTS VIN Pin Operating Current IOP EN and PWM = H, fSW = 2 MHz ● − 13 18 mA VIN Pin Quiescent Current IQ EN = H and PWM = L, fCLKOUT = 2 MHz ● − 10 − mA VIN = 16 V, VEN = 0 V ● − 2 10 µA VIN Pin Sleep Current IQSLEEP INPUT LOGIC LEVELS (EN, PWM, APWM) Input Logic Level-Low VIL ● − − 0.4 V Input Logic Level-High VIH ● 1.5 − − V 60 100 140 kΩ Input Pull-Down Resistor REN, RPWM, RAPWM Input = 5 V OUTPUT LOGIC LEVELS (CLKOUT) Output Logic Level-Low VOL 5 V < VIN < 40 V ● − − 0.3 V Output Logic Level-High VOH 5 V < VIN < 40 V ● 1.8 − − V ● 33 50 67 % − 200 − ns CLKOUT Duty Cycle DCLKOUT fSW = 2 MHz, no external sync CLKOUT Negative Pulse Width [2] tCLKNPW External sync = 260 kHz to 2.3 MHz APWM PIN APWM Frequency Range [2] fAPWM Clock signal applied to pin ● 40 − 1000 kHz Range [2] DAPWM Clock signal applied to pin ● 0 − 90 % VDD VIN > 4.5 V, iLOAD < 1 mA APWM Duty Cycle VDD REGULATOR Regulator Output Voltage 4.05 4.25 4.45 V VDD UVLO Start Threshold VDDUVLOrise VDD rising, no external load − 3.2 − V VDD UVLO Stop Threshold VDDUVLOfall VDD falling, no external load − 2.65 − V gm VCOMP = 1.5 V − 1000 − μA/V Source Current IEA(SRC) VCOMP = 1.5 V − –500 − μA Sink Current IEA(SINK) VCOMP = 1.5 V − +500 − μA COMP Pin Pull Down Resistance RCOMP FAULT = 0, VCOMP = 1.5 V − 1.4 − kΩ ERROR AMPLIFIER Amplifier Gain [2] Continued on the next page… Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple ELECTRICAL CHARACTERISTICS [1] (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indicates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C Characteristics Symbol Test Conditions Min. Typ. Max. Unit DITHERING CONTROL DITH Pin Source Current iDITH(src) Output current when VDITH < 0.8 V − 20 − μA DITH Pin Sink Current iDITH(sink) Output current when VDITH > 1.2 V − −20 − μA VOVP(th) OVP pin connected to VOUT OVERVOLTAGE PROTECTION OVP Pin Voltage Threshold OVP Pin Sense Current Threshold iOVP(th) OVP Sense Current Temperature Coefficient [2] ∆iOVP Current into OVP pin IOVPLKG VOUT = 16 V, EN = L OVP Pin Leakage Current OVP Variation at Output Undervoltage Detection Threshold Secondary Overvoltage Protection ΔOVP VUVP(th) VOVP2 ● Current into OVP pin at 125ºC Measured over temperature ● ● 2.2 2.5 2.8 V 140 146.5 153 µA 140 150 160 µA − −36 − nA/ºC − 0.1 1 µA Measured at VOUT when ROVP = 249 kΩ − − 5 % Measured at VOUT when ROVP = 249 kΩ [2] − 3.3 4.2 V Measured at VOUT when ROVP = 0 Ω − 0.2 0.25 V Measured at SW pin; part latches when OVP2 is detected ● 51 55 59 V ISW = 0.75 A, VIN = 16 V ● − 250 500 mΩ BOOST SWITCH Switch On Resistance Switch Pin Leakage Current RSW ISWLKG25 VSW = 13.5 V, VPWM = VIL, TJ = 25°C − 0.1 1 µA ISWLKG85 [2] VSW = 13.5 V, VPWM = VIL, TJ = 85°C − − 10 µA ● 3.0 3.75 4.5 A Switch Pin Current Limit ISW(LIM) IC truncates present switching cycle when primary limit is reached Secondary Switch Current Limit [2] ISW(LIM2) IC latches off when secondary limit is reached − 5.1 − A Minimum Switch On-Time tSW(ON) ● 45 65 85 ns Minimum Switch Off-Time tSW(OFF) ● − 50 66 ns ● 1.95 2.15 2.35 MHz OSCILLATOR FREQUENCY Oscillator Frequency FSET Pin Voltage fSW RFSET = 10 kΩ RFSET = 110 kΩ − 200 − kHz VFSET RFSET = 10 kΩ − 1.00 − V VSYNCL FSET/SYNC pin logic Low ● − − 0.4 V VSYNCH FSET/SYNC pin logic High SYNCHRONIZATION Sync Input Logic Level ● 1.5 − − V fSWSYNC ● 260 − 2300 KHz Synchronization Input Min Off-Time tPWSYNCOFF ● 150 − − ns Synchronization Input Min On-Time tPWSYNCON ● 150 − − ns Synchronized PWM Frequency Continued on the next page… Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple ELECTRICAL CHARACTERISTICS [1] (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indicates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C Characteristics Symbol Test Conditions Min. Typ. Max. Unit LED CURRENT SINKS LEDx Accuracy [4] ErrLED iISET = 120 µA (RISET = 8.33 kΩ), RFSET = 10 kΩ, VAPWM = 0 V ● − 0.7 3 % LEDx Matching ΔLEDx iISET = 120 µA, RFSET = 10 kΩ, VAPWM = 0 V ● − 0.8 2 % LEDx Regulation Voltage VLED Measured individually with all other LED pins tied to ≥1 V, iISET = 120 µA, VAPWM = 0 V ● 600 700 800 mV iISET = 120 µA, VAPWM = 0 V ● IISET to ILEDx Current Gain AISET ISET Pin Voltage VISET Allowable ISET Current iISET 812 832 852 A/A 0.97 1 1.03 V ● 20 − 144 µA ● 4.5 5.2 6 V LED String Partial-Short-Detect Voltage VLEDSC Sensed from each LED pin to GND while its current sink is in regulation; all other LED pins tied to 1 V LED String Partial-Short-Detect Duration tLEDSC Time required to confirm LED string partialshort and pull FAULT = L − − 6.6 µs LED Pin Shorted-to-GND Check Duration tLEDSTG Wait time before proceeding with Soft-Start (if no LED pin is shorted to GND) − 1.5 − ms Soft-Start Ramp Up Time Enable Pin Shut Down Delay Minimum PWM Dimming On-Time tSSRU A80603 6.5 8 9.5 ms A80603-1 13 16 19 ms EN goes from High to Low; exceeding tEN(OFF) results in IC shutdown ● 10 16 22 ms tPWMH First and subsequent PWM pulses ● − 0.3 0.4 µs IGSINK VGS = VIN, no input OCP fault − −113 − µA VGS = VIN – 6 V, input OCP fault tripped − 6 − mA VIN – VSENSE = 200 mV; monitored at FAULT pin − − 3 µs Measured between GATE and VIN when gate is fully on − −6.7 − V ● 16 20 24 µA Measured between VIN and VSENSE, RADJ = 0 Ω ● 88 100 110 mV tPEB iPEB = 60 µA 2.4 3.2 4.0 µs VFAULT IFAULT = 1 mA − − 0.5 V iFAULT-LKG VFAULT = 5 V − − 1 µA 155 170 − °C − 20 − °C tEN(OFF) GATE PIN Gate Pin Sink Current Gate Pin Source Current Gate Shutdown Delay When OverCurrent Fault Is Tripped [2] Gate Voltage IGSOURCE tFAULTT VGS VSENSE PIN VSENSE Pin Sink Current VSENSE Trip Point iADJ VSENSETRIP PEB PIN PEB Delay Time FAULT PIN FAULT Pull Down Voltage FAULT Pin Leakage Current THERMAL PROTECTION (TSD) Thermal Shutdown Threshold [2] Thermal Shutdown Hysteresis [2] TSD Temperature rising TSDHYS For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization; not production tested. [3] Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 4 V. IN IN [4] LED current is trimmed to cancel variations in both Gain and ISET voltage. [1] Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple FUNCTIONAL DESCRIPTION The A80603 is a multistring LED regulator with an integrated boost switch and four precision current sinks. It incorporates a patented Pre-Emptive Boost (PEB) control algorithm to achieve PWM dimming ratio over 15,000:1 at 200 Hz. PEB control also minimizes output ripple to avoid audible noise from output ceramic capacitors. The switching frequency can be either synchronized to an external clock or generated internally. Spread-spectrum technique (with user-programmable dithering range and modulation frequency) is provided to reduce EMI. A clock-out signal (CLKOUT) allows other converters to be synchronized to the switching frequency of A80603. Only if no faults were detected, then the IC can proceed to start switching. As long as EN = H, the PWM pin can be toggled to control the brightness of LED channels by using PWM dimming. Alternatively, EN and PWM can be tied together to allow single-wire control for both power on/off and PWM dimming. If EN is pulled low for longer than 16 ms, the IC shuts off. Enabling the IC The A80603 wakes up when EN pin is pulled above logic high level, provided that VIN pin voltage is over the VIN_UVLO threshold. The boost stage and LED channels are enabled separately by PWM = H signal after the IC powers up. The IC performs a series of safety checks at power up, to determine if there are possible fault conditions that might prevent the system from functioning correctly. Power-up checks include: • VOUT shorted to GND • LED pin shorted to GND • FSET pin open/shorted Figure 4: Startup showing EN, VDD, CLKOUT, and ISET (PWM = L). Note that CLKOUT is available as soon as VDD ramps up, even though Boost stage and LED drivers are not yet enabled. • ISET pin open/shorted to GND, etc. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Powering Up: LED Detection Phase The VIN pin has an undervoltage lockout (UVLO) function that prevents the A80603 from powering up until the UVLO threshold is reached. Once the VIN pin goes above UVLO and a high signal is present on the EN pin, the IC proceeds to power up. At this point, the A80603 is going to enable the disconnect switch and will try to check if any LED pins are shorted to GND and/or are not used. The LED detection phase starts when PWM = H and the GATE voltage of the input disconnect PMOS switch is pulled down to 3.3 V below VIN. VOUT VOUT Using all LED Channels Using LED Channels 1-3 LED1 LED1 LED2 LED2 LED3 LED3 GND LED4 GND LED4 6.19 kΩ Figure 6: How to signal an unused LED channel during startup LED detection phase Table 1: LED Detection phase voltage threshold levels LED Pin Voltage Measured Interpretation Outcome < 120 mV LED pin shorted to GND fault Cannot proceed with soft-start unless fault is removed ~ 230 mV LED channel not in use LED channel is removed from operation > 340 mV LED channel in use Proceed with soft-start Figure 5: Startup showing EN+PWM, GATE, LED1, and ISET. Switching frequency = 2.15 MHz. Note that LED Detection Phase starts as soon as GATE pin is pulled down to 3.3 V below VIN (provided that PWM = H). Once the voltage threshold on VLED pins exceeds ~120 mV, a delay of approximately 1.5 ms is used to determine the status of the pins. Unused LED pin should be terminated with a 6.19 kΩ resistor to GND. At the end of LED detection phase, any channel with pull down resistor is then disabled and will not contribute to the boost regulation loop. Figure 7: A80603 normal startup showing all channels passed LED Detection phase. Total LED current = 100 mA × 4 (only LED1 and LED2 pin voltages are shown). Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Figure 8: A80603-1 normal startup showing all channels passed LED Detection phase. Note longer soft start timer. Figure 9: A80603 normal startup showing LED1 channel is disabled with a 6.19 kΩ resistor to GND. Total LED current = 100 mA × 3. If an LED pin is shorted to ground, the A80603 will not proceed with soft start until the short is removed from the LED pin. This prevents the A80603 from ramping up the output voltage and putting an uncontrolled amount of current through the LEDs. Figure 10: A80603; LED1 is shorted-to-GND initially, then released. After the fault is removed, the IC auto-recovers and proceeds with soft-start. FAULT is released at the end of LED detection phase. Figure 11: A80603-1, LED1 is shorted-to-GND initially, then released. After the fault is removed, the IC auto-recovers and proceeds with soft-start. FAULT is released at the beginning of LED detection phase. The FAULT pin is pulled low in case of LED pin shorted-to-GND fault (A80603 only), but the IC continues to retry. Once the fault is removed, the soft-start process will continue. The same applies in case of FSET or ISET pin is shorted to GND. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Power Up: Boost Output Undervoltage During startup, after the input disconnect switch has been enabled, the output voltage is checked through the OVP (overvoltage protection) pin. If the sensed voltage does not rise above VUVP(th), the output is assumed to be at fault and the IC will not proceed with soft start. Output UVP level is linked to the OVP level programmed according to the equation: VUVP = VOVP / 12 Undervoltage protection may be caused by one of the following faults: • Output capacitor shorted to GND • Boost inductor or diode open • OVP sense resistor open After an UVP (undervoltage protection) fault, the A80603 is immediately shutdown and latched off. To enable the IC again, the latched fault must be cleared. This can be achieved by powering-cycling the IC, which means either: • VIN falls below falling UVLO threshold, or • EN = L for >16 ms. This is illustrated by the following startup timing diagram (not to scale): EN PWM VIN 3.3 V GATE 6.7 V 0 1V LEDx 0 LED detection phase 93% OVP 1.5 ms OVP VOUT VIN 0 tSSRU i LED 0 A B C D Soft-Start E Regulation Figure 12: Complete startup process of A80603 Alternatively, latched fault can be cleared by keeping EN = H but pulling PWM = L for >16 ms. This method has the advantage that it does not interrupt the CLKOUT signal. Explanation of Events: Soft Start Function B: When GATE is pulled down to 3.3 V below VIN, ISET becomes enabled. IC is now waiting for PWM = H to startup. During startup, the A80603 ramps up its boost output voltage following a fixed slope, as determined by OVP set point and SoftStart Timer. This technique limits the input inrush current, and ensures consistent startup time regardless of the PWM dimming duty cycle. The soft-start process is completed when any one of the following conditions is met: • All enabled LED channels have reached their regulation current, • Output voltage has reached 93% of its OVP threshold, or • Soft-start ramp time (tSSRU) has expired. A: EN = H wakes up the IC. VDD ramps up and CLKOUT becomes available. IC starts to pull down GATE slowly. C: Once PWM = H, the IC checks each LEDx pins to determine if it is in use, disabled, or shorted to GND. D: Soft-Start begins at the completion of LED pin short-detect phase of 1.5 ms. VOUT ramps up following a fixed slope set by OVP and soft-start timer of ~8 ms (16 ms for the A80603-1). E: Soft-start terminates when all LED currents reached regulation, VOUT reached 93% OVP, or soft-start timer expired. To summarize, the complete startup process of A80603 consists of: • • • • Power-up error checking Enabling input disconnect switch LED pin open/short detection Soft-start ramp Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Frequency Selection IC Off The switching frequency of the boost regulator is programmed by a resistor connected to FSET pin. The switching frequency can be selected anywhere from 200 kHz to 2.3 MHz. The chart below shows the typical switching frequency verses FSET resistor value. EN=H & VIN>UVLO EN=L Power up (VDD, BG ready; GATE pulled L; Fault checking) FAULT State (FAULT = L) Any Fault detected? Yes No EN=L IC Ready (CLKOUT active, FAULT = L ) EN=H & PWM=L EN=H & PWM=H Pin shorted to GND fault → FAULT = L LED Pin Check (In Use, Disabled, or Shorted to GND) Time-out without faults → FAULT = H Soft Start (boost SW active; LED sinks = on when PWM = H) Soft start finished Any Fault detected? PWM Dimming Yes Alternatively, the following empirical formula can be used: No Equation 1: LED=on EN && PWM = L LED=off Start 16 ms timer fSW = 21.5 / (RFSET + 0.2) where fSW is in MHz and RFSET is in kΩ. Clear 16 ms timer EN && PWM = H Figure 14: Switching Frequency as a function of FSET Resistance Timer expired Figure 13: A80603 Startup Flow Chart If a fault occurs during operation that will increase the switching frequency, the internal oscillator frequency is clamped to a maximum of 3.5 MHz. If the FSET pin is shorted to GND, the part will shut down. For more details, refer to the Fault Mode Table section. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Synchronization EN The A80603 can also be synchronized using an external clock. At power up, if the FSET pin is held low, the IC will not start. Only when the FSET pin is tristated to allow for the pin to rise to about 1 V, or when a sync clock is detected, the A80603 will then try to power up. The basic requirement of the external sync signal is 150 ns minimum on-time and 150 ns minimum off time. The diagram below shows the timing restrictions for a synchronization clock at 2.2 MHz. t PWSYNCON 154 ns PWM 500 ns Ext_Sync / FSET 1 V CLKOUT Internal oscillator External Sync Figure 16: Avoid switching over between Internal Oscillator and External Sync in highlighted region Loss of External Sync Signal 150 ns Suppose the A80603 started up with a valid external SYNC signal, but the SYNC signal is lost during normal operation. In that case, one of the following happens: 150 ns t PWSYNCOFF t = 454 ns Figure 15: Pulse width requirements for an External Sync clock at 2.2 MHz Based on the above, any clock with a duty cycle between 33% and 66% at 2.2 MHz can be used. The table below summarizes the allowable duty cycle range at various synchronization frequencies. Table 2: Acceptable Duty Cycle range for External Sync clock at various frequencies Sync. Pulse Frequency Duty Cycle Range 2.2 MHz 33% to 66% 2 MHz 30% to 70% 1 MHz 15% to 85% 600 kHz 9% to 91% 300 kHz 4.5% to 95.5% If it is necessary to switch over between internal oscillator and external sync during operation, ensure the transition takes place at least 500 ns after the previous PWM = H rising edge. Alternatively, execute the switchover during PWM = L only. This restriction does not apply if PWM dimming is not being used. • If the external SYNC signal is high impedance (open), the IC continues normal operation after approximately 5 μs, at the switching frequency set by RFSET. No FAULT flag is generated. • If the external SYNC signal is stuck low (shorted to ground), the IC will detect an FSET-shorted-to-GND fault. FAULT pin is pulled low after approximately 10 μs, and switching is disabled. Once the FSET pin is released or SYNC signal is detected again, the IC will proceed to soft-start. To prevent generating a fault when the external SYNC signal is stuck at low, the circuit shown below can be used. When the external SYNC signal goes low, the IC will continue to operate normally at the switching frequency set by the RFSET. No FAULT flag is generated. External Sychronization 220 pF Signal Schottky Barrier Diode FSET/SYNC RFSET 10 kΩ Figure 17: Countermeasure for External Sync Stuck-at-Low Fault It is important to use a small capacitance for the AC-coupling capacitor (220 pF in the above example). If the capacitance is too large, the IC may incorrectly declare a FSET-shorted-to-GND fault and restart. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Switching Frequency Dithering To minimize the peak EMI spikes at switching frequency harmonics, the A80603 offers the option of frequency dithering, or spread-spectrum clocking. This feature simplifies the input filters needed to meet the automotive CISPR 25 conducted and radiated emission limits. There are no hard limits on dithering range and modulation frequency. As a general guideline, pick a dithering range between ±5% and 10%, with the modulation frequency between 1 kHz and 3 kHz. In practice, using a larger dithering range and/or higher modulation frequency do not generate any noticeable benefits. For maximum flexibility, the A80603 allows both dithering range and modulation frequency to be independently programmable using two external components. If dithering function is not desired, it can be disabled by disconnecting the RDITH between DITH and FSET pins. Connect DITH pin to VDD if CDITH is not populated. Dithering is always disabled when fSW is controlled by external sync. RDITH and CDITH have no effects in this case even if they were populated. The Dithering Modulation Frequency is given by the approximate equation: Clock Out Function Equation 2: fDM (kHz) = 25 / CDITH (nF) where CDITH is the value of capacitor connected from DITH pin to GND. The dithering Range is given by the approximate equation: Equation 3: Range (±%) = 20 × RFSET / RDITH where RFSET is the resistor from FSET pin to GND, RDITH is the resistor between DITH and FSET pins. As an example, by using RFSET = 10 kΩ, RDITH = 40.1 kΩ, and CDITH = 22 nF, the resulted switching frequency is fSW = 2.15 MHz ±5% modulated at 1.1 kHz. This is illustrated by the following diagram. FSET RFSET 10 kΩ iFSET = 100 µA ±5 µA RDITH 40.1 kΩ DITH The CLKOUT signal is available as soon as the IC is enabled (EN = H), even when the boost stage is not active (PWM = L). Its frequency is the same as that of the internal oscillator. Its duty cycle, however, depends on how the switching frequency is generated: • If fSW is programmed by FSET resistor, the CLKOUT duty cycles is approximately 50%. • If fSW is controlled by external sync, the output signal has a fixed 150 ns negative pulse width (CLKOUT = L), regardless of the external sync frequency. This is illustrated by the following waveforms: VDITH 1.2 V iDITH = ±20 µA The A80603 allows other ICs to be synchronized to its internal switching frequency through the CLKOUT pin. VFSET 1.0 V 0.8 V CDITH 22 nF Dithering Range = ±5% iDITH 20 µA 0 Modulation frequency = 1.1 kHz –20 µA Per iod = 0.8 × C / i (0.88 ms when C = 22 nF) fSW (MHz) 2.25 2.15 2.05 Time (ms) 0 0.88 Figure 18: How to Program Switching Frequency Dithering Range and Modulation Frequency Figure 19: Without external sync, the CLKOUT signal has a fixed duty cycle of 50%. Delay from CLKOUT falling edge to SW falling edge is approximately 50 ns. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple PWM Dimming When both EN and PWM pins are pulled high, the A80603 turns on all enabled LED current sinks. When either EN or PWM is pulled low, all LED current sinks are turned off. The compensation (COMP) pin is floated, and critical internal circuits are kept active. Figure 20: With external sync, the CLKOUT signal has a fixed negative pulse width of 200 ns. Delay from SYNC rising edge to CLKOUT falling edge is approximately 60 ns. LED Current Setting The maximum LED current can be up to 120 mA per channel, and is set through the ISET pin. Connect a resistor RISET between this pin and GND. The relation between ILED and RISET is given below: Equation 4: By using the patented Pre-Emptive Boost (PEB) control algorithm, the A80603 is able to achieve minimum PWM dimming on-time down to 300 ns. This translates to PWM dimming ratio up to 15,000:1 at the PWM dimming frequency of 200 Hz. Technical details on PEB will be explained in the next section. ILED = ISET × AISET ISET = VISET / RISET Therefore RISET = (VISET × AISET ) / ILED Figure 21: PWM dimming operation at 20% 1 kHz. CH1 = PWM (5 V/ div), CH2 = SW (20 V/div), CH3 = VOUT, CH4 = iLED (200 mA/div). = 832 / ILED where ILED current is in mA and RISET is in kΩ. This sets the maximum current through the LEDs, referred to as the ‘100% current’. The average LED current can be reduced from the 100% current level by using either PWM dimming or analog dimming. Table 3: ISET resistor values vs. LED current. Resistances are rounded to the nearest E-96 (1%) resistor value. Standard Closest RISET Resistor Value LED current per channel 6.98 kΩ 120 mA 8.25 kΩ 100 mA 10.5 kΩ 80 mA 13.7 kΩ 60 mA 21.0 kΩ 40 mA Figure 22: Zoom in view for PWM on-time = 10 µs. Notice that the LED current is shifted with respect to PWM signal. Ripple at VOUT is ~0.2 V when using 2 × 4.7 µF MLCC as output capacitors. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple CH1 (Yellow) = PWM (5 V/div); CH2 (Red) = Inductor current (500 mA/div); CH3 (Blue) = VOUT (1 V/div); CH4 (Green) = LED current (200 mA/div); time scale = 2 µs/div. Figure 23: Zoom-in view showing A80603 is able to regulate LED current at PWM on-time down to 300 ns. The typical PWM dimming frequencies fall between 200 Hz and 1 kHz. There is no hard limit on the highest PWM dimming frequency that can be used. However at higher PWM frequency, the maximum PWM dimming ratio will be reduced. This is shown in the following table: Table 4: Maximum PWM Dimming Ratio that can be achieved when operating at different PWM Dimming Frequency PWM Frequency PWM Period Maximum PWM Dimming Ratio 200 Hz 5 ms 15,000:1 1 kHz 1 ms 3,000:1 3.3 kHz 300 µs 1,000:1 20 kHz 50 µs 150:1 Figure 24: Traditional PWM Dimming operation where boost switch and LED current are enabled at the same time. Note that VOUT shows overall ripple of ~0.5 V When PWM signal goes high, a conventional LED driver turns on its boost switching at the time with LED current sinks. The problem is that the inductor current takes several switching cycles to ramp up to its steady-state value before it can deliver full power to the output load. During the first few cycles, energy to the LED load is mainly supplied by the output capacitor, which results in noticeable dip in output voltage. Pre-Emptive Boost The basic principle of pre-emptive boost (PEB) can be best explained by the following two waveforms. The first one shows how a conventional LED driver operates during PWM dimming operation. The second one shows that of the A80603. Common test conditions for both cases: PWM = 1% at 1 kHz (on-time=10 µs), fSW = 2.15 MHz, L = 10 µH, VIN = 12 V, LED load = 8 series (VOUT = ~25 V) at 100 mA × 4. COUT = 2 × 4.7 µF 50 V 1210 MLCC. COMP: RZ = 280 Ω, CZ = 68 nF. Common scope settings: Figure 25: A80603 PWM dimming operation with PEB delay set to 3 µs. Note that VOUT ripple is reduced to ~0.2 V. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple In the A80603, the boost switch is also enabled when PWM goes high. However, the LED current is not turned on until after a short delay of tPEB. This allows the inductor current to build up before it starts to deliver the full power to LED load. During the pre-boost period, VOUT actually bumps up very slightly, while the following dip is essentially eliminated. When PWM goes low, both boost switching and LED remains active for the same delay of tPEB. Therefore the PWM on-time is preserved in LED current. Analog Dimming with APWM Pin APWM RISET PEB delay can be programmed using an external resistor, RPEB, from PEB pin to GND. Their relationship is shown in the following chart: LED Driver Figure 27: Simplified block diagram of APWM function 5 The APWM pin is used in conjunction with the ISET pin to achieve analog dimming. This is a digital signal pin that internally adjusts the ISET current. The typical input signal frequency is between 40 kHz and 1 MHz. The duty cycle of this signal is inversely proportional to the percentage of current delivered to the LED. The relationship is shown below: 4 Normalized LED Current vs. APWM Duty Cycle 9 8 7 tPEB (µs) PWM PEB Delay (µs) vs. PEB Resistor value (kΩ) 10 APWM ISET Current Adjust Block ISET Current Mirror ISET 6 3 100% 2 80% 0 6 8 10 12 14 16 RPEB (kΩ) 18 20 22 24 Figure 26: How PEB delay time varies with value of PEB pin resistor to GND. Ideally, tPEB is equal to the inductor current ramp up time. But the latter is affected by many external parameters, such as switching frequency, inductance, VIN and VOUT ratio, etc. Therefore, some experimentation is required to optimize the PEB delay time. In general for switching frequency at 2 MHz, tPEB = 2.5 to 4 µs is a good starting point. The advantage of PEB is that even a non-optimized delay time can significantly reduce the output ripple voltage compared to a conventional LED driver. Measured LED Current 1 60% Theore�cal 40% 20% 0% 0% 20% 40% 60% APWM Duty Cycle 80% 100% Figure 28: Showing LED current is inversely proportional to the APWM duty cycle. Test conditions: VIN =12 V, VOUT = 25 V (8 × WLED), total LED current = 100 mA × 4, APWM frequency = 100 kHz As an example, a system that delivers a full LED current of 100 mA per channel would deliver 75 mA when an APWM signal with a duty-cycle of 25% is applied (because analog dimming level is 100% – 25% = 75%). This is demonstrated by the following waveforms. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple As an example, assume that: • LED from lowest bin has an efficacy of 80 lm/W • LED highest bin has an efficacy of 120 lm/W Suppose the maximum LED current was set at 100 mA based LEDs from lowest bin. When using LEDs from highest bin, the current should then be reduces to 67% (80/120). This can be achieved by sending APWM clock with 33% duty cycle. When analog dimming is not used, APWM pin should be either tied to GND or left floating (there is an internal pull-down resistor to GND). Extending LED Dimming Ratio Figure 29: PWM = H. Total LED current drops from 400 mA (4 × 100 mA/ch) to 300 mA when APWM of 25% duty cycle is applied. Note that LED current takes ~0.5 ms to settle after change in APWM. The dynamic range of LED brightness can be further extended, by using a combination of PWM duty cycle, APWM duty cycle, and analog dimming method. For example, the following approach can be used to achieve a 100,000:1 dimming ratio at 200 Hz: • Vary PWM duty cycle from 100% down to 0.01% to give 10,000:1 dimming. This requires PWM dimming on-time be reduced down to 0.5 µs. • With PWM dimming on-time fixed at 0.5µs, vary APWM duty from 0% to 90% to reduce peak LED current from 100% down to 10%. This gives a net effect of 100,000:1 dimming. Figure 30: PWM = 25% at 1 kHz. Peak LED current drops from 400 mA (4 × 100 mA/ch) to 300 mA when APWM of 25% duty cycle is applied One popular application of analog dimming is for LED brightness calibration, commonly known as ‘LED Binning’. LEDs from the same manufacturer and series are often grouped into different ‘bins’ according to their light efficacy (lumens per watt). It is therefore necessary to calibrate the ‘100% current’ for each LED bin, in order to achieve uniform luminosity. To use APWM pin as a trim function, the user should first set the 100% current based on efficacy of LED from the lowest bin. When using LED with higher efficacy, the required current is then trimmed down to the appropriate level using APWM duty cycle. Normalized LED Current (%) 100 Average LED Current vs. PWM Dimming Duty Cycle 10 1 0.1 PWM Dimming 0.01 APWM + PWM Ideal 0.001 0.001 0.01 0.1 1 10 PWM Dimming Duty Cycle (%) 100 Figure 31: How to achieve 100,000:1 dimming ratio by using both PWM and APWM. Test conditions: VIN = 12 V, VOUT = 25 V (8 × WLED), total LED current = 400 mA, PWM frequency = 200 Hz, APWM frequency = 100 kHz. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Note that the A80603 is capable of providing analog dimming range greater than 10:1. By applying APWM with 96% duty cycle, for example, an analog dimming range of 25:1 can be achieved. However, this requires the external APWM signal source to have very fine pulse-width resolution. At 200 kHz APWM frequency, a resolution of 50 ns is required to adjust its duty cycle by 1%. Analog Dimming with External Voltage Besides using APWM signal, the LED current can also be reduced by using an external voltage source applied through a resistor to the ISET pin. The dynamic range of this type of dimming is dependent on the ISET pin current. The recommended iSET range is from 20 µA to 144 µA for the A80603. Note that the IC will continue to work at iSET below 20 µA, but the relative error in LED current becomes larger at lower dimming level. Below is a typical application circuit using a DAC (digital-analog converter) to control the LED current. The ISET current (which directly controls the LED current) is normally set as VISET/RISET. The DAC voltage can be higher or lower than VISET, thus adjusting the LED current to a lower or higher value. A80603 R2 VDAC When VDAC is lower than 1.00 V, the LED current is increased. Some common applications for the above scheme include: • LED binning • Thermal fold-back using external NTC (negative temperature coefficient) thermistor In the following application example, the thermistor used is NTCS0805E3684JXT (680 kΩ @ 25°C). R1 = 336 kΩ, R2 = 20 kΩ, and R3 = 8.45 kΩ. The LED current per channel is reduced from 97 mA at 25°C to 34 mA at 125°C. VDD (4.25 V) NTC R2 R1 A80603 ISET (1.0 V) R3 GND Figure 33: Thermal foldback of LED current using NTC thermistor ISET RISET GND Figure 32: Adjusting LED current with an external voltage source Equation 5: iISET = VISET VDAC − VISET  −  RISET  R2  where VISET is the ISET pin voltage (typically 1.0 V), and VDAC is the DAC output voltage. When VDAC is higher than 1.00 V, the LED current is reduced. Figure 34: LED current varies with temperature when using thermistor NTCS0805E3684JXT for thermal foldback Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 20 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple VDD The VDD pin provides regulated bias supply for internal circuits. Connect a CVDD capacitor with a value of 1 μF or greater to this pin. The internal LDO can deliver up to 2 mA of current with a typical VDD voltage of about 4.25 V. This allows it to serve as the pull up voltage for FAULT pin. There is an alternative way to reset the internal fault status registers. By keeping EN = H and PWM = L for longer than 16 ms, the A80603 clears all internal fault registers but does not go into sleep mode. The next time PWM pin goes high, the IC will still go through soft start process. The difference is that VDD voltage and CLKOUT signal are always available as long as EN = H. Shutdown If EN pin is pulled low for longer than tEN(OFF) (~16 ms), the A80603 enters shutdown (sleep mode). The next time EN pin goes high, all internal fault registers are cleared. The IC needs to go through a complete soft start process after PWM goes high. Figure 36: As long as EN = H, the IC does not shut down VDD and CLKOUT. But internal latched faults are cleared by PWM = L for ~16 ms. Figure 35: After EN = L for ~16 ms, the IC completely shuts down so VDD (Blue) decays. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 21 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple FAULT DETECTION AND PROTECTION LED String Partial-Short Detect All LED current sink pins (LED1 to LED4) are designed to withstand the maximum output voltage, as specified in the Absolute Maximum Ratings table. This prevents the IC from being damaged if VOUT is directly applied to an LED pin due to an output connector short. For the A80603 only, the FAULT pin is pulled low in case any LED string is directly or partially shorted. However, the rest of the LED strings continue to operate. The FAULT pin is latched at low until it is reset by either EN = L or PWM = L for >16 ms. In case of direct-short or partial-shorted fault in any LED string during operation, the LED pin with voltage exceeding VLEDSC will be removed from regulation. This prevents the IC from dissipating too much power due to large voltage drop across the LED current sink. Figure 39: A80603-1 startup sequence when LED string#2 has a partial-short fault (6 × WLED instead of 8). As soon as LED2 pin rises above VLEDSC (~5 V), the channel is disabled but FAULT remains High. Figure 37: A80603 Normal startup sequence showing voltage at LED1 and LED2 pins. VIN = 6 V, output = 8 × WLED in series, current = 4 × 100 mA At least one LED pin must be at regulation voltage (below ~1.2 V) for the LED string partial-short detection to activate. In case all of the LED pins are above regulation voltage (this could happen when the input voltage rises too high for the LED strings), they will continue to operate normally. Overvoltage Protection The A80603 offers a programmable output overvoltage protection (OVP), plus a fixed secondary overvoltage protection (OVP2). The OVP pin has a threshold level of 2.5 V typical. Overvoltage protection is tripped when current into this pin exceeds ~150 µA. A resistor can be used to set the OVP threshold up to 40 V approximately. This is sufficient for driving 11 white LEDs in series. The formula for calculating the OVP resistor is shown below: Equation 6: ROVP = (VOVP – VOVP(th)) / iOVP(th) where VOVP is the desired OVP threshold, VOVP(th) = 2.5 V typical, iOVP(th) = 150 µA typical. Figure 38: A80603 startup sequence when LED string#2 has a partialshort fault (6 × WLED instead of 8). As soon as LED2 pin rises above VLEDSC (~5 V), the channel is disabled and FAULT = Low. To determine the desired OVP threshold, take the maximum LED string voltage at cold and add ~10% margin on top of it. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 22 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple The OVP event is not a latched fault and, by itself, does not pull the FAULT pin to low. If the OVP condition occurs during a load dump, for example, the IC will stop switching but not shut down. There are several possibilities of why an OVP condition is encountered during operation. The two most common being an open LED string and a disconnected output connector. The waveform below shows a typical OVP condition. When one LED string becomes open, current through its LED driver drops to zero. The A80603 responses by boosting the output voltage higher. When output reaches OVP threshold, the LED string without current is removed from regulation. The rest of LED strings continue to draw current and drain down VOUT. Once VOUT falls below ~97% OVP, boost will resume switching to power the remaining LED strings. Figure 41: An open-diode fault is introduced during normal operation. SW voltage jumps to ~70 V, causing the MOSFET to self-conduct and dissipate energy in the inductor. It should be noted that the SW MOSFET in A80603 is designed to avalanche and dissipate the excess energy safely in case of open-diode fault. Therefore the IC is not damaged even though SW node rises above AbsMax rating momentarily. Boost Switch Overcurrent Protection The boost switch is protected with cycle-by-cycle current limiting set at typical 3.75 A, minimum 3.0 A. The waveform below shows normal switching at VIN = 6 V, VOUT = 25 V, and total LED current 400 mA. Figure 40: An open-LED string faults causes VOUT to ramp up and trip OVP. The A80603 then disables the open LED string and continues with remaining strings. The A80603 also has a fixed secondary overvoltage protection to protect its internal switch. If the boost Schottky diode suddenly becomes open during normal operation, the energy stored in the inductor will force SW node voltage to increase rapidly. Once voltage on the SW pin exceeds OVP2, switching and all LED drivers are disabled. The IC remains latched off until it is reset. Figure 42: Normal switching waveform at VIN = 6 V showing the SW node voltage (Red) and inductor current (Green). Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 23 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple When the input voltage is reduced further, input current increases and peak switch current reaches 3.2 A. SW_OCP is tripped and the IC skips a switching cycle to reduce the current If the input current level goes above the preset current limit threshold, the part will be shut down in less than 3 µs. This is a latched condition. The fault flag is also set to indicate a fault. This feature protects the input from drawing too much current during heavy load. It also prevents catastrophic failure in the system due to a short of the inductor or output capacitors shorted to GND. The waveform below illustrates the typical input overcurrent fault condition. As soon as input OCP limit is reached, the part disables the gate of the disconnect switch Q1 and latches off. Figure 43: When peak current in SW pin reaches ~3.2 A, overcurrent protection kicks in and the IC skips a switching cycle. There is also a secondary current limit (ISW(LIM2)) that is sensed on the boost switch. This current limit once detected immediately shuts down the A80603. This current limit is set at about 33% higher than the pulse-by-pulse current limit. It is to protect the switch from destructive current spikes in case the boost inductor is shorted. Once this limit is tripped, the A80603 will immediately shut down and latch off. Input Overcurrent Protection and Disconnect Switch VIN iSENSE RSC iADJ To L1 RADJ VSENSE VIN CG Q1 (PMOS) GATE A80603 VIN – VSENSE = RSC × iSENSE + RADJ × iADJ Figure 44: Optional input disconnect switch using a PMOSFET The primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. Figure 45: Startup into an output shorted-to-GND fault. Input OCP is tripped when current (Green trace) exceeds 4 A. PMOS Gate (Red) is turned off immediately and IC latches off. During startup when Q1 first turns on, an inrush current flows through Q1 into the output capacitance. If Q1 turns on too fast (due to its low gate capacitance), the inrush current may trip input OCP limit. In this case, an external gate capacitance CG is added to slow down the turn-on transition. Typical value for CG is around 4.7 to 22 nF. Do not make CG too large, since it also slows down the turn-off transient during a real input OCP fault. Setting the Current Sense Resistor The typical threshold for the current sense is 100 mV when RADJ is 0 Ω. The A80603 can have this voltage trimmed using the RADJ resistor. The typical trip point should be set to at least 3.75 A, which coincides with the cycle-by-cycle peak current limit typical threshold. A sample calculation is done below for 4.2 A of input current. When RADJ is not used: Equation 7: VSENSETRIP = RSC × iSENSE = 100 mV Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 24 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple The desired sense resistor is RSC = 100 mV / 4.2 A = 23.8 mΩ. But this is not a standard E-24 resistor value. Pick the closest lower value which is 22 mΩ. When RADJ is used: Equation 8: VSENSETRIP = RSC × iSENSE + RADJ × iADJ Therefore RADJ = [VSENSETRIP – (RSC × iSENSE)] / iADJ = [100 mV – 92.4 mV] / 20 µA = 380 Ω Input UVLO When VIN and VSENSE rise above VUVLOrise threshold, the A80603 is enabled. The IC is disabled when VIN falls below VUVLOfall threshold for more than 50 μs. This small delay is used to avoid shutting down because of momentary glitches in the input power supply. The possible fault conditions that the part can detect include: • • • • • • • • • • Open LED Pin or open LED string Shorted or partially shorted LED string LED pin shorted to GND Open or shorted boost diode Open or shorted boost inductor VOUT short to GND SW shorted to GND ISET shorted to GND FSET shorted to GND Input disconnect switch drain shorted to GND Note that some of these faults will not be protected if the input disconnect switch is not being used. An example of this is VOUT short to GND fault. Fault Protection During Operation The A80603 constantly monitor the state of the system to determine if any fault conditions occur during normal operation. The response to a triggered fault condition is summarized in the table below. It is important to note that there are several points at which the A80603 monitors for faults during operation. The locations are input current, switch current, output voltage, switch voltage, and LED pins. Some of the protection features might not be active during startup to prevent false triggering of fault conditions. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 25 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Table 5: A80603 Fault Mode Table Fault Name Type Active Fault Flag Set Description Boost Switch Disconnect Switch LED Sink drivers Primary Switch Overcurrent Protection (Cycle-By-Cycle Current Limit) Auto-restart Always NO This fault condition is triggered when the SW current exceeds the cycle-by-cycle current limit, ISW(LIM).The present SW on-time is truncated immediately to limit the current. Next switching cycle starts normally. Off for a single cycle ON ON Secondary Switch Current Limit Latched Off Always YES When current through boost switch exceeds secondary SW current limit (iSW(LIM2)) the device immediately shuts down the disconnect switch, LED drivers and boost. The Fault flag is set. To reset the fault the EN or PWM pin needs to be pulled low for 16 ms. OFF OFF OFF Input Disconnect Current Limit Latched Off YES The device is immediately shut off if the voltage across the input sense resistor is above the VSENSEtrip threshold. To reset the fault the EN or PWM pin must be pulled low for 16 ms. OFF OFF OFF Secondary OVP Latched Off Always YES Secondary overvoltage protection is used for open diode detection. When diode D1 opens, the SW pin voltage will increase until VOVP(SEC) is reached . This fault latches the IC. The input disconnect switch and LED drivers are disabled. To reset the fault the EN or PWM pin needs to be pulled low for 16 ms. OFF OFF OFF LEDx Pin Shorted to GND Auto-restart Startup YES If any of the LED pins is determined to be shorted to GND when PWM first goes high, soft-start process is halted. Only when the short is removed, then soft-start is allowed to proceed. OFF ON OFF LEDx Pin Open Auto-restart Normal operation YES If an LED string is not getting enough current, the device will first respond by increasing the output voltage until OVP is reached. Any LED string that is still not in regulation will be disabled. The device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. ON ON OFF for open pins. ON for all others. ISET Short Protection Auto-restart Always YES Fault occurs when the ISET current goes above 150% of max current. The boost will stop switching and the IC will disable the LED sinks until the fault is removed. When the fault is removed, the IC will try to regulate to the preset LED current. OFF ON OFF YES Fault occurs when the FSET current goes above 150% of max current. The boost will stop switching, Disconnect switch will turn off and the IC will disable the LED sinks until the fault is removed. When the fault is removed, the IC will try to restart with soft-start. OFF OFF OFF STOP during OVP event. ON ON FSET/SYNC Short Protection Auto-restart Always Always Overvoltage Protection Auto-restart Always NO Fault occurs when current into OVP pin exceeds iOVP(th) (typically 150 µA). The IC will immediately stop switching but keep the LED drivers active, to drain down the output voltage. Once the output voltage decreases to ~97% OVP level, the IC will restart switching to regulate the output current. Undervoltage Protection Auto-restart Always YES Device immediately shuts off boost and current sinks if the voltage at VOUT is below VUVP(th). This may happen if VOUT is shorted to GND, or boost diode is open before startup. It will auto-restart once the fault is removed. OFF ON OFF LED String Partial Short Detection Latched and Continue Always YES Fault occurs if an LED pin voltage exceeds VLEDSC with its current sink in regulation, while at least one other LED pin is below ~1.2 V. This may happen when two or more LEDs are shorted within a string. The LED string exceeding the threshold will then be disabled and removed from operation. This fault cannot be detected if PWM ontime is < tLEDSD (5.5 µs max) ON ON OFF for shorted string. ON for all others. Overtemperature Protection Auto-restart Always YES Fault occurs when the die temperature exceeds the over-temperature threshold, typically 170°C. IC will restart after temperatures drops lower by TSDHYS OFF OFF OFF VIN UVLO Auto-restart Always NO Fault occurs when VIN drops below VUVLO(fall), which is 3.9 V max. This fault resets all latched faults. OFF OFF OFF Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 26 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Table 6: A80603-1 Fault Mode Table Fault Name Type Active Fault Flag Set Description Boost Switch Disconnect Switch LED Sink drivers Primary Switch Overcurrent Protection (Cycle-By-Cycle Current Limit) Auto-restart Always NO This fault condition is triggered when the SW current exceeds the cycle-by-cycle current limit, ISW(LIM).The present SW on-time is truncated immediately to limit the current. Next switching cycle starts normally. Off for a single cycle ON ON Secondary Switch Current Limit Latched Off Always YES When current through boost switch exceeds secondary SW current limit (iSW(LIM2)) the device immediately shuts down the disconnect switch, LED drivers and boost. The Fault flag is set. To reset the fault the EN or PWM pin needs to be pulled low for 16 ms. OFF OFF OFF Input Disconnect Current Limit Latched Off YES The device is immediately shut off if the voltage across the input sense resistor is above the VSENSEtrip threshold. To reset the fault the EN or PWM pin must be pulled low for 16 ms. OFF OFF OFF Secondary OVP Latched Off Always YES Secondary overvoltage protection is used for open diode detection. When diode D1 opens, the SW pin voltage will increase until VOVP(SEC) is reached . This fault latches the IC. The input disconnect switch and LED drivers are disabled. To reset the fault the EN or PWM pin needs to be pulled low for 16 ms. OFF OFF OFF LEDx Pin Shorted to GND Auto-restart Startup NO * If any of the LED pins is determined to be shorted to GND when PWM first goes high, soft-start process is halted. Only when the short is removed, then soft-start is allowed to proceed. OFF ON OFF LEDx Pin Open Auto-restart Normal operation NO * If an LED string is not getting enough current, the device will first respond by increasing the output voltage until OVP is reached. Any LED string that is still not in regulation will be disabled. The device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. ON ON OFF for open pins. ON for all others. ISET Short Protection Auto-restart Always YES Fault occurs when the ISET current goes above 150% of max current. The boost will stop switching and the IC will disable the LED sinks until the fault is removed. When the fault is removed, the IC will try to regulate to the preset LED current. OFF ON OFF YES Fault occurs when the FSET current goes above 150% of max current. The boost will stop switching, Disconnect switch will turn off and the IC will disable the LED sinks until the fault is removed. When the fault is removed, the IC will try to restart with soft-start. OFF OFF OFF STOP during OVP event. ON ON FSET/SYNC Short Protection Auto-restart Always Always Overvoltage Protection Auto-restart Always NO Fault occurs when current into OVP pin exceeds iOVP(th) (typically 150 µA). The IC will immediately stop switching but keep the LED drivers active, to drain down the output voltage. Once the output voltage decreases to ~97% OVP level, the IC will restart switching to regulate the output current. Undervoltage Protection Auto-restart Always YES Device immediately shuts off boost and current sinks if the voltage at VOUT is below VUVP(th). This may happen if VOUT is shorted to GND, or boost diode is open before startup. It will auto-restart once the fault is removed. OFF ON OFF ON ON OFF for shorted string. ON for all others. LED String Partial Short Detection Auto-restart Always NO * Fault occurs if an LED pin voltage exceeds VLEDSC with its current sink in regulation, while at least one other LED pin is below ~1.2 V. This may happen when two or more LEDs are shorted within a string. The LED string exceeding the threshold will then be disabled and removed from operation. This fault cannot be detected if PWM ontime is < tLEDSD (5.5 µs max) Overtemperature Protection Auto-restart Always YES Fault occurs when the die temperature exceeds the over-temperature threshold, typically 170°C. IC will restart after temperatures drops lower by TSDHYS OFF OFF OFF VIN UVLO Auto-restart Always NO Fault occurs when VIN drops below VUVLO(fall), which is 3.9 V max. This fault resets all latched faults. OFF OFF OFF * Indicates different behavior between A80603 and A80603-1. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 27 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple A80603 Fault Recovery Mechanism IC Off EN=H & VIN>UVLO Power up (VDD, BG ready; GATE pulled L; Fault checking) Timing Diagram to show how to clear Latched Fault with PWM = L IC Ready EN=L (CLKOUT active, FAULT =L) EN=H & PWM=L Normal Fault Removed OCP EN=H & PWM=H Pin shorted to GND fault  FAULT =L VOUT-GND Shorted Fault i_IN LED Pin Check 0 (In-Use, Disabled, or Shorted-to-GND) Time-out without faults  FAULT =H FAULT Soft Start (boost SW active; LED sinks=on when PWM=H) EN=H & PWM=L for >16 ms EN=L for >16 ms PWM Soft start finished A Running (boost and LED sinks controlled by PWM) fault cleared EN=H & PWM=L for >16 ms EN=L for >16 ms Latching fault detected * Non-latching fault detected * Latched Off (GATE pulled H, boost SW and LED sinks disabled, FAULT =L) Non-Latched Fault State ` 16 ms B C 16 ms D E F Explanation of events : A: VOUT-to-GND Short fault introduced. IC trips input OCP which is a latched fault. FAULT is then pulled Low and IC stays in Latched mode (CLKOUT remains available). B: After PWM=L for 16 ms, IC clears the latched fault internally but FAULT stays Low. C: Input OCP is tripped again since VOUT is still shorted to GND. So IC returns to Latched mode again and FAULT remains Low. D: PWM=H and VOUT -to-GND Short fault is removed, but IC cannot restart since it is still in Latched mode. E: After PWM=L for 16 ms, IC clears the latched fault internally again F: At the next PWM =H, IC restarts and detected no faults, so FAULT finally goes High * Note: Fault conditions may be detected in any state or during any state transition. Most faults are non-latching, meaning the IC will auto-restart as soon as the fault is removed. Only the following faults are latching: Input Disconnect Overcurrent, SW Secondary OCP, and SW Secondary OVP. Latching faults can only be cleared by: 1. Reset the IC by bring VIN below UVLO, 2. Reset the IC by bring EN=L for >16 ms, or 3. EN=H and PWM=L for >16 ms. The last method has the advantage that it does not interrupt the CLKOUT signal. In case the fault condition (e.g. VOUT shorted to GND) is still present when the latching fault is cleared by PWM=L for >16 ms, the IC will trip fault once again and stay latched off. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 28 Wide Input Voltage Range A80603 and LED Driver with Pre-Emptive Boost ALT80600 High Efficiency Fault Tolerant LED Driver A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use Reference Allegro DWG-2871 (Rev. A) or JEDEC MO-220WGGD. Dimensions in millimeters – NOT TO SCALE. Exact case and lead configuration at supplier discretion within limits shown. 0.50 0.30 4.00 ±0.10 24 24 0.95 1 1 2 A 2 2.80 4.10 4.00 ±0.10 DETAIL A 24× 2.80 D 0.08 C 0.75 ±0.05 C +0.05 0.25 –0.07 4.10 SEATING PLANE C PCB Layout Reference View 0.0-0.05 0.50 BSC 0.14 REF 0.20 REF 0.40 ±0.10 0.10 REF 0.05 REF 0.203 REF 0.05 REF 0.40 ±0.10 B 2.70 Detail A +0.10 –0.15 2 1 0.20 REF 24 2.70 +0.10 –0.15 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 0.10 REF Package ES, 24-Contact QFN with Exposed Pad and Wettable Flank Figure 46: Package ES, 24-Pin 4 mm × 4 mm QFN with Exposed Thermal Pad and Wettable Flank Allegro MicroSystems, LLC 115 Northeast Cutoff Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. 955 Perimeter Road 1.508.853.5000; www.allegromicro.com Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 29 A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple Revision History Number Date Description – March 4, 2019 Initial release Copyright 2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 30