A8291

A8291 Single LNB Supply and Control Voltage Regulator Features and Benefits ▪ 2-wire serial I2C™ -compatible interface: control (write) and status (read) ▪ LNB voltages (16 programmable levels) compatible with all common standards ▪ Tracking switch-mode power converter for lowest dissipation ▪ Integrated converter switches and current sensing ▪ Provides up to 500 mA load current ▪ Static current limit circuit allows full current at startup and 13→18 V output transition; reliably starts wide load range ▪ Push-pull output stage minimizes 13→18 V and 18→13 V output transition times for highly capacitive loads ▪ Adjustable rise/fall time via external timing capacitor ▪ Built-in tone oscillator, factory-trimmed to 22 kHz facilitates DiSEqC™ tone encoding, even at no-load ▪ Four methods of 22 kHz tone generation, via I2C™ data bits and/or external pin ▪ Filter bypass MOSFET minimizes losses during tone transmit ▪ 22 kHz tone detector facilitates DiSEqC™ 2.0 decoding ▪ Auxiliary modulation input ▪ LNB overcurrent with timer ▪ Diagnostics for output voltage level, input supply UVLO, and DiSEqC™ tone output ▪ Cable disconnect diagnostic Description Intended for analog and digital satellite receivers, this single low noise block converter regulator (LNBR) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable. The A8291 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. A high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. The high levels of component integration ensure extremely low noise and ripple figures. The A8291 has been designed for high efficiency, utilizing the Allegro® advanced BCD process. The integrated boost switch has been optimized to minimize both switching and static losses. To further enhance efficiency, the voltage drop across the tracking regulator has been minimized. The A8291 has integrated tone detection capability, to support full two-way DiSEqC™ communications. Several schemes are available for generating tone signals, all the way down to no-load, and using either the internal clock or an external Package: 28 pin 5 mm × 5mm MLP/QFN (suffix ET) Continued on the next page… Functional Block Diagram VS C2 100 μF C1 100 nF VREG C3 220 nF VDD R1 R2 R3 R4 R5 R6 fsw EXTM BFC TCAP TDO SDA SCL ADD TDO IRQ PAD GND Tone Detect TDI Fault Monitor I 2 C™Compatible Interface OCP PNG TSD VUV Clock Divider 22 kHz Oscillator TCAP C7 10 nF fsw TGate DAC LNB Voltage Control L1 33 μH D1 L3 1H C4 100 nF C5 100 μF LX GNDLX C6 1 μF BOOST VCP VIN Charge BFC Pump Boost Converter TMode EXTM Wave Shape Linear Stage VPump D2 B R10 1 B D5 B C Regulator C12 BFO BFI R7 15 VOUT LNB C8 D3 220 nF R9 30 C11 0.68 μF A L2 220 μH C13 10 nF C9 220 nF C D4 B A B C R9-C11 network is needed only when a highly inductive load is applied, such as ProBand LNB. D2, D4, D5, and R10 are used for surge protection. Either C12 or C9 should be used, but not both. R8 100 C10 10 nF 8291-DS, Rev.3 A8291 Description (continued) Single LNB Supply and Control Voltage Regulator time source. A DiSEqC™ filter bypass switch is also integrated, to minimize the output impedance during tone generation. A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, cable disconnect, power not good, and tone detect. The device uses a 2-wire bidirectional serial interface, compatible with the I2C™ standard, that operates up to 400 kHz. The A8291 is supplied in a lead (Pb) free 28-lead MLP/QFN. Selection Guide Part Number A8291SETTR-Tb aContact Allegro bLeadframe Packinga 7 in. reel, 1500 pieces/reel 12 mm carrier tape Description ET package, MLP/QFN surface mount 0.90 mm nominal height for additional packing options. plating 100% matte tin. Absolute Maximum Ratings Characteristic Load Supply Voltage, VIN pin Output Current* Output Voltage; BFI, BFO, LNB, LX, and BOOST pins Output Voltage, VCP pin Logic Input Voltage, EXTM and BFC pins Logic Input Voltage, other pins Logic Output Voltage Operating Ambient Temperature Junction Temperature Storage Temperature TA TJ(max) Tstg Symbol VIN IOUT Conditions Rating 16 Internally Limited –1 to 33 –1 to 41 –0.3 to 5 –0.3 to 7 –0.3 to 7 –20 to 85 150 –55 to 150 Units V A V V V V V °C °C °C *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. Package Thermal Characteristics* Package ET RθJA (°C/W) 32 PCB 4-layer * Additional information is available on the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A8291 Single LNB Supply and Control Voltage Regulator Device Pin-out Diagram 27 GNDLX 22 BFO 21 NC 20 NC 19 BFC 18 NC 17 NC 16 NC 15 NC IRQ 14 28 LNB 25 VIN PAD ADD 11 24 BFI SCL 12 BOOST VCP TCAP NC TDO EXTM TDI 1 2 3 4 5 6 7 SDA 10 NC 13 8 9 Terminal List Table Name ADD BFC BFI BFO BOOST EXTM GND GNDLX IRQ LNB LX NC PAD SCL SDA TCAP TDI TDO VCP VIN VREG Number 11 19 24 22 1 6 8 27 14 28 26 4, 13, 15-18, 20, 21, 23 Pad 12 10 3 7 5 2 25 9 Address select Bypass FET control Bypass FET input (connect to LNB) Bypass FET output Tracking supply voltage to linear regulator External modulation input Signal ground Boost switch ground Interrupt request Output voltage to LNB Inductor drive point No connection Exposed pad; connect to the ground plane, for thermal dissipation I2C™-compatible clock input I2C™-compatible data input/output Capacitor for setting the rise and fall time of the LNB output Tone detect input Tone detect output Gate supply voltage Supply input voltage Analog supply Function VREG GND (Top View) 23 NC 26 LX Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A8291 Single LNB Supply and Control Voltage Regulator ELECTRICAL CHARACTERISTICS at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1 Characteristics General Set-Point Accuracy, Load and Line Regulation Err IIN(Off) Supply Current Boost Switch On Resistance Switching Frequency Switch Current Limit Linear Regulator Voltage Drop TCAP Pin Current Output Voltage Rise Time2 Output Voltage Pull-Down Time2 Output Reverse Current Ripple and Noise on LNB Output, Peak-to-Peak2 Protection Circuitry Output Overcurrent Limit Overcurrent Disable Time VIN Undervoltage Lockout Threshold VIN Turn On Threshold Undervoltage Hysteresis Thermal Shutdown Threshold2 Thermal Shutdown Hysteresis2 Power Not Good Flag Set Power Not Good Flag Reset Power Not Good Hysteresis Cable Disconnect Boost Voltage Cable Disconnect Set Cable Disconnect Current Source ILIMLNB tDIS VUVLO VIN(th) VUVLOHYS TJ ∆TJ PNGSET PNGHYS VCAD VCADSET ICADSRC VLNB = 21.00 V, VBOOST = 22.8 V With respect to VLNB With respect to VLNB CADT bit = 1, ENB bit = 1, VSEL0 through VSEL3 = 1 PNGRESET With respect to VLNB VIN falling VIN rising 500 40 7.05 7.40 – – – 77 82 – 22.0 20.16 1.0 600 48 7.35 7.70 350 165 20 85 90 5 22.8 21.00 1.75 700 56 7.65 8.00 – – – 93 98 – 23.5 21.84 2.5 mA ms V V mV °C °C % % % V V mA IIN(On) Relative to selected VLNB target level, ILOAD = 0 to 450 mA ENB bit = 0, LNB output disabled, VIN = 12 V ENB bit = 1, LNB output enabled, ILOAD = 0 mA, VIN = 12 V –4.5 – – – 320 2.2 VBOOST – VLNB, no tone signal, ILOAD = 450 mA TCAP capacitor (C7) charging TCAP capacitor (C7) discharging For VLNB 13 → 18 V; CTCAP = 5.6 nF, ILOAD = 450 mA For VLNB 18 → 13 V; CLOAD = 100 μF, ILOAD = 0 mA ENB bit = 0, VLNB = 33 V , BOOST capacitor (C5) fully charged 20 MHz bandwidth 600 –12.5 7.5 – – – – – – – 300 352 3.0 800 –10 10 500 12.5 1 30 4.5 10.0 19.0 600 384 4.0 1000 –7.5 12.5 – – 5 – % mA mA mΩ kHz A mV μA μA μs ms mA mVPP Symbol Test Conditions Min. Typ. Max. Units RDS(on)BOOST ILOAD = 450 mA fSW ILIMSW ∆VREG ICHG IDISCHG tr(VLNB) tf(VLNB) IRLNB Vrip,n(pp) Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A8291 Single LNB Supply and Control Voltage Regulator ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1 Characteristics Bypass FET Bypass FET Control (BFC) Logic Input Input Leakage Bypass FET On Resistance Turn On/Off Delay2 Tone Tone Frequency Tone Amplitude, Peak-to-Peak Tone Duty Cycle Tone Rise Time Tone Fall Time EXTM Logic Input EXTM Input Leakage Tone Detector Tone Detect Input Amplitude Receive, Peak-to-Peak Tone Detect Input Amplitude Transmit, Peakto-Peak Tone Reject Input Amplitude, Peak-to-Peak Frequency Capture Input Impedance2 TDO Output Voltage TDO Output Leakage I2C™-Compatible Interface Logic Input (SDA,SCL) Low Level Logic Input (SDA,SCL) High Level Logic Input Hysteresis Logic Input Current Logic Output Voltage SDA and IRQ Logic Output Leakage SDA and IRQ SCL Clock Frequency Output Fall Time Bus Free Time Between Stop/Start Hold Time Start Condition Setup Time for Start Condition SCL Low Time VSCL(L) VSCL(H) VI2CIHYS II2CI Vt2COut(L) Vt2CLKG fCLK tfI2COut tBUF tHD:STA tSU:STA tLOW Vt2COut(H) to Vt2COut(L) VI2CI = 0 to 7 V ILOAD = 3 mA Vt2COut = 0 to 7 V – 2.0 – –10 – – – – 1.3 0.6 0.6 1.3 – – 150 800 mA 10 nF, 10 VMIN, X5R or X7R, 0402 or 0603 10 nF, 50 V, X5R or X7R, 0402 or 0603 TDK: C2012X5R1E684K Murata: GRM21BR71E684KA88 Kemet: C0805C684K3PAC AVX: 08053D684KAT2A TDK: C3216X7R1E105K Murata: GRM31MR71E105KA01 Taiyo Yuden: TMK316BJ105KL-T Kemet: C1206C105K3RACTU Diodes, Inc: B140HW-7 Central Semi: CMMSH1-40 Vishay: 1.5KE24A-E3/54 Diodes, Inc.: 1.5KE24A-T Sanken: SFPB-74 Vishay: B340A-E3/5AT Diodes, Inc: B340A-13-F Central Semi: CMSH3-40MA TDK: TSL0808RA-330K1R4-PF Taiyo Yuden: LHLC08TB330K Coilcraft: DR0608-333L TDK: TSL0808RA-221KR54-PF Taiyo Yuden: LHLC08TB221K Coilcraft: DR0608-224L Kemet: LB3218-T1R0MK Murata: LQM31PN1R0M00L Taiyo Yuden: LB3218T1R0M TDK: MLP3216S1R0L ChemiCon: EKZE500ELL101MHB5D Nichicon: UHC1V101MPT Manufacturer Device C11 0.68 μF, 25 VMIN, X5R or X7R, 0805 C6 1.0 μF, 25 VMIN, X5R or X7R, 1206 D1, D2, D3 Schottky diode, 40 V, 1 A, SOD-123 TVS, 24 V, 200 A, 1500 W; Use one TVS to provide surge protection up to 3 kV and two TVSs for protection from 3 kV to 6 kV (1.2/50, 8/20, 12 A, per IEC61000-4-5) D4 D5 Schottky diode, 40 V, 3 A, SMA L1 33 μH, ISAT > 1.3 A, DCR < 130 mΩ L2 220 μH, ISAT > 0.5 A, DCR < 0.8 Ω L3 1 μH, 1 A, DCR < 120 mΩ, 1206 R1 to R6 R7 R8 R9 R10 *Either Determined by VDD, bus capacitance, etc. 15 Ω, 1%, 1/8 W 100 Ω, 1%, 1/8 W 30 Ω, 1/8 W 1 Ω, 1/8 W C9 or C12 are used, but not both. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 17 A8291 Single LNB Supply and Control Voltage Regulator Package ET 28-Pin MLP/QFN 5.15 .203 4.85 .191 All dimensions reference only, not for tooling use (reference JEDEC MO-220VHHD) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 28 1 2 A B A 5.15 .203 4.85 .191 28X 0.08 [.003] C 28X 0.30 .012 0.18 .007 0.10 [.004] M C A B 0.05 [.002] M C 0.50 .020 SEATING PLANE 1.00 .039 0.80 .031 0.20 .008 REF 0.05 .002 0.00 .000 C 0.30 .012 NOM 1.15 .045 NOM 28 0.50 .020 NOM 3.15 NOM .124 1 2 4X0.20 .008 MIN C 4.8 .189 NOM 0.65 .026 0.45 .018 B 3.15 NOM .124 2 1 24X0.20 .008 MIN 3.15 NOM .124 4.8 .189 NOM R0.30 .012 REF 3.15 NOM 4X 0.20 .008 MIN .124 28 I2C™ is a trademark of Philips Semiconductors. DiSEqC™ is a trademark of Eutelsat S.A. Copyright ©2005, 2007, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 18