A8584
Wide Input Voltage, 500 kHz , 2.5 A, Asynchronous Buck Regulator
FEATURES AND BENEFITS
DESCRIPTION
• Automotive AEC-Q100 qualified
• Wide operating voltage range: 4.7 to 36 V
• UVLO stop threshold is at 3.8 V (typ)
• Supports 40 V input for surge and load dump testing
• Adjustable output voltage as low as 0.8 V
• Internal 800 mV reference with ±1.5% accuracy
• Internal 100 mΩ high-side switching MOSFET
• Adjustable switching frequency, fSW: 250 to 500 kHz
• Synchronization to external clock: 1.2 × fSW to 1.5 × fSW
• Sleep mode supply current less than 3 μA
• Soft start time externally set via the SS pin
• Very low no-load current
• Pre-bias startup compatible
• Power OK (POK) output
• Pulse-by-pulse current limiting (OCP)
• Hiccup mode short-circuit protection (HIC)
• Overtemperature protection (TSD)
• Open-circuit and adjacent pin short-circuit tolerant
• Short-to-ground tolerant at every pin
• Externally adjustable compensation
• Stable with ceramic output capacitors
The A8584 is an adjustable frequency, high output current,
PWM regulator that integrates a low resistance, high-side,
N-channel MOSFET. The A8584 incorporates current-mode
control to provide simple compensation, excellent loop
stability, and fast transient response. The A8584 utilizes
external compensation to accommodate a wide range of power
components to optimize transient response without sacrificing
stability.
The A8584 regulates input voltages from 4.7 to 36 V, down
to output voltages as low as 0.8 V, and can supply approximately
2.5 A of load current. The A8584 features include an
externally adjustable switching frequency, an externally set
soft start time to minimize inrush currents, an EN/SYNC input
to either enable VOUT and/or synchronize the PWM switching
frequency, and a Power OK (POK) output to indicate when
VOUT is within regulation. The A8584 only turns on the
lower FET to charge the boot capacitor when needed, not at
Continued on the next page…
APPLICATIONS:
PACKAGE: 16-pin TSSOP (suffix LP)
• GPS/infotainment
• Automobile audio
• Home audio
• Network and telecom
Not to scale
Typical Application
V IN
1
2
3
CIN
5
12
7
4
CSS
8
11
RFSET
RZ
CP
VIN
VIN
VIN
GND
GND
SW
SW
A8584
BOOT
LO
16
15
D1
VOUT
CO1
CBOOT
14
EN/SY NC
SS
FSET
FB
COMP
9
RFB1
PAD
RFB2
CZ
POK
6
RPU
POK
Figure 1. Typical application
A8584-DS, Rev. 4
MCO-0000845
May 9, 2022
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
DESCRIPTION (continued)
every PWM cycle. This improves light load efficiency and provides
no-load currents low. The sleep mode current of the A8584 control
circuitry is less than 3 µA.
In addition, the A8584 provides adjacent pin short-circuit and
short-to-ground protection at every pin to satisfy the most
demanding applications.
Protection features include VIN undervoltage lockout (UVLO),
pulse-by-pulse overcurrent protection (OCP), hiccup mode
short-circuit protection (HIC), and thermal shutdown (TSD).
The A8584 device is available in a 16-pin TSSOP package with
exposed pad for enhanced thermal dissipation. It is lead (Pb) free,
with 100% matte tin leadframe plating.
SELECTION GUIDE
Part Number
Packing
A8584KLPTR-T
4000 pieces per 13-in. reel
ABSOLUTE MAXIMUM RATINGS [1]
Characteristic
Symbol
VIN Pin to GND
Notes
VIN
SW Pin to GND [2]
SS Pin
All Other Pins
Unit
–0.3 to 40
V
Continuous
–0.3 to VIN + 0.3
V
Single pulse, tW < 50 ns
–1.0 to VIN + 5.0
V
VBOOT
VSW – 0.3 to
VSW + 7.0
V
VSS
–0.3 to VIN + 0.3
V
VI
–0.3 to 5.5
V
VSW
BOOT Pin Above SW Pin
Rating
Operating Ambient Temperature
TA
–40 to 125
°C
Maximum Junction Temperature
TJ(max)
150
°C
Tstg
–55 to 150
°C
Storage Temperature
K temperature range for automotive
[1] Stresses
beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to absolute-maximum–rated conditions for extended periods may affect device reliability.
[2] SW has internal clamp diodes to GND and VIN. Applications that forward bias these diodes should take care not to exceed the IC
package power dissipation limits.
THERMAL CHARACTERISTICS
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
On 4-layer PCB based on JEDEC standard
Value
Unit
34
°C/W
*Additional thermal information available on the Allegro website
Table of Contents
Specifications
2
Functional Block Diagram
3
4
Typical Characteristic Performance
8
Pin-out Diagram and Terminal List
Functional Description
10
10
14
Overview
Protection Features
Application Information
16
16
Package Outline Drawing
31
Design and Component Selection
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
Functional Block Diagram
BOOT
VIN
VIN
VREG
VREF 0.8 V
POR
Regulator
fSW
OSC
Adj
PWM Clk
Slope
Compensation
0.85 V
Typ
∑
Sleep
BS UVLO
–
TSD
3.5 kΩ
VREF
FBOK
POK
Rising
–
85%×VREF
90%×VREF
150 nA
FB
+
Clamp 1.7 V Typ
–
+
+
COMP
Error
Amp
OCP
Hiccup reset VSS = 235 mV Typ
10 µA
BOOT
– SW
FAULT A
Fault
Logic
UVLO (VIN)
VSS –
400 mV
2.9 V
OFF
POR
Latch reset
EN/SYNC
toggle
EN Digital
SW
10 Ω
tOFF(MIN)
–
40 kΩ Typ
SS
Diode
Missing
R Q
+
1.25 V Typ
1.65 V Typ
SW
VREG
EN/SYNC
Comp
EN/SYNC
100
mΩ
Reset
DOM
S Q
PWM
Comp
PWM
Ramp
Offset
300 mV
–
+
Current Sense
Amp
OCP
SYNC
Adj
FSET
EN/SYNC >1.2 × fSW
FBOK
UVLO
(VIN)
+
VIN
20 µA
1500 Ω
Latched
Hiccup
Protection
HICCUP
B
OFF
GND
GND
PAD
A FAULT = 1, if:
EN = 0, or
UVLO = 1
B HICCUP = 1, if Hiccup protection enabled (VFB < 625 mV) and
a net count of > 7 OCP events occur
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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3
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
Pinout Diagram
VIN 1
16 SW
VIN 2
15 SW
VIN 3
14 BOOT
SS 4
GND 5
POK 6
EN/SYNC 7
FSET 8
PAD
13 NC
12 GND
11 COMP
10 GND
9 FB
Terminal List Table
Number
Name
Description
1, 2, 3
VIN
Power input for the control circuits and the drain of the internal high-side N-channel
MOSFET. Connect this pin to a power supply of 4.7 to 36 V. A high quality ceramic capacitor
should be placed very close to this pin.
4
SS
Soft-start pin. Connect a capacitor, CSS, from this pin to GND to set the soft-start time. This
capacitor also determines the hiccup period during an overcurrent event.
5, 10, 12
GND
Ground.
6
POK
Power OK output signal. This pin is an open drain output that transitions from low impedance
to high impedance when the output is within the final regulation voltage.
7
EN/SYNC
Enable and synchronization input. This pin is a logic input that turns the converter on or
off. Set this pin to logic high to turn the converter on or set this pin to logic low to turn the
converter off. This pin also functions as a synchronization input to allow the PWM frequency
to be set by an external clock.
8
FSET
9
FB
11
COMP
13
NC
14
BOOT
15, 16
SW
The source of the internal high-side N-channel MOSFET. The external free-wheeling diode
(D1) and output inductor (LO) should be connected to this pin. Both D1 and LO should be
placed close to this pin and connected with relatively wide traces.
–
PAD
Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad.
Frequency setting pin. A resistor, RFSET, from this pin to GND sets the PWM switching
frequency. See figure 10 and/or equation 2 to determine the value of RFSET.
Feedback (negative) input to the Error amplifier. Connect a resistive divider from the
converter output node, VOUT , to this pin to program the output voltage.
Output of the error amplifier and compensation node for the current-mode control loop.
Connect a series RC network from this pin to GND for loop compensation. See the Design
and Component Selection section of this datasheet for further details.
No connect.
High-side gate drive boost input. This pin supplies the drive for the high-side N-channel
MOSFET. Connect a 100 nF ceramic capacitor from BOOT to SW.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
ELECTRICAL CHARACTERISTICS [1]: Valid at VIN = 12 V, TA = 25°C ,
–40°C ≤ TJ ≤ 125°C ; unless otherwise specified
Characteristics
Symbol
indicates specifications guaranteed through
Test Conditions
Min.
Typ. [2]
Max.
Unit
INPUT VOLTAGE SPECIFICATIONS
Operating Input Voltage Range
VIN
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
VINSTART
VIN rising
VINSTOP
VIN falling
4.7
−
36
V
−
4.2
4.6
V
−
3.8
4.2
V
280
400
520
mV
VEN/SYNC = 5 V, VFB = 1.5 V,
no PWM switching
−
3.0
5.0
mA
IQSLEEP
VIN = 16 V, VEN/SYNC ≤ 0.4 V,
TA = TJ between –40°C and 85°C
−
−
3.0
μA
VIN = 16 V, VEN/SYNC ≤ 0.4 V, TA = TJ = 125°C
−
5
15
μA
VFB
4.7 V < VIN < 36 V, VFB = VCOMP
788
800
812
mV
IFB
VCOMP = 1.5 V, VFB regulated so that
ICOMP = 0 A
−
–150
–300
nA
–
56
–
dB
VUVLOHYS
INPUT CURRENTS
Input Quiescent Current
IQ
Input Sleep Supply Current [3]
REFERENCE VOLTAGE
Feedback Voltage
ERROR AMPLIFIER
Feedback Input Bias Current
Open Loop Voltage Gain
AVOL
Transconductance
gm
ICOMP = 0 μA, VSS > 700 mV
550
750
1000
μA/V
0 V < VSS < 700 mV
–
225
–
μA/V
Source Current
IEA(SRC)
VFB < 0.8 V, VCOMP = 1.5 V
−
–50
−
μA
Sink Current
IEA(SINK)
VFB > 0.8 V, VCOMP = 1.5 V
−
+50
−
μA
Maximum Output Voltage
VEAVO(max)
COMP Pull-Down Resistance
RCOMP
1.3
1.7
2.1
V
FAULT = 1
−
1500
−
Ω
VCOMP for 0% duty cycle
−
300
−
mV
ns
PULSE WIDTH MODULATION (PWM)
PWM Ramp Offset
VPWMOFFSET
Minimum Controllable On-Time
tON(MIN)
−
100
150
Minimum Switch Off-Time
tOFF(MIN)
−
100
150
ns
COMP to SW Current Gain
gmPOWER
−
2.85
−
A/V
fSW = 250 kHz
−
0.19
−
A/μs
fSW = 500 kHz
−
0.38
−
A/μs
IDS = 400 mA, VBOOT − VSW = 6 V
−
100
−
mΩ
VIN = 16 V, VEN/SYNC ≤ 0.4 V, VSW = 0 V
TA = TJ between –40°C and 85°C
−
−
10
μA
VIN = 16 V, VEN/SYNC ≤ 0.4 V, VSW = 0 V,
TA = TJ = 125°C
−
50
150
µA
IDS = 10 mA, (VBOOT – VSW) < 4 V
−
10
12
Ω
Slope Compensation
SE
MOSFET PARAMETERS
Hi-Side MOSFET On Resistance
High-Side MOSFET Leakage
Current [3]
Low-Side MOSFET On Resistance
RDS(on)HS
ILEAK
RDS(on)LS
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at VIN = 12 V, TA = 25°C ,
–40°C ≤ TJ ≤ 125°C ; unless otherwise specified
Characteristics
Symbol
Test Conditions
indicates specifications guaranteed through
Min.
Typ. [2]
Max.
Unit
−
250
−
kHz
OSCILLATOR FREQUENCY
Oscillator Frequency
fSW
RFSET = 105 kΩ
SYNCHRONIZATION TIMING
Synchronization Frequency Range
fSW_MULT
1.2 × fSW
−
1.5 × fSW
kHz
Synchronized PWM Frequency
fSW_SYNC
−
−
750
kHz
Synchronization Input Duty Cycle
DSYNC
−
−
80
%
Synchronization Input Pulse Width
tWSYNC
200
−
−
ns
Synchronization Input Edge Rise Time
trSYNC
−
10
15
ns
Synchronization Input Edge Fall Time
tfSYNC
−
10
15
ns
ENABLE/SYNCHRONIZATION INPUT
EN/SYNC High Threshold
VENIH
VEN/SYNC rising
−
1.65
1.80
V
EN/SYNC Low Threshold
VENIL
VEN/SYNC falling
−
1.25
−
V
0.40
0.85
−
V
−
400
−
mV
EN/SYNC Low Threshold (Sleep)
EN/SYNC Hysteresis
EN/SYNC Digital Delay
EN/SYNC Input Resistance
VENILSLEEP VEN/SYNC falling
VENHYS
tSLEEP
VENIH – VENIL
−
32
−
PWM
cycles
20
40
−
kΩ
Duty cycle = 5%
−
3.25
−
A
VEN/SYNC transitioning high or low cycles
REN/SYNC
OVERCURRENT PROTECTION (OCP) AND HICCUP MODE
Pulse-by-Pulse Current Limit
Hiccup Disable Threshold
Hiccup Enable Threshold
OCP / HICCUP Count Limit
ILIM
Duty cycle = 40%
−
3.0
−
A
VHICDIS
VFB rising
−
750
−
mV
VHICEN
VFB falling
−
625
−
mV
Hiccup enabled, OCP pulses
−
7
−
counts
255
330
−
mV
−
235
310
mV
OCPLIMIT
SOFT START (SS)
SS COMP Release Voltage
VSSRELEASE VSS rising due to ISSSU
SS Fault/Hiccup Reset Voltage
VSSRESET
VSS falling due to ISSHIC
SS Maximum Charge Voltage
VSSCHRG
SS Startup (Source) Current
ISSSU
VSS = 1 V, HICCUP = FAULT = 0
SS Hiccup (Sink) Current
ISSHIC
VSS = 0.5 V, HICCUP = 1
−
3.1
−
V
−10
–20
−30
μA
5
10
20
μA
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at VIN = 12 V, TA = 25°C ,
–40°C ≤ TJ ≤ 125°C ; unless otherwise specified
Characteristics
Symbol
Test Conditions
indicates specifications guaranteed through
Min.
Typ. [2]
Max.
Unit
FAULT = 1
−
3.5
−
kΩ
SOFT START (SS) (continued)
SS Input Resistance
SS to VOUT Delay Time
RSS
tSSDELAY
CSS = 22 nF
−
363
−
μs
VOUT Soft Start Ramp Time
tSS
CSS = 22 nF
−
880
−
μs
SS Switching Frequency
fSS
VFB = 0 V
−
fSW / 3
−
MHz
VFB ≥ 600 mV
−
fSW
−
MHz
VPOK
IPOK = 4 mA
−
−
0.4
V
POK Leakage
IPOKLEAK
VPOK = 5 V
−
−
1
μA
POK Comparator Threshold
VPOKTHRESH
VFB rising, as a percentage of VREF
87
90
93
%
POK Hysteresis
VPOKHYS
VFB falling, as a percentage of VREF
2
5
6
%
POWER OK (POK) OUTPUT
POK Output Voltage
POK Digital Delay
tdPOK
VFB rising only
TTSD
Temperature rising
−
7
−
PWM
cycles
150
165
−
°C
−
20
−
°C
THERMAL PROTECTION (TSD)
Thermal Shutdown Threshold [4]
Thermal Shutdown
Hysteresis [4]
TTSDHYS
[1] For
input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as
going into the node or pin (sinking).
[2] Typical specifications are at T = 25°C.
A
[3] For T = T between –40°C and 85°C, ensured by design and characterization, not production tested.
A
J
[4] Ensured by design and characterization, not production tested.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
Typical Characteristic Performance
Switching Frequency versus Temperature
263
803
802
801
800
799
798
797
796
-50
-25
0
25
50
75
100
125
150
175
Switching Frequency, fSW (MHz)
804
261
260
259
258
257
256
255
254
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Soft Start (Source) Current versus Temperature
Soft Start Hiccup (Sink) Current versus Temperature
–16
–17
–18
–19
–20
-50
-25
0
25
50
75
100
125
150
175
10.0
9.9
9.8
9.7
9.6
9.5
-50
-25
Ambient Temperature, TA (°C)
750
700
650
-25
0
25
50
75
100
Ambient Temperature, TA (°C)
25
50
75
100
125
150
175
Error Amplifier Voltage Gain versus Temperature
125
150
175
Open Loop Voltage Gain, AVOL (dB)
800
600
-50
0
Ambient Temperature, TA (°C)
Error Amplifier Transconductance versus Temperature
Transconductance, gm (μA/V)
262
Ambient Temperature, TA (°C)
SS Hiccup (Sink) Current, ISSHIC (µA)
SS Startup (Source) Current, ISSSU (µA)
Reference Voltage, VREF (mV)
Reference Voltage versus Temperature
VIN = 4.7 V
58
57
56
55
54
53
52
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
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955 Perimeter Road
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8
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
UVLO Threshold Voltage versus Temperature
Enable Threshold Voltage versus Temperature
4.2
VINSTART (VIN rising)
4.1
4.0
3.9
VINSTOP (VIN falling)
3.8
3.7
-50
Input Quiescent Current, IQ (µA)
EN/SYNC Threshold, VENx (V)
1.4
-25
0
25
50
75
100
125
150
175
1.3
VENIH (Run: VEN/SYNC rising)
1.2
1.1
1.0
0.9
VENILSLEEP (Sleep: VEN/SYNC falling)
0.8
0.7
0.6
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
Sleep Input Current versus Temperature
SW Leakage Output Current versus Temperature
VIN = 16 V, EN/SYNC = Low
5
4
3
2
1
0
–1
-50
-25
0
25
50
75
100
Ambient Temperature, TA (°C)
VIN = 16 V, EN/SYNC = Low
60
High-Side MOSFET Leakage,
ILEAK (µA)
UVLO Threshold, VINx (V)
4.3
125
150
175
50
40
30
20
10
0
–10
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
FUNCTIONAL DESCRIPTION
Overview
The A8584 is an asynchronous PWM regulator that incorporates
all the control and protection circuitry necessary to satisfy a wide
range of applications. The A8584 employs current mode control
to provide fast transient response, simple compensation, and
excellent stability. The features of the A8584 include a precision
reference, an adjustable switching frequency, a transconductance
error amplifier, an enable/synchronization input, an integrated
high-side N-channel MOSFET, adjustable soft-start time, pre-bias
startup, low current sleep mode, and a Power OK (POK) output.
The protection features of the A8584 include undervoltage lockout (UVLO), pulse-by-pulse over current protection (OCP), hiccup mode short-circuit protection (HIC), and thermal shutdown
(TSD). In addition, the A8584 provides open-circuit, adjacent pin
short-circuit, and pin-to-ground short-circuit protection.
Reference Voltage
The A8584 incorporates an internal reference that allows output
voltages as low as 0.8 V. The accuracy of the internal reference
is ±1.5% through the operating temperature range. The output
voltage of the regulator is adjusted by connecting a resistor
divider (RFB1 and RFB2 in figure 1) from VOUT to the FB pin
of the A8584.
Oscillator/Switching Frequency
The PWM switching frequency of the A8584 is adjustable from
250 kHz to 500 kHz and has an accuracy of ±12% through the
operating temperature range. Connecting a resistor from the
FSET pin to GND, as shown in figure 1, sets the switching
frequency. An FSET resistor with 1% tolerance is recommended.
A graph of switching frequency versus FSET resistor value is
shown in the Design and Component Selection section of this
datasheet.
Transconductance Error Amplifier
The primary function of the transconductance error amplifier
is to regulate the converter output voltage. The error amplifier
is shown in figure 2. It is shown as a 3-terminal input device
with two positive and one negative inputs. The negative input is
simply connected to the FB pin and is used to sense the feedback
voltage for regulation. The two positive inputs are used for soft
start and regulation. The error amplifier performs an “analog OR”
selection between the two positive inputs. The error amplifier
regulates to either the soft start pin voltage (minus 400 mV) or
the A8584 internal reference, whichever is lower.
To stabilize the regulator, a series RC compensation network
(RZ and CZ) must be connected from the error amplifier output
(COMP pin) to GND as shown in figure 1. In some applications,
an additional, a low value capacitor (CP) may be connected in
parallel with the RC compensation network to reduce the loop
gain at higher frequencies. However, if the CP capacitor is too
large, the phase margin of the converter may be reduced. If the
regulator is disabled or a fault occurs, the COMP pin is immediately pulled to GND via approximately 1500 Ω, and PWM
switching is inhibited.
Slope Compensation
The A8584 incorporates internal slope compensation to allow
PWM duty cycles above 50% for a wide range of input/output
voltages, switching frequencies, and inductor values. As shown in
the Functional Block Diagram, the slope compensation signal is
added to the sum of the current sense and PWM ramp offset. The
amount of slope compensation is scaled directly with the switching frequency.
400 mV
A8584
SS
+
Error Amplifier
+
VREF
800 mV
COMP
-
FB
Figure 2. The A8584 transconductance error amplifier
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
10
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
Sleep Mode
If the voltage at the EN/SYNC pin is pulled below 400 mV
(VENILSLEEP ) the A8584 will enter a sleep mode where the internal control circuits will be shut off and draw less than 3 µA from
VIN . However, the total current drawn by the VIN pin will be the
sum of the current drawn by the control circuitry ( VENIH ), the A8584 will turn on and,
provided there are no fault conditions, soft start will be initiated
and VOUT will ramp to its final voltage in a time set by the soft
start capacitor (CSS). (The operating modes of the A8584 based
on EN/SYNC voltage are summarized in figure 3.)
• A synchronization input that accepts an external clock to turn on
the A8584 and (after soft starting) will scale the PWM switching frequency from 1.2X to 1.5X above the base frequency set
by the FSET resistor.
V IN
R
EN/SYNC
A8584
2.2 V < V Z < 4.7 V
Figure 4. Automatically enabling the A8584 from VIN or some other
power rail
VEN > 1.15 V
VEN > 1.65 V
SLEEP
WAKE
RUN
(iIN < 3 µA
PWM = Off )
(iIN ≈ 2 mA
PWM = Off )
(iIN ≈ 3 mA
PWM = On )
VEN < 0.85 V
for 32 cycles
VEN > 1.15 V
VSS < 0.2 V
Discharge
Soft-start capacitor
Wait up to
32 cycles
(PWM = Off)
(PWM = On)
VEN < 0.85 V
Timer expired
Figure 3. EN/SYNC voltage and A8584 operating modes
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
down transition delay from switching to sleep mode is shown in
figure 5.
offset, the slope compensation, and the current sense signal rises
above the error amplifier voltage, the comparator will reset the
PWM flip-flop and the upper MOSFET will be turned off. If the
output voltage of the error amplifier drops below the PWM Ramp
Offset (VPWMOFFSET) then zero PWM duty-cycle (pulse skipping)
operation is achieved.
Power MOSFETs
The A8584 includes a low RDS(on) , high-side N-channel
MOSFET capable of delivering up to 2.6 A (typ) of current
at 90% duty cycle. The A8584 also includes a 10 Ω, low-side
MOSFET to insure the boot capacitor (CBOOT) is always
charged.
Current Sense Amplifier
Unlike other typical asynchronous regulators, the A8584 only
turns on the lower MOSFET when the boot capacitor must be
charged. This minimizes negative currents in the output inductor
and improves the light load efficiency. When the EN/SYNC input
is low or a fault occurs, the A8584 is disabled and the regulator output stage is tristated by turning off both the upper and
lower MOSFETs.
Pulse Width Modulation (PWM)
A high-speed PWM comparator, capable of pulse widths less
than 100 ns, is included in the A8584. The inverting input of
the comparator is connected to the output of the error amplifier.
The noninverting input is connected to the sum of the current
sense signal, the slope compensation, and a PWM Ramp Offset
(VPWMOFFSET, nominally 300 mV). At the beginning of each
PWM cycle, the CLK signal sets the PWM flip-flop and the
upper MOSFET is turned on. When the summation of the DC
A high-bandwidth current sense amplifier monitors the current in
the upper MOSFET. The PWM comparator, the pulse-by-pulse
current limiter, and the hiccup mode up/down counter require the
current signal.
Soft Start (Startup) and Inrush Current Control
Inrush currents to the converter are controlled by the soft start
function of the A8584. When the A8584 is enabled and all faults
are cleared, the soft start (SS) pin will source approximately
20 μA (ISSSU) and the voltage on the soft start capacitor (CSS)
will ramp upward from 0 V. When the voltage on the soft start
pin exceeds the Soft Start COMP Release Voltage threshold
(VSSRELEASE , 330 mV typical, measured at the soft start pin) the
output of the error amplifier is released, and shortly thereafter the
upper and lower MOSFETs will begin switching. As shown in
figure 6, there is a short delay (tSSDELAY) to initiate PWM switching, between when the EN/SYNC pin transitions high and when
the soft start voltage reaches 330 mV.
VOUT
C1
VCOMP
32 cycles delay
C2
VEN/SYNC
C3
t
Figure 5. PWM switching stops and sleep mode begins approximately
32 cycles after EN/SYNC transitions low; shows VOUT (ch1, 1 V/div.),
VCOMP (ch2, 1 V/div.), VEN/SYNC (ch3, 2 V/div.), t = 50 µs/div.
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
When the A8584 begins PWM switching, the error amplifier
regulates the voltage at the FB pin to the soft start pin voltage
minus the Soft Start PWM Threshold voltage (VSSPWM). When
PWM switching starts, the voltage at the soft start pin rises from
330 mV to 1.13 V (a difference of 800 mV), the voltage at the FB
pin rises from 0 V to 800 mV, and the regulator output voltage
rises from 0 V to the required set-point determined by the feedback resistor divider (RFB1 and RFB2).
When the voltage at the soft start pin reaches approximately
1.13 V, the error amplifier will “switch over” and begin regulating to the A8584 internal reference, 800 mV. The voltage at the
soft start pin will continue to rise to about 3.3 V. The soft start
functionality is shown in figure 6.
If the A8584 is disabled or a fault occurs, the internal fault latch
is set and the soft start pin is pulled to GND via approximately
3.5 kΩ. The A8584 will clear the internal fault latch when the
voltage at the soft start pin decays to approximately 235 mV
(VSSRESET).
If the A8584 enters hiccup mode, the capacitor on the soft start
pin is discharged by a 10 μA current sink (ISSHIC ). Therefore, the
soft start pin capacitor value (CSS) controls the time between soft
start attempts. Hiccup mode operation is discussed in more detail
in the Output Short Circuit (Hiccup Mode) Protection section of
this datasheet. During startup, the PWM switching frequency is
scaled linearly from fSW / 3 to fSW as the voltage at the FB pin
ramps from 0 V to 600 mV. This is done to minimize the peak
current in the output inductor when the input voltage is high and
VEN/SYNC
C1
C2
C3
tSS
If the output capacitors are pre-biased to some voltage, the A8584
will modify the normal startup routine to prevent discharging
the output capacitors. Normally, the COMP pin is released and
PWM switching starts when the voltage at the soft start pin
reaches 330 mV. In the case with pre-bias at the output, the prebias voltage will be sensed at the FB pin. The A8584 will not
start switching until the voltage at the soft-start pin increases to
approximately VFB + 330 mV. At this soft start pin voltage, the
error amplifier output is released, the voltage at the COMP pin
rises, PWM switching starts, and VOUT will ramp upward starting
from the pre-bias level. Figure 7 shows startup when the output
voltage is pre-biased to 2.0 V.
Power OK (POK) Output
The Power OK (POK) output is an open drain output, so an
external pull-up resistor must be connected. An internal comparator monitors the voltage at the FB pin and controls the open drain
device at the POK pin. POK remains low until the voltage at the
FB pin is within 10% of the final regulation voltage. The POK
output is pulled low if: (1) the EN/SYNC pin transitions low for
more than 32 PWM cycles, (2) UVLO occurs, or (3) TSD occurs.
VEN/SYNC
5V
C1
2V
VOUT
VOUT
C2
1.13 V
VCOMP
C3
0.330 V
C4
C5
Pre-Biased Startup
5V
tSSDELAY
VSS
the output of the regulator is either shorted, or soft starting a
relatively high output capacitance.
VOUT increases
monotonically
COMP pin
released
VCOMP
VSS
0.330 V
Switching delayed until
VSS = VFB + 0.330 V
C4
IL
C5
t
Figure 6. Startup to VOUT = 5 V, 2.0 A, with CSS = 22 nF; shows VEN/SYNC
(ch1, 2 V/div.), VOUT (ch2, 2 V/div.), VCOMP (ch3, 500 mV/div.), VSS (ch4,
500 mV/div.), IL (ch5, 2 A /div.), t = 200 µs/div.
IL
t
Figure 7. Startup to VOUT = 5 V, with VOUT pre-biased to 2 V; shows
VEN/SYNC (ch1, 2 V/div.), VOUT (ch2, 2 V/div.), VCOMP (ch3, 500 mV/div.),
VSS (ch4, 500 mV/div.), IL (ch5, 2 A /div.), t = 200 µs/div.
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
If the A8584 is running and EN/SYNC transitions low, then after
32 PWM cycles, POK will transition low and remain low only as
long as the internal rail is able to enhance the open drain output
device. After the internal rail collapses, POK will return to the
high impedance state. The POK comparator incorporates hysteresis to prevent chattering due to voltage ripple at the FB pin.
Protection Features
Undervoltage Lockout (UVLO)
An Undervoltage Lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage
is below the lockout threshold (VINSTART). The UVLO comparator incorporates enough hysteresis (VUVLOHYS) to prevent on/off
3.8
Pulse-by-Pulse Current LImit
ILIM, D (%)
3.6
Maximum
3.4
3.2
cycling of the regulator due to IR drops in the VIN path during
heavy loading or during startup.
Thermal Shutdown (TSD)
The A8584 protects itself from over-heating, with an internal
thermal monitoring circuit. If the junction temperature exceeds
the upper thermal shutdown threshold (TTSD , nominally 165°C)
the voltages at the soft start and COMP pins will be pulled to
GND and both the upper and lower MOSFETs will be shut off.
The A8584 will stop PWM switching and stay in WAKE state
(see figure 3). It will automatically restart when the junction
temperature decreases more than the thermal shutdown hysteresis
(TTSDHYS , nominally 20°C).
Table 1. Pulse-by-Pulse Current Limit
versus Duty Cycle
D
(%)
ILIM
(A)
Min.
Typ.
Max.
5
2.80
3.25
3.70
20
2.68
3.14
3.60
40
2.51
2.99
3.46
60
2.35
2.84
3.32
2.2
80
2.18
2.69
3.18
2.0
90
2.10
2.61
3.11
Typical
3.0
2.8
2.6
Minimum
2.4
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
Duty Cycle, D (%)
Figure 8. Pulse-by-pulse current limit versus duty cycle
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
Disable Threshold (VHICDIS , nominally 750 mV), Hiccup mode
protection is disabled.
Pulse-by-Pulse Overcurrent Protection (OCP)
The A8584 monitors the current in the upper MOSFET and if the
current exceeds the pulse-by-pulse overcurrent threshold (ILIM)
then the upper MOSFET is turned off. Normal PWM operation
resumes on the next clock pulse from the oscillator. The A8584
includes leading edge blanking to prevent falsely triggering the
pulse-by-pulse current limit when the upper MOSFET is turned
on. Pulse-by-pulse current limiting is always active.
Hiccup Mode overcurrent protection monitors the number of
overcurrent events using an up/down counter: an overcurrent
pulse increases the count by one, and a PWM cycle without an
overcurrent pulse decreases the count by one. If the total count
reaches more than 7 (while Hiccup mode is enabled) then the
Hiccup latch is set and PWM switching is stopped. The Hiccup
signal causes the COMP pin to be pulled low with a relatively
low resistance (1500 Ω). Hiccup mode also enables a current sink
connected to the soft start pin (nominally 10 µA) so, when Hiccup first occurs, the voltage at the soft start pin ramps downward.
Hiccup mode operation is shown in figure 9.
The A8584 is conservatively rated to deliver 2.5 A for most
applications. However, the exact current it can support is heavily
dependent on duty cycle, ambient temperature, thermal resistance of the PCB, airflow, component selection, and nearby heat
sources. The A8584 is designed to deliver more current at lower
duty cycles and slightly less current at higher duty cycles. For
example, the pulse-by-pulse limit at 20% duty cycle is
2.68 A (min), 3.14 A (typ) but at 80% duty cycle the pulse limit
is 2.18 A (min), 2.69 A (typ). Use table 1 and figure 8 to determine the real current limit, given the duty cycle required for each
application. Take care to do a careful thermal solution or thermal
shutdown will occur.
When the voltage at the soft start pin decays to a low level
(VSSRESET , 235 mV typical), the Hiccup latch is cleared and the
10 µA soft start pin current sink is turned off. The soft start pin
will resume charging the soft start capacitor with 20 µA and the
voltage at the soft start pin will ramp upward. When the voltage at the soft start pin exceeds the COMP release threshold
(VSSRELEASE , 330 mV typical), the low resistance pull-down at
the COMP pin will be turned off and the Error amplifier will
force the voltage at the COMP pin to ramp up quickly, and PWM
switching will begin. If the short circuit at the converter output
remains, another Hiccup cycle will occur. Hiccups will repeat
until the short circuit is removed or the converter is disabled. If
the short circuit is removed, the A8584 will soft start normally
and the output voltage will be ramped to the required level as
shown in figure 9.
Output Short Circuit (Hiccup Mode) Protection
Hiccup mode protects the A8584 when the load is either too high
or when the output of the converter is shorted to ground. When
the voltage at the FB pin is below the Hiccup Enable Threshold (VHICEN , nominally 625 mV), Hiccup mode protection is
enabled. When the voltage at the FB pin is above the Hiccup
Short removed
C2
VSS
330 mV
VOUT
235 mV
C1
VCOMP
C3
C4
≈ 6.5 A
IL
t
Figure 9. Hiccup mode operation and recovery ; shows VSS (ch1, 200 mV/div.),
VOUT (ch2, 2 V/div.), VCOMP (ch3, 1 V/div.), IL (ch4, 5 A/div.), t = 500 µs/div.
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
APPLICATION INFORMATION
Design and Component Selection
RFSET = 26730 – 1.8
fSW
Setting the Output Voltage (VOUT, RFB1, RFB2)
The output voltage of the A8584 is determined by connecting
a resistor divider from the output node (VOUT) to the FB pin,
as shown in figure 10. There are trade-offs when choosing the
value of the feedback resisters. If the series combination (RFB1
+ RFB2) is relatively low, the light load efficiency of the regulator will be reduced. So, to maximize the efficiency, it is best to
choose high values for the resistors. On the other hand, if the parallel combination (RFB1 // RFB2) is too high, then the regulator
may be susceptible to noise coupling into the FB pin. In general,
the feedback resisters must satisfy the ratio shown in equation 1
to produce a required output voltage.
RFB1
VOUT
RFB2 = 0.8 V – 1
Table 2. Recommended Feedback Resistor Values
Table 2 shows the most common output voltages and recommended feedback resistor values, assuming less than 0.2% efficiency loss at light load of 100 mA and a parallel combination of
4 kΩ presented to the FB pin. For optimal system accuracy, it is
recommended that the feedback resistors have ≤1% tolerances.
PWM Switching Frequency (RFSET)
A8584
RFB1
FB
RFB2
VOUT
(V)
RFB1
VOUT to FB pin
(kΩ)
RFB2
FB pin to GND
(kΩ)
1.2
6.04
12.1
1.5
7.50
8.45
1.8
9.09
7.15
2.5
12.4
5.76
3.3
16.5
5.23
5.0
24.9
4.75
7.0
34.8
4.53
8.0
40.2
4.42
9.6
47.5
4.32
500
PWM Switching Frequency, fSW (kHz)
VOUT
(2)
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable PWM on-time,
tON(MIN) of the A8584. If the system required on-time is less than
the A8584 minimum controllable on-time, then switch node jitter
will occur, and the output voltage will have increased ripple or
oscillations. The PWM switching frequency should be calculated
using equation 3, where VOUT is the output voltage, tON(MIN) is
the minimum controllable on-time of the A8584 (worst case of
(1)
The PWM switching frequency is set by connecting a resistor
from the FSET pin to ground. Figure 11 is a graph showing the
relationship between the typical switching frequency (y axis)
and the FSET resistor, 1/RFSET (x axis). For a given switching
frequency (fSW), the FSET resistor can be calculated using equation 2, where fSW is in kHz and RFSET is in kΩ.
450
400
350
300
250
200
50
60
70
80
90
100
110
120
RFSET Resistance, RFSET (kΩ)
Figure 10. Connecting the feedback divider
Figure 11. PWM switching frequency versus RFSET
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
100 ns), and VIN(MAX) is the maximum required operational input
voltage to the A8584 (not the peak surge voltage).
fSW <
VOUT
tON(MIN) × VIN(MAX)
(3)
If the A8584 synchronization function is employed, the base
switching frequency should be chosen such that jitter will not
result at the maximum synchronized switching frequency according to equation 3, that is, 1.5 × fSW < fSW calculated by equation 2.
Output Inductor (LO)
The value of the output inductor (LO) is usually calculated to set
a particular peak-to-peak ripple current in the inductor. However,
the inductor physical size and cost will be directly proportional
to the peak current or saturation specification. There are tradeoffs
among: peak-to-peak ripple current, system efficiency, transient
response, and cost. If the peak-to-peak inductor ripple is chosen
to be relatively high, then the inductor value will be low, the system efficiency will be reduced, the transient response will be fast,
the inductor physical size will be small, and the cost reduced. If
the peak-to-peak inductor ripple is chosen to be relatively low,
then the inductor value will be high, the system efficiency will be
higher, the transient response will be slow, the inductor physical
size will be larger, and the cost will be increased.
Equation 4 can be used to estimate the inductor value, given a
particular peak-to-peak ripple current (ΔIL ), input voltage (VIN ),
output voltage (VOUT), and switching frequency (fSW). The reference designs in this datasheet use a peak-to-peak ripple current of
25% of the 2.0 A, DC rating of the A8584, or 0.5 APP .
V
LO ≥ f OUT
SW × ∆IL
V
1 – VOUT
IN
If the preceding equation yields an inductor value that is not a
standard value, the next higher available value should be used.
(4)
After choosing a standard inductor value, equation 5 should be
used to make sure the A8584 slope compensation is adequate.
In this equation VIN(MIN) is the minimum required input voltage,
VOUT is the output voltage, fSW is the switching frequency, and
Vf is the forward voltage of the asynchronous Schottky diode.
LO ≥ 1.3 ×
VOUT + Vf
fSW
1–
0.18 × (VIN(MIN)+ Vf )
VOUT + Vf
(5)
Ideally, the rated saturation current of the inductor should be
higher than the maximum current capability of the A8584 at the
expected duty cycle. Unfortunately, this usually results in a physically larger, more costly inductor. At a minimum, the saturation current of the inductor should support the DC rating of the
A8584 (2.5 A), plus ½ of the inductor peak-to-peak ripple current
(usually 0.5 APP ), the capacitive startup current (ICO ), and some
margin for component, frequency, and voltage tolerances. For
example, an inductor with a 3.0 A rating allows 2.5 A of load current, 0.4 APP of ripple current, 0.25 A of capacitive startup current
(ICO ), along with a 20% frequency decrease, a 20% inductance
decrease, and a 10% input voltage increase (at 5.0 VOUT , 12 VIN ,
425 kHz ).
After an inductor is chosen, it should be tested during output
short circuit conditions. The inductor current should be monitored
using a current probe. A good design should ensure the inductor
or the regulator are not damaged when the output is shorted to
GND at maximum input voltage and the highest expected ambient temperature
Output Capacitors (COUT)
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
The output voltage ripple (ΔVOUT ) is a function of the output
capacitor parameters: ESRCO , ESLCO , and CO , as follows:
ΔVOUT = ΔVESR + ΔVESL + ΔVCO (6)
It is commonly known that, for a constant load on the regulator, the current in the output inductor is equal to the DC output
current plus ΔIL . Therefore, using Kirchhoff’s current law, it can
be shown that the current in the output capacitors is equal to the
ripple current in the output inductor, or IC = ΔIL . Knowing this,
we can determine the first term in equation 6:
ΔVESR = ΔIL × ESRCO (7)
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
To calculate the second term in equation 6, ΔVESL , we must
determine the slope of the output inductor current, di/dt, which is
(VIN – VOUT) / LO:
∆VESL = LO
di
V –V
= ESLCO × IN OUT
dt
LO
(8)
To calculate the third term in equation 6, we must understand
that, over a single PWM cycle, the amount of charge into the
output capacitors must equal the amount of charge out of the
capacitors, or the capacitor output voltages would drift. What this
means is the output inductor current (ΔIL) flows in and out of the
output capacitor and is centered at 0 A, as shown in figure 12.
For any capacitor, the voltage is:
∆VCO ≥
1
COUT
i × dt
In this case, the integral term can be graphically calculated by
examining the 2 areas, A1 and A2, shown in figure 12:
∆I
DTS ∆IL DTS
A1 = 1 × L ×
=
2
2
2
8
∆I
(1 –D)TS
∆IL TS
∆IL DTS
A2 = 1 × L ×
=
–
2
2
2
8
8
i × dt = A1 + A2 =
∆IL TS
8
Substituting this into the equation for ΔVCO results in:
TS
ICO (A)
DTS
(1 – D)TS
∆IL / 2
0
A1
DTS /2
A2
[(1 – D)TS ]/2
–∆IL / 2
Time
Figure 12. Output capacitor current waveform
∆VCO =
∆IL TS
∆IL
=
8 COUT
8 fSW COUT
(9)
Combining equations 7, 8, and 9 results in an expression for the
total output voltage ripple:
∆VOUT = ∆IL× ESRCO +
∆IL
VIN – VOUT
× ESLCO +
8 fSW COUT
LO
The type of output capacitors will determine which terms of
equation 10 are dominant.
(10)
For ceramic output capacitors the ESR and ESL are extremely
low, so the output voltage ripple will be dominated by the third
term of equation 10:
∆IL
∆VOUT =
(10a)
8 fSW COUT
To reduce the voltage ripple of a design using ceramic output
capacitors, simply: increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors the value of capacitance will be
relatively high, so the third term in equation 10 will be minimized
and the output voltage ripple will be determined primarily by the
first two terms of equation 10:
V – VOUT
∆VOUT = ∆IL× ESRCO + IN
× ESLCO
(10b)
LO
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply: decrease the equivalent ESR and ESL by
using a high(er) quality capacitor, and/or add more capacitors in
parallel, or reduce the inductor current ripple (that is, increase
the inductor value). The ESR of some electrolytic capacitors
can be quite high, so Allegro recommends choosing a quality
capacitor that clearly documents the ESR or the total impedance
in the datasheet. Also, the ESR of electrolytic capacitors usually increases significantly at cold ambient, which increases the
output voltage ripple and, in many cases, reduces the stability of
the system.
To reduce the output voltage ripple and save PCB area, a design
could combine both ceramic and electrolytic capacitors in parallel. If this is done, the ceramic capacitors should be placed and
grounded as close as possible to the load to be most effective. AC
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
ripple voltage measurements should be made differentially across
the ceramic capacitors with a very short ground lead.
The transient response of the A8584 depends on the number and
type of output capacitors. In general, minimizing the ESR of the
output capacitance will result in a better transient response. The
ESR can be minimized by simply: adding more capacitors in
parallel, or by using higher quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount:
∆VOUT = ∆ILOAD × ESRCO + di ESLCO
(11)
dt
After the load transient occurs, the output voltage will deviate
for a short time depending on the system bandwidth, the output
inductor value, and output capacitance. After a short delay, the
Error amplifier will bring the output voltage back to its nominal
value. The speed at which the Error amplifier brings the output
voltage back to its set point will depend mainly on the closedloop bandwidth of the system. A higher bandwidth usually results
in a shorter time to return to the nominal voltage. However, a
higher bandwidth system may be more difficult to obtain acceptable gain and phase margins. Selection of the compensation
components (RZ, CZ, CP) are discussed in more detail in the
Compensation Components section of this datasheet.
Input Capacitors (CIN)
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input voltage with adequate design margin. Second,
their rms current rating must be higher than the expected rms
input current to the regulator. Third, they must have enough
capacitance and a low enough ESR to limit the input voltage
dV/dt to something much less than the hysteresis of the UVLO
circuitry (nominally 400 mV for the A8584) at maximum loading
and minimum input voltage.
The input capacitors must deliver the rms current according to
equation 12, where the duty cycle, D ≈ (VOUT + Vf ) / (VIN + Vf )
and Vf is the forward voltage of the asynchronous diode (D1 in
figure 1):
Irms = IO √D×(1– D)
(12)
Figure 13 shows the normalized input capacitor rms current
versus duty cycle. To use this graph, simply find the operational
duty cycle (D) on the x axis and determine the input/output
current multiplier on the y axis. For example, at a 20% duty
cycle, the input/output current multiplier is 0.400. Therefore,
if the regulator is delivering 2.0 A of steady-state load current,
the input capacitor(s) must support 0.400 × 2.0 A or 0.8 Arms . A
single capacitor may support the rms input current requirement or
several capacitors may have to be paralleled. Ceramic capacitors
can deliver quite a bit of current but their total capacitance will be
relatively low. For example, a 4.7 µF, 16 V, 1206, X7R ceramic
capacitor can easily deliver 3 to 4 Arms .
Electrolytic capacitors can typically deliver 100 to 500 mArms of
current so 2 or 3 of these may be required to support the ripple
current. Electrolytic capacitors will typically offer much more
capacitance than the same quantity of ceramic capacitors. So,
electrolytic capacitors are typically able to provide more current
over extended periods of time where VIN would otherwise droop.
However, ceramic capacitors have very low ESR and inductance,
so they are best for filtering the high frequency switching noise.
A good design will employ both types of capacitors with the
ceramic capacitors placed closest to the input pin of the A8584.
The input capacitors must limit the voltage deviations at the VIN
pin to something significantly less than the A8584 UVLO hysteresis during maximum load and minimum input voltage. Equation
13 allows us to calculate the minimum input capacitance:
IOUT × D × (1 – D )
CIN ≥
(13)
fSW(MIN) × (∆VIN(MIN) – IOUT × ESRCIN)
Where ΔVIN(MIN) is chosen to be much less than the hysteresis of the VIN UVLO comparator (ΔVIN(MIN) ≤ 100 mV is
Irms / IOUT (A)
A8584
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0
10
20
30
40
50
60
Duty Cycle, D (%)
70
80
90
100
Figure 13. Normalized input capacitor ripple current versus duty cycle
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19
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
recommended), fSW(MIN) is the lowest expected PWM frequency, and ESRCIN is the equivalent series resistance of the
input capacitor(s).
the load current according to equation 14, where D is the duty
cycle (VOUT + Vf ) / (VIN + Vf ) and IOUT(max) is the maximum
continuous ouput current of the regulator:
If we choose ceramic input capacitors (ESR < 5 mΩ), the IOUT ×
ESRCIN term can be neglected in equation 13. Also, the
D × (1 – D) term has an absolute maximum value of 0.25 at
50% duty cycle. So, for a conservative design, based on
IOUT = 2.0 A, fSW(MIN) = 340 kHz (425 kHz – 20%), D × (1 – D)
= 0.25, and ΔVIN =100 mV:
CIN ≥
2.0 (A) × 0.25
= 14.7 µF
340 (kHz) × 100 (mV)
A good design should consider the DC-bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction) so these types should be avoided. The X5R and
X7R type capacitors should be the primary choices due to their
stability versus both DC bias and temperature.
For all ceramic capacitors, the DC-bias effect is even more
pronounced on smaller case sizes, so a good design will use the
largest affordable case size (such as 1206 or 1210). Also, it is
advisable to select input capacitors with plenty of design margin
in the voltage rating, to accommodate the worst-case transient
input voltage (for example, load dump as high as 40 V for automotive applications).
Asynchronous Diode (D1)
There are three requirements for the asynchronous diode. First,
the asynchronous diode must be able to withstand the regulator
input voltage when the high-side MOSFET is on. Therefore, the
design should have a diode with a reverse voltage rating ( Vr )
higher than the maximum expected input voltage (that is, the
surge voltage). Second, the forward voltage of the diode (Vf )
should be minimized or the regulator efficiency will suffer. Also,
if Vf is too high, the missing diode protection in the A8584 could
be falsely activated. A Schottky-type diode, which can maintain
a very low Vf when the converter output is shorted to ground at
the coldest ambient temperature, is highly recommended. Third,
the asynchronous diode must conduct the output current when
the high-side MOSFET is off. Therefore, the average forward
current rating of this diode (If(av) ) must be high enough to deliver
If(av) ≥ IOUT(max) (1 – D(min)) (14)
To save cost and PCB area, the designer might be tempted to use
a diode with a relatively low current rating and the smallest PCB
footprint. However, doing this usually results in a hotter diode
and lower system efficiency. For the asynchronous converter,
most losses can occur in this diode. To optimize efficiency, one
should use a higher rated, physically larger diode. Also, diodes
with very high reverse voltage ratings usually have higher
forward voltages, which reduces system efficiency. Therefore, a
diode with the lowest possible reverse voltage rating should be
used. However, care should be taken to be sure this diode is not
destroyed during input voltage transients or surge events.
Bootstrap Capacitor (CBOOT)
A bootstrap capacitor must be connected between the BOOT and
SW pins to provide floating gate drive to the high-side MOSFET.
For most applications 100 nF is sufficient. This should be a highquality ceramic capacitor, such as an X5R or X7R, with a voltage
rating of at least 16 V. The A8584 incorporates a low-side MOSFET to ensure that the bootstrap capacitor is always charged,
even when the converter is lightly loaded.
Soft Start and Hiccup Mode Timing (CSS)
The soft start time of the A8584 is determined by the value of
the capacitance on the SS pin. When the A8584 is enabled, the
voltage at the SS pin will start from 0 V and will be charged by
the soft start current, ISSSU (nominally 20 μA). However, PWM
switching will not begin instantly because the voltage at the
SS pin must rise above the COMP release voltage, VSSRELEASE
(nominally 0.33 V). The soft start delay (tSSDELAY) can be calculated using equation 15:
0.33 (V)
tSSDELAY = CSS ×
ISSSU
(15)
If the A8584 is starting into a full load (nominally 2.0 A) and
the soft start time (tSS) is too fast, the pulse-by-pulse overcurrent threshold may be exceeded and Hiccup mode protection
triggered. This occurs because the total of the full load current,
the inductor ripple current, and the additional current required to
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Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
charge the output capacitors (ICO = CO × dVOUT /dtSS) is higher
than the pulse-by-pulse current threshold, as shown in figure 14.
This phenomenon is more pronounced when using high value
electrolytic type output capacitors.
To avoid prematurely triggering hiccup mode the soft start
capacitor, CSS, should be calculated using the following formula:
20 (µA) × VOUT × COUT
CSS ≥
(16)
0.8 (V) × ICO
Where VOUT is the output voltage, COUT is the output capacitance, ICO is the amount of current allowed to charge the output
capacitance during soft start (Allegro recommends 0.125 A < ICO
< 0.375 A). Higher values of ICO result in faster soft start times.
However, lower values of ICO ensure that Hiccup mode is not
falsely triggered as components vary.
Components can easily change due to initial tolerances, aging, or
temperature (output capacitance, soft start capacitance, soft start
charging currents, and so forth). Allegro recommends starting the
design with an ICO of 0.125 A and increasing it only if the soft
start time is too slow. If a non-standard capacitor value for CSS is
calculated, the next larger value should be used.
The output voltage ramp time, tSS , can be calculated by using
either of the following formulas:
tSS = VOUT ×
or
COUT
ICO
tSS = 0.8 (V) ×
(17a)
CSS
20 (µA)
IOUT (A)
(17b)
}
ILIM
ILOAD
tSS
Time
Figure 14. Output capacitor current (ICO) during startup
ICO
When the A8584 is in Hiccup mode, the CSS capacitor is used as
a timing capacitor and sets the hiccup period. The SS pin charges
the CSS capacitor with ISSSU (nominally 20 μA) during a startup
attempt and discharges the CSS capacitor with ISSHIC (nominally
10 μA) between startup attempts. Because the ratio of the SS pin
currents is 2:1, the time between hiccups will be at least twice
as long as the startup time. Therefore, the effective duty-cycle of
the A8584 will be very low when the output is shorted to ground.
With such a low duty cycle, the junction temperature of the
A8584 will be maintained at an extremely low value, compared
to other short circuit protection techniques.
Compensation Components (RZ, CZ, CP)
To compensate the system, it is important to understand where
the buck power stage, load resistance, and output capacitance
form their poles and zeros in frequency. Also, it is important to
understand that the compensated Error amplifier introduces a
zero and two more poles, and where these should be placed to
maximize system stability, provide a high bandwidth, and optimize the transient response.
First, look at the power stage of the A8584, the output capacitors, and the load resistance. This circuitry is commonly referred
as the “control to output” transfer function. The low frequency
gain of this section depends on the COMP to SW current gain
(gmPOWER), and the value of the load resistor (RLOAD). The DC
gain of the control-to-output is:
GCO = gmPOWER × RLOAD (18)
The control-to-output transfer function has a pole (fP1) formed by
the output capacitance (COUT) and load resistance (RLOAD) at:
1
fP1 =
(19)
2� × RLOAD × COUT
The control-to-output transfer function also has a zero (fZ1)
formed by the output capacitance (COUT) and its associated ESR:
1
fZ1 =
(20)
2� × ESR × COUT
For a design with very low-ESR type output capacitors (for example, ceramic or OSCON output capacitors), the ESR zero (fZ1 )
is usually at a high frequency, so it can be ignored. On the other
hand, if the ESR zero falls below or near the 0 dB crossover frequency of the system (such as with electrolytic output capacitors),
then it should be cancelled by the pole formed by the CP capacitor
and the RZ resistor (discussed and identified later as fP3).
Allegro MicroSystems
955 Perimeter Road
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21
Wide Input Voltage, 500 kHz , 2.5 A,
Asynchronous Buck Regulator
A8584
A Bode plot of the control-to-output transfer function for the
application circuit on page 29 (VOUT = 3.3 V, RLOAD = 1.3 Ω) is
shown in figure 15. The pole at fP1 can be seen at 2 kHz, while
the ESR zero, fZ1 , occurs at a very high frequency, 530 kHz (this
is typical for a design using ceramic output capacitors).
Next, look at the feedback resistor divider, (RFB1 and RFB2), the
Error amplifier (gm), and its compensation network RZ/CZ/CP. It
greatly simplifies the transfer function derivation if RO >> RZ,
and CZ >> CP. In most cases, RO > 2 MΩ, 1 kΩ < RZ < 50 kΩ,
220 pF < CZ < 47 nF, and CP
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