A8603
Multiple-Output Regulator for Automotive LCD Displays
FEATURES AND BENEFITS
DESCRIPTION
The A8603 is a fixed-frequency, multiple-output supply for
LCD bias. Its switching frequency can be either programmed
or synchronized with an external clock signal between 350 kHz
and 2.25 MHz. This will minimize interference with AM and
FM radio bands.
•
•
•
•
•
•
•
•
•
Automotive-grade AEC-Q100 qualified
Input voltage from 3 to 10 V
Four individual output supplies
Independent control of each output voltage
Boost switching frequency: 350 kHz to 2.25 MHz
External synchronization capability is available
Frequency dithering to reduce EMI
Less than 10 μA shutdown current
Protection features: overcurrent, overvoltage, short
circuit, and thermal overload protection
• Fully programmable outputs through I2C
□ Regulator voltage
□ Startup/shutdown sequences
□ Fault retry counter
An I 2 C-compliant serial interface allows a system
microcontroller to configure the A8603 by writing into its
internal registers. A system controller can also access the A8603
status registers in case of fault conditions.
The A8603 incorporates a boost stage followed by two linear
regulators and two charge-pump regulators. Each output voltage
can be programmed independently through serial interface.
During power-up and shutdown, the outputs are turned on and
off in preprogrammed sequences with adjustable delay. This
will meet the sequencing requirements for specific LCD panels.
PACKAGES:
Short-circuit protection is provided for all outputs. The boost
switch is protected against overcurrent and overvoltage.
24-Pin 4 mm × 4 mm QFN
with Sidewall Plating
The A8603 is provided in a 24-pin 4 mm × 4 mm QFN
package, with exposed thermal pad to allow operation at high
ambient temperatures. It is lead (Pb) free with 100% matte-tin
leadframe plating.
24-Pin 4 mm × 4 mm QFN
with Wettable Flank
APPLICATIONS
Not to scale
D1
L1
VSUPPLY
3 to 10 V
COUT
SW
VIN
Enable
FSET/SYNC
IC
2
SDA
SCL
ADDR
VIN
VOUT
AVDD
EN
External Sync
Micro
Controller
• GPS
• Infotainment
• Medium LCDs
VGH
A8603
VGL
VCOM
VAVDD 8 to 14 V
VVGH 14 to 29 V
VVGL -4 to -12 V
LCD PANEL
VVCOM 3 to 7.5 V
FAULT
System Block Diagram Showing Typical Regulator Voltages
A8603-DS, Rev. 12
MCO-0000138
January 28, 2021
Multiple-Output Regulator for
Automotive LCD Displays
A8603
Table 1: Selection Guide
Part Number
Package
Packing*
Pin Soldering
A8603KESTR-R
24-pin 4×4 QFN with exposed thermal pad
1500 pieces per 13-in. reel
Sidewall Plating
A8603KESTR-J
24-pin 4×4 QFN with exposed thermal pad
Contact Factory
Wettable Flank
VGL/VGH Charge Pumps
Boost Controller
Boost Switching Frequency
Boost Frequency Dithering
18
20
22
23
*Contact Allegro™ for additional packing options.
Table of Contents
Specifications 3
Absolute Maximum Ratings
Thermal Characteristics
Pinout Diagrams and Terminal List Table
Functional Block Diagram
Electrical Characteristics
3
3
4
5
6
Characteristic Performance
Functional Description
10
12
Diagnostic Registers
15
Description of Regulators
17
Program Diagnostics
Programmable Registers
I2C Register Map
Real-Time Status Registers
Latched Status Registers
AVDD Regulator
VCOM Regulator
12
13
14
15
16
17
17
Fault Conditions
24
Thermal Analysis
33
Package Outline Drawing
35
Over- and Undervoltage Protections
Overcurrent Protection
Examples of Various Fault Conditions
Pre-Output Fault Detection
General Fault Detection
Fault Monitoring
Fault1 (Group1)
Fault2 (Group2)
Fault3 (Group3)
Boost Stage Power Loss
Output Regulator Power Loss
24
24
25
29
29
31
31
31
31
33
33
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
Multiple-Output Regulator for
Automotive LCD Displays
A8603
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS [1][2][5]
Characteristic
Symbol
Rating
Unit
All voltages measured with respect to GND
–0.3 to 11
V
Continuous
–0.6 to 22
V
–1 to 40
V
VOUT
–0.3 to 22
V
VAVDD
–0.3 to lower of 16 or
VOUT + 0.3
V
VIN Pin Voltage
VIN
SW Pin Voltage [3][4]
VSW
OUT Pin Voltage
AVDD Pin Voltage
Notes
Voltage spikes (pulse width < 100 ns)
CP11 Pin Voltage
VCP11
Positive charge pump
–0.3 to 31
V
CP12 Pin Voltage
VCP12
Positive charge pump
–0.3 to VCP11 + 0.3
V
VVGH, VVGH3
Positive charge pump
–0.3 to 31
V
VCP21
Negative charge pump
–0.3 to 14
V
VCP22, VVGL
Negative charge pump
VGH and VGH3 Pin Voltage
CP21 Pin Voltage
CP22 and VGL Pin Voltage
FAULT Pin Voltage
BIAS, COMP, FSET Pin Voltage
VCOM Pin Voltage
AGND, PGND and GNDVCOM Pin
Voltage
–14 to 0.3
V
VFAULT
–0.3 to lower of 10 or
VVIN + 0.3
V
VBIAS, VCOMP,
VFSET
–0.3 to 3.3
V
VVCOM
–0.3 to lower of 8.5 or
VAVDD + 0.3
V
VAGND, VPGND,
VGNDVCOM
–0.3 to 0.3
V
Logic Pins (EN, SCL, SDA, ADDR, NC)
–
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
–0.3 to 5.5
V
–40 to 125
°C
TJ(max)
150
°C
Tstg
–55 to 150
°C
K temperature range
[1] Stresses
beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions
for extended periods may affect device reliability.
[2] All voltages referenced to AGND.
[3] The SW pin has internal clamp diodes to GND. Applications that forward bias this diode should take care not to exceed the IC package power dissipation limits. Note:
Exact energy specification to be determined.
[4] The switch DMOS is self-protected. If voltage spikes exceeding 40 V are applied, the device would conduct and absorb the energy safely.
[5] When V = 0 (no power), all inputs are limited by –0.3 to 5.5 V.
IN
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Package Thermal Resistance
[6] Additional
Symbol
RqJA
Test Conditions [6]
Value
Unit
37
°C/W
Package ES on 4-layer PCB based on JEDEC standard
thermal information available on the Allegro website.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
Multiple-Output Regulator for
Automotive LCD Displays
A8603
19 VGH3
20 CP11
21 CP12
22 VOUT
23 PGND
24 SW
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
VIN
1
18 VGH
FAULT
2
17 CP21
EN
3
16 CP22
PAD
15 VGL
COMP 12
BIAS 11
9
FSET 10
13 AVDD
ADDR
6
8
NC
SDA
14 AGND
7
4
5
SCL
VCOM
GNDVCOM
Package ES, 24-Pin QFN Pinouts
Terminal List Table
Number
Name
Function
1
VIN
2
FAULT
3
EN
4
VCOM
5
GNDVCOM
6
NC
No Connect (reserved for Test Mode); connect to GND in actual PCB
7
SCL
I2C clock signal
8
SDA
I2C data signal
9
ADDR
I2C address selection (up to 4 physical IC addresses based on voltage level)
10
FSET
Input for synchronizing boost and charge pump signals switching frequency to external clock signal; alternatively, it can be
connected to an external resistor to set the switching frequency
11
BIAS
Output from internal 2.8 V bias regulator; connect to GND via 1 μF ceramic capacitor for decoupling
12
COMP
Compensation pin, connect to external COMP components (RZ and CZ)
13
AVDD
Output from internal LDO (item 1 in Functional Block Diagram) powered by VOUT
14
AGND
Analog GND reference for signals; connect to ground plane
Input supply voltage (3 to 10 V) for the IC
Open-drain output, pulls low in case of error condition
Enable pin for enabling the IC; system can only be enabled after VIN is above UVLO level (refer to Startup Timing Diagram)
Output from internal low-dropout (LDO) regulator (item 2 in Functional Block Diagram) powered by AVDD
Ground reference for VCOM; connect to ground plane
15
VGL
16
CP22
Inverted charge pump output (item 3 in Functional Block Diagram)
17
CP21
18
VGH
2× charge pump output (item 4 in Functional Block Diagram)
19
VGH3
3× charge pump output (item 4 in Functional Block Diagram)
20
CP11
21
CP12
22
VOUT
Connect to boost output for internal LDO and charge pump regulators
23
PGND
Power ground for internal boost switch; connect this pin to ground terminal of output ceramic capacitor(s)
24
SW
–
PAD
Capacitor terminals for inverted charge pump (item 3 in Functional Block Diagram)
Capacitor terminals for charge pump (item 4 in Functional Block Diagram)
Internal boost converter switch node
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
Multiple-Output Regulator for
Automotive LCD Displays
A8603
D1
L1
VIN
(3 to 10 V)
SW
VOUT
VOUT
PGND
(Output voltages shown
for typical LCD panel.)
AVDD
VIN
Enable
BIAS
Boost
Control
BIAS
Regulator
ON
ON
Ref1
2.8 V
FSET/SYNC
Ext. Sync.
RFSET
RZ
CZ
Osc with
Dithering
ON
AVDD_ON
VCOM_ON
EN
SDA
SCL
BIAS
ADDR
Enable
Enable
I2C
Interface
R1
R2
VGH_ON
ON
+
VCOM
3 to 7.5 V
GNDVCOM
CP11
CP12
VGH (2×)
18 V
VGH
+
VGH3
CP11
CP12
VGL > 90%
VGL/VGH
Interlock
VGH < 30%
D2A
Converters
VGL_OFF
Regulation
Targets
Ref 1–4
VCOM
Ref4
Register
Bank
VIN
2×/3×
Charge
Pump
OFF
4
VGH_OFF
Control Bus
Ext. Enable
LDO
2
Ref2
COMP
AGND
AVDD
10 V
LDO
1
VGL_ON
VGH
VGH (3×)
27 V
VGH
VGH3
VGL
Inverter
Charge
Pump
OFF 3
Optional 3× Configuration
CP21
CP22
VGL
VGL
–8 V
ON
Ref3
+
CP21
FAULT
Fault
OVP
UVP
OCP
TSD
...
CP22
VGL
–12 V
VGL
Using 2 External
Diodes
+
Functional Block Diagram
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
Multiple-Output Regulator for
Automotive LCD Displays
A8603
ELECTRICAL CHARACTERISTICS [1]: Valid at VIN = 5 V, EN = high, fSW = 2 MHz, VAVDD = 10 V, VVGH1 = 20 V, VVGL = –8 V, TJ = TA = 25°C,
except • indicates specifications guaranteed for TJ = TA = −40°C to 125°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
•
3
–
10
V
•
–
2.8
2.9
V
–
0.15
0.25
V
–
2.8
–
V
–
1
10
µA
INPUT VOLTAGE AND CURRENT
Input Voltage
VIN Pin Undervoltage Lockout
(UVLO) Threshold
VIN Pin UVLO Hysteresis
BIAS Voltage
VIN
VUVLO
VIN rising
VUVLO(HYS)
VBIAS
Internal BIAS regulator, EN = high
Shutdown BIAS Current [1]
IVINBIAS(SD)
Current into VIN pin, EN = low
•
Standby BIAS Current
IVINBIAS(STB)
EN = high, output disabled
–
3
–
mA
Operating BIAS Current
IVINBIAS(OP)
EN = high, output enabled
–
6
–
mA
Switch Peak Current Limit
ISWILIM
Cycle-by-cycle current limit
2.2
2.6
3
A
Switch Secondary Current Limit
ISWILIM2
Trips SW_OCP fault if exceeded
–
3.7
–
A
Switch On-Resistance
RDS(on)
ISW = 0.4 A
Switch Minimum On-Time
tON(MIN)
Switch Minimum Off-Time
tOFF(MIN)
SW Pin Leakage Current
ISW(LKG)
VOUT Pin Leakage Current
IOUT(LKG)
SW Pin Overvoltage Protection
Threshold
VSW(OVP)
Measured from SW to GND
SW OVP Detection Time [2]
tSW(OVP)
BOOST SWITCH
SW OVP to Shutdown Delay [2]
tFAULT(OVP)
•
–
0.4
0.7
Ω
•
–
65
120
ns
•
–
60
100
ns
VSW = 5 V, EN = low
–
0.1
–
µA
VOUT = 5 V, EN = low
–
0.1
–
µA
VOUT = 10 V, EN = low
–
25
37
µA
18.6
21
23
V
Minimum pulse width required for VSW ≥
VSW(OVP) to be detected as SW OVP
–
40
–
ns
Delay from SW OVP to FAULT = L
–
1
2.5
µs
–
0.64
–
V
•
SWITCHING FREQUENCY / SYNCHRONIZATION
FSET_SYNC Pin Voltage
VFSETSYNC
FSET_SYNC Pin Current
IFSETSYNC
Switching Frequency
Synchronization Frequency
fSW
fSYNC
Without using external synchronization signal
22
–
140
µA
RFSET_SYNC = 5.1 kΩ
•
1.8
2
2.2
MHz
External logic sugnal connected to FSET_
SYNC pin
•
0.35
–
2.25
MHz
Synchronization Minimum On-Time
tSYNC(ON)
•
150
–
–
ns
Synchronization Minimum Off-Time
tSYNC(OFF)
•
150
–
–
ns
No external synch, REG0x10 = ‘00b’
–
0
–
%
No external synch, REG0x10 = ‘01b’
–
5
–
%
No external synch, REG0x10 = ‘10b’
–
10
–
%
No external synch, REG0x10 = ‘11b’
–
15
–
%
Switching Frequency Dithering
Range
ΔfSW0
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
Multiple-Output Regulator for
Automotive LCD Displays
A8603
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at VIN = 5 V, EN = high, fSW = 2 MHz, VAVDD = 10 V, VVGH1 = 20 V, VVGL = –8 V,
TJ = TA = 25°C, except • indicates specifications guaranteed for TJ = TA = −40°C to 125°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
ERROR AMPLIFIER
Open-Loop Voltage Gain [2]
Transconductance [2]
AVOL
gm
–
43
–
dB
ICOMP = between –100 µA and 100 µA
–
550
–
µA/V
EA Source Current
IEA_SRC
VCOMP = 0.7 V, VOUT below regulation target
–
200
–
µA
EA Sink Current
IEA_SINK
VCOMP = 0.7 V, VOUT over regulation target
–
200
–
µA
RCOMP1
Active pull-down when EN = H, Boost disabled
–
2.5
–
kΩ
RCOMP2
Passive pull-down when EN = L
–
450
–
kΩ
COMP Pull-Down Resistor
LOGIC INPUTS
EN Pin Logic High
VIH_EN
•
1.8
–
–
V
EN Pin Logic Low
VIL_EN
•
–
–
0.8
V
Internal Pull-Down Resistance to
AGND
REN(PD)
–
100
–
kΩ
Hard-Reset Duration [2]
tRESET
EN = L duration in order to initiate a hardware
reset during normal operation
2
–
–
µs
FSET Pin Input Logic High
VIH_FSE
When used in external sync mode
•
1.5
–
–
V
FSET Pin Input Logic Low
VIL_FSE
When used in external sync mode
•
–
–
0.4
V
OVER- AND UNDERVOLTAGE PROTECTION FOR OUTPUT REGULATORS
Output Overvoltage Fault Threshold
VOUTx(OV)
Output rising; measured as % of target voltage
–
120
–
%
Output Undervoltage Fault Threshold
VOUTx(UV)
Output falling; measured as % of target voltage
–
80
–
%
•
5
–
15
V
OUTPUT REGULATORS
AVDD Output Voltage
VAVDD
VCOM Output Voltage
VVCOM
VAVDD > VVCOM + 1.5 V
•
2.5
–
7.5
V
VGH Output Voltage
VVGH
VGH & VGH3 shorted
•
10
–
30
V
VGL Output Voltage
VVGL
•
–12
–
–4
V
VAVDD(DO)
Defined as VOUT – VAVDD; when AVDD = 15 V,
IOUT = 100 mA
–
2.1
–
V
Boost Minimum Headroom for
VGH Regulator
VVGH(DO)
Defined as VOUT – VVGH / 2; when VVGH = 24 V,
IOUT = 8 mA
–
2.9
–
V
Boost Minimum Headroom for
VGL Regulator
VVGL(DO)
Defined as VOUT – (–VVGL); when VVGL = –12 V,
IOUT = –8 mA
–
3.5
–
V
Ouptut Pull-Down Resistor During
Shutdown (AVDD, VCOM)
ROUTPD1
EN = high, output disabled
–
250
–
Ω
Ouptut Pull-Down Resistor During
Shutdown (VGH, VGL)
ROUTPD2
EN = high, output disabled
–
500
–
Ω
Ouptut Pull-Down Resistor in Sleep
Mode (AVDD, VCOM, VGH)
ROUTPD3
EN = low, VIN > VUVLO
–
1
–
kΩ
Ouptut Pull-Down Resistor in Sleep
Mode (VGL only)
ROUTPD4
EN = low
–
10
–
kΩ
Boost Minimum Headroom for
AVDD Regulator
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
Multiple-Output Regulator for
Automotive LCD Displays
A8603
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at VIN = 5 V, EN = high, fSW = 2 MHz, VAVDD = 10 V, VVGH1 = 20 V, VVGL = –8 V,
TJ = TA = 25°C, except • indicates specifications guaranteed for TJ = TA = −40°C to 125°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
200
275
350
mA
36
45
54
mA
11
20
26
mA
11
20
26
mA
OUTPUT CURRENT CAPACITY
AVDD OCP Trip Level
IAVDD(OCP)
VCOM OCP Trip Level
IVCOM(OCP)
Includes IVCOM
VGH OCP Trip Level
IVGH(OCP)
VGL OCP Trip Level
IVGL(OCP)
Current into VGL pin
AVDD, VGH, and VGL Load
Regulation
VAVDDreg
VVGHreg
VVGLreg
VAVDD =10 V, IAVDD = 10 to 100 mA
VVGH = 20 V, IVGH = 0.4 to 4 mA
VVGL = –8 V, IVGL = –0.8 to –8 mA
•
–0.1
–
0.1
V
AVDD Accuracy
ErrAVDD
Reg00 = 0x40 (VAVDD = 10.04 V), IAVDD = 50 mA
•
–2.1
–
2.1
%
ErrVCOM
Reg01,02 = 0x100 (VVCOM = 5.005 V),
IVCOM = 10 mA
•
–2.1
–
2.1
%
OUTPUT VOLTAGE ACCURACY
VCOM Accuracy
VGH Accuracy
errVGH
Reg04 = 0x40 (VVGH = 20.65 V), IVGH = 2 mA
•
–2.5
–
2.5
%
VGL Accuracy
errVGL
Reg03 = 0x20 (VVGL = –8.39 V), IVGL = –4 mA
•
–2.5
–
2.5
%
VCOM Step Size
10
mV
VCOM Load Regulation [2]
VVCOMreg
ILOAD = 2 to 20 mA, VVCOM = 5.0 V
•
–5
–
5
mV
VCOM Temperature Coefficient [2]
TCVCOM
VVCOM = 5 V, –30°C < TA < 85°C,
ILOAD = 10 mA
•
–100
–
150
μV/°C
Minimum Dropout for VCOM from
AVDD
VVCOM(DO)
VAVDD = 7 V, IVCOM = 20 mA
–
–
1.5
V
FAULT Pull-Down Voltage
VFAULT(PD)
Fault condition asserted, pull-up current = 1 mA
–
–
0.4
V
FAULT Pin Leakage Current
VFAULT(LKG)
Fault condition cleared, pull-up to 5 V
–
–
1
µA
tSU_TO_min
Minimum timeout when Reg0x9 = 0x03 or lower
–
9.6
–
ms
tSU_TO_max
Maximum timeout when Reg0x9 = 0x1F
–
99.2
–
ms
tSU_DLY_min
Minimum delay when Reg_X = 0x00, X = 5..8 [3]
–
0
–
ms
tSU_DLY_max
Maximum delay when Reg_X = 0xFF, X = 5..8 [3]
–
25.5
–
ms
All outputs discharged to below 10% target
(30% for VGL and VGH)
40
50
65
ms
tSD_DLY_min
Minimum delay when Reg_X = 0x00,
X = C,D,E,F [3]
–
0
tSD_DLY_max
Maximum delay when Reg_X = 0xFF,
X = C,D,E,F [3]
–
25.5
–
ms
Maximum time for any output to stay in OCP
fault condition before shutdown.
40
50
60
ms
Maximum number of fault retries.
Programmable through Reg0x0A
0
–
15
tRESTART_min
Cooldown time between fault shutdown and
next retry. Reg0x0B = 0x03 or lower
–
9.6
–
ms
tRESTART_max
Cooldown time between fault shutdown and
next retry. Reg0x0B = 0x3F
–
201.6
–
ms
FAULT PIN
PROGRAMMABLE DELAYS AND TIMERS
Startup Timeout/Watchdog Timer
(Time limit for all outputs to reach
90% target, starting from internal
EN=H)
Startup Delay Timer#1-4
(One each for AVDD/VCOM/VGL/
VGH)
Shutdown Timeout
(starting from internal EN = L)
Shutdown Delay Timer#5-8
(One each for AVDD/VCOM/VGL/
VGH)
Overcurrent Protection (OCP)
Timeout
Fault Retry Counter
Fault Cool-Down Timer
tSD_TO
tOCP_TO
NRESTART
ms
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
Multiple-Output Regulator for
Automotive LCD Displays
A8603
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at VIN = 5 V, EN = high, fSW = 2 MHz, VAVDD = 10 V, VVGH1 = 20 V, VVGL = –8 V,
TJ = TA = 25°C, except • indicates specifications guaranteed for TJ = TA = −40°C to 125°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
155
165
–
°C
–
20
–
°C
THERMAL SHUTDOWN (TSD) PROTECTION
TSD Threshold [2]
TTSD
TSD Hysteresis [2]
TTSD(HYS)
Temperature rising
I2C INTERFACE
Logic Input Low (SDA, SCL)
VSCL(L)
–
–
0.8
V
Logic Input High (SDA, SCL)
VSCL(H)
2.3
–
–
V
VI2CIHYS
–
150
–
mV
II2CI
–1
–
1
µA
SDA = Low, pull-up current = 2.5 mA
–
–
0.4
V
EN = Low, pull-up to 5.5 V
–
–
1
µA
–
–
400
KHz
Logic Input
Hysteresis [2]
Logic Input Current
SDA Output Voltage Low
VI2COut(L)
SDA Output Leakage
II2CLKG
SCL Clock Frequency
fCLK
ADDR PIN COMPARATOR THRESHOLD
Voltage Level for Address 101,0000
VADDLEVEL1
0
–
0.3
V
Voltage Level for Address 101,0001
VADDLEVEL2
ADDR connected to GND
0.6
–
0.9
V
Voltage Level for Address 101,0010
VADDLEVEL3
1.5
–
1.8
V
Voltage Level for Address 101,0011
VADDLEVEL4
2.4
–
3
V
ADDR connected to BIAS pin
[1] For
input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin
(sinking).
[2] Ensured by design and characterization, not production tested.
[3] Refer to Table 5 for Register Map.
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Multiple-Output Regulator for
Automotive LCD Displays
A8603
CHARACTERISTIC PERFORMANCE
Startup Timing Diagram
VIN
(power supply)
EN
(external enable)
BIAS
(IC internal supply)
2 µs to initiate a “Hardware Shutdown.” The IC responds by pulling Internal Enable to Low.
B: The A8603 shuts down all output regulators in sequence, according to their shutdown delay times. All registers will be restored to power-up
defaults at the end of a Hardware Shutdown. This does not apply to a Software Shutdown when user programs INT_EN = L.
C: After the last regulator has shut down, the A8603 resets all internal registers to their power-on defaults, sets the HARD_RESET status bit to
1, and pulls FAULT pin to Low. The A8603 is now ready to accept new I2C commands.
D: The A8603 is powered down only if EN = L after shutdown has completed.
Notes on Shutdown Timing Diagram
•
•
•
•
•
•
Each regulator has a programmable Shutdown Delay timer. Each timer has a resolution of 0.1 ms and a maximum duration of 25.5 ms.
AVDD can only be turned off after VCOM is turned off (t5 = 0 is allowed)
VGL can only be turned off after VGH drops below 30%, even through t7 = 0 is allowed.
There is no dependency between {t5, t6} and {t7, t8}
Once a shutdown is in progress, both external Enable and Internal EN are ignored until shutdown is completed.
All output discharge times are based on external capacitance and internal pull-down resistance (250 Ω for AVDD and VCOM, 500 Ω for VGH and
VGL). The external DC load is assumed to be negligible.
• If any of the regulator output does not decay to below 10% (30% for VGL and VGH) of target voltage after 50 ms time-out period, starting from
beginning of shutdown, it is ignored and then the IC is allowed to power down.
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Multiple-Output Regulator for
Automotive LCD Displays
A8603
FUNCTIONAL DESCRIPTION
The A8603 is a flexible multivoltage regulator designed for LCD
panel bias applications. It utilizes a high-efficiency boost converter, together with space-saving low-dropout (LDO) regulator
and charge pump circuits to provide four independently adjustable voltage outputs:
device. Two bus lines, SCL and SDA, provide access to the internal control registers. The clock input on the SCL pin is generated
by the master, while the SDA line functions as either an input or
an open-drain output for the A8603, depending on the direction
of the data flow.
• AVDD: Typically between 5 and 15 V. Nominal output current
100 mA. This output is from a LDO powered by VOUT.
In case there are two or more slave devices in an I2C network,
each device must present a unique physical address for the master
to select. To avoid conflict, the A8603 uses a 4-level ADDR pin
to set its physical address. Depending on the voltage level at
ADDR, the physical address is set as ‘101,00xx’, where
xx = {00 | 01 | 10 | 11}. This is illustrated by the figure below.
• VCOM: Typically between 3 and 7.5 V at 20 mA. The power
supply of this regulator is internally connected to AVDD.
Therefore AVDD must be at least 1.5 V higher than the upper
limit of VCOM.
• VGL: Typically between –12 and –4 V at 4 mA. This voltage
is generated by an inverted charge pump, which is powered by
VOUT.
• VGH: Typically between 10 and 24 V at 4 mA. This voltage is
generated by a 2× charge pump, which is powered by VOUT.
If necessary, an external 3× charge pump can generate a higher
VGH between 20 and 30 V at 4 mA.
SDA
SCL
BIAS
(2.8 V)
ADDR
R1
Program Diagnostics
A8603 features the I2C (Inter-Integrated Circuit, alternatively
spelled as I2C) serial interface and programmable memory array.
The I2C serial interface allows external microcontroller or some
type of master device to communicate with A8603 as its slave
I2C
Interface
R2
Figure 2: Select I2C Address by Using Resistor Divider
at ADDR Pin
Table 1: I2C Address Selection Using Resistor Divider
A8603
SCL
Micro
Controller
SDA
Driver
Driver
Driver
clock
data_in
data_out
I 2C
Interface
Read/Write
Register Array
R1 (k)
R2 (k)
VADDR (V)
I2C Address
open
0
0
101,0000
27.4
10
0.75
101,0001
6.98
10
1.65
101,0010
0
open
2.8
101,0011
addr
ADDR
2 Bit
Decoder
Figure 1: I2C Serial Interface and Programmable
Memory Array
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12
Multiple-Output Regulator for
Automotive LCD Displays
A8603
Programmable Regulators
The target voltage for each output regulator is programmed by
writing to a register, according to the following equation:
The A8603 has four voltage regulators: AVDD, VCOM, VGL,
and VGH.
Target_Voltage = Min_voltage + #steps × step_size
For example, to set AVDD to 12 V, the user should write ‘0x59’
to Reg0x00. This is because:
Target voltages of all four regulators are programmable by
internal registers. In addition, other features (such as startup
and shutdown sequences, Fault retry counter, etc.) can also be
programmed.
#steps = (Target_Voltage – Min_Voltage) / step_size
= (12 – 5) / 0.07874 = 88.9
So the content of Reg0x00 is 89 in decimal, or ‘0x59’ in hexadecimal.
Table 2: Target Voltages
Output Regulator
Register
Min. Voltage (V)
Max. Voltage (V)
DAC # of Bits
DAC # of Steps
Step Size (mV)
78.74
AVDD
00
5 (Reg=0x00)
15 (0x7F)
7
127
VCOM
01, 02
2.5 (0x0000)
7.5 (0x01FF)
9
511
9.785
VGL
03
–3.6 (0x00)
–13.03 (0x3F)
6
63
–149.7
VGH
04
9.9 (0x00)
31.236 (0x7F)
7
127
168
*Note: AVDD must be at least 1.5V higher than VCOM, so not all combinations of VCOM and AVDD are possible.
Table 3: Startup Time Delay
Refer to Startup Timing Diagram on how those time delays are defined.
Timer
Min. Delay (ms)
Max. Delay (ms)
Step Size (ms)
Number of Bits
t1 = AVDD
0 (0x00)
25.5 (0xFF)
0.1
8
t2 = VCOM
0
25.5
0.1
8
t3 = VGL
0
25.5
0.1
8
t4 = VGH
0
25.5
0.1
8
Table 4: Shutdown Time Delay
Refer to Shutdown Timing Diagram on how those time delays are defined.
Timer
Min. Delay (ms)
Max. Delay (ms)
Step Size (ms)
Number of Bits
t5 = AVDD
0 (0x00)
25.5 (0xFF)
0.1
8
t6 = VCOM
0
25.5
0.1
8
t7 = VGL
0
25.5
0.1
8
t8 = VGH
0
25.5
0.1
8
Name
Register
Default
Min.
Max.
Step Size
Number of Bits
Watchdog Timer
0x09
51.2 (0x10) ms
9.6 (0x03) ms
99.2 (0x1F) ms
3.2 ms
5
Cooldown Timer
0x0B
102.4 (0x20) ms
9.6 (0x03) ms
201.6 (0x3F) ms
3.2 ms
6
Fault Retry Counter
0x0A
8 (0x08)
0 (0x00)
15 (0x0F)
1
4
Dithering:
Reg0x10 bit[0,1]: controls Dithering off, ±5%, 10% or 15%.
Power Sequence:
Reg0x10 bit4: By default VGL is enabled before VGH during power-up. But if this bit is set to ‘1’, then VGH is enabled first.
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Multiple-Output Regulator for
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A8603
Table 5: I2C Register Map
Registers
Default
Regulator Programming
Address
Comments
0x00-0x13
AVDD_voltage
0x40
0x00
7 bits adjust AVDD regulator output from 5 V to 15 V in 78.74 mV step.
VCOM_voltage_msb
0x1
0x01
VCOM_voltage_lsb
0x0
0x02
9 bits adjust VCOM regulator output from 2.5 V to 7.5 V in 9.785 mV step.
Must be programmed in the order of MSB followed by LSB.
VGL_voltage
0x20
0x03
6 bits adjust VGL regulator output from –3.6 V to –13.03 V in –150 mV step.
VGH_voltage
0x40
0x04
7 bits adjust VGH regulator output from 9.9 V to 31.236 V in 168 mV step.
delay_startup_AVDD
0x0
0x05
Program the turn-on delay for AVDD. 100 µs step size. 0 ms to 25.5 ms.
delay_startup_VCOM
0x20
0x06
Program the turn-on delay for VCOM (after AVDD). 100 µs step size. 0 ms
to 25.5 ms. See Startup Timing diagram.
delay_startup_VGL
0x40
0x07
Program the turn-on delay for VGL. 100 µs step size. 0 ms to 25.5 ms.
delay_startup_VGH
0x40
0x08
Program the turn-on delay for VGH (after VGL). 100 µs step size. 0 ms to
25.5 ms.
watchdog_timer
0x10
0x09
Maximum time allowing regulator to reach its target value. 3.2 ms step.
9.6 ms to 99.2 ms. Same value is used for all regulators.
fault_counter
0x8
0x0A
Programmable counter allowing system to reattempt 0 to 15 times at the
event of fault.
cooldown_timer
0x20
0x0B
Prevent immediate reattempt after the fault. System will wait for timer
to expire before possible reattempt to turn on the regulators. Step size
3.2 ms. Range 9.6 ms to 201.6 ms.
delay_shutdown_AVDD
0x0
0x0C
Program the turn-off delay for AVDD (after VCOM). 100 µs step size. 0 ms
to 25.5 ms. See Shutdown Timing diagram.
delay_shutdown_VCOM
0x0
0x0D
Program the turn-off delay for VCOM. 100 µs step size. 0 ms to 25.5 ms.
delay_shutdown_VGL
0x0
0x0E
Program the turn-off delay for VGL (after VGH). 100 µs step size. 0 ms to
25.5 ms.
delay_shutdown_VGH
0x0
0x0F
Program the turn-off delay for VGH. 100 µs step size. 0 ms to 25.5 ms.
dither
0x0
0x10
Bit[1,0] for dither programming (off/5%/10%/15%);
Bit4 for VGL/VGH power sequence option.
regulator_internal_enable
0x0
0x11
‘1’ = Turn all regulators on. ‘0’ = OFF
spare1
0x0
0x12
Spare
spare2
0x0
0x13
Spare
Fault Status
0x14-0x1B
output_status_now
0x0
0x14
Present output voltage status of regulators (over 10%, 30%, or 90%)
ilimt_status_now
0x0
0x15
Present output current status of regulators (OCP)
fault_status_now
0x0
0x16
Present fault status (TSD, FSET_short, SW_OVP, SW_OCP, etc.)
output_status_hold
0x0
0x17
Latched output voltage status (over 120% or under 80%)
ilimt_status_hold
0x0
0x18
Latched output current status
fault_status_hold
0x0
0x19
Latched fault status
rstatus_hold
0x01
0x1A
Retry counter status [bit 4:7], Diagnostic [2,3], Hard_Reset [1], and POR [0].
sstatus_hold
0x0
0x1B
OVP/UVP status of regulators during startup
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Multiple-Output Regulator for
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A8603
DIAGNOSTIC REGISTERS
All faults and critical signals are recorded into log registers.
External devices can read these log registers for diagnostic or
maintenance purposes.
Real-Time Status Registers
Registers 0x14 to 0x16 are read-only (refer to Tables 6 - 8).
The A8603 provides two types of diagnostic status registers:
• Registers 0x14-16 (#20-22 in decimal) store the real-time
status bits for regulator voltage, current, and fault conditions.
• Registers 0x17-1B (#23-27 in decimal) store the ‘latched’
status bits for voltage, current, and fault conditions. In case
of a fault shutdown, the real-time status bits may be cleared,
but the user can read the latched status bits and determine the
cause for the shutdown.
Table 6: Register 0x14 – Output Voltage Status During Startup/Shutdown
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
VGH > 90%
VGL > 90%
VCOM > 90%
AVDD > 90%
VGH > 30%
VGL > 30%
VCOM > 10%
AVDD > 10%
Each bit is set to ‘1’ when its corresponding regulator voltage is above threshold. They are only useful during startup and shutdown.
Table 7: Register 0x15 – Output Current Status During Operation
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
VGH ILimit
VGL ILimit
VCOM ILimit
AVDD ILimit
Each bit is set to ‘1’ when its corresponding regulator is operating at current limit. Note that those bits are ignored during startup phase (where all regulators must work at current limit to charge up output capacitors quickly). During normal operation mode, it is acceptable for any regulator to reach its current limit momentarily. Only if the overcurrent
condition persists for 50 ms, then the FAULT pin is pulled down and a RailFault (Reg0x16 bit2) is recorded.
Table 8: Register 0x16 – Fault Status
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FAULT
MaxRetry
WatchDog
SW ILimit2
SW OVP
Rail Fault
FSET fault
TSD
Explanation of each bit:
Bit7 = 1 if any Fault has occurred (it is not set in case of a POR or Hard-Reset).
Bit6 = 1 if the number of fault retries has reached MaxRetry limit.
Bit5 = 1 if the startup watchdog timer (Reg0x09) has expired before all output regulators can reach 90% target.
Bit4 = 1 if the boost switch current has exceeded its secondary OCP limit (150% of cycle-by-cycle current limit).
Bit3 = 1 if the boost switch voltage has exceeded its OVP threshold.
Bit2 = 1 if any output regulator reached its OCP limit for 50 ms.
Bit1 = 1 if the FSET pin is either open or shorted to GND.
Bit0 = 1 if a thermal shutdown has occurred.
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Multiple-Output Regulator for
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A8603
Latched Status Registers
Registers 0x17 to 0x1B hold the status bits after a fault has
occurred. Each bit is read-only and can be only cleared by writing
a ‘1’ to it. In case of a fault shutdown, the user can read those
registers to determine the cause of the shutdown, and then clear
them by writing ‘0xFF’ to each register.
Table 9: Register 0x17 – Latched Output Over- and Undervoltage Protection Fault
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
VGH > 120%
VGL > 120%
VCOM > 120%
AVDD > 120%
VGH < 80%
VGL < 80%
VCOM < 80%
AVDD < 80%
Each bit is set to ‘1’ when its corresponding regulator has tripped OVP/UVP fault. Note that those bits can only be set after all regulators have finished startup stage and the IC
is in normal operation mode.
Table 10: Register 0x18 – Latched Output Overcurrent Protection Fault
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
-
-
-
VGH ILimit
VGL ILimit
VCOM ILimit
AVDD ILimit
Each bit is set to ‘1’ when its corresponding regulator is operating at current limit during normal operation.
Table 11: Register 0x19 – Latched Fault Status
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FAULT
MaxRetry
Watchdog
SW ILimit2
SW OVP
Rail Fault
FSET fault
TSD
See Register 0x16 for explanation of each bit.
Table 12: Register 0x1A – Latched Non-Fault Status
bit7
bit6
bit5
bit4
Current Retry Counter (Read-Only)
bit3
bit2
bit1
bit0
SW ILimit1
Slow Shutdown
Hard Reset
Power-On Reset
Bit[4..7] = Current Retry Counter (0 to 15)
Bit3 = 1 if boost switch cycle-by-cycle current limit has be reached. This is not a fault condition and IC does not shutdown.
Bit2 = 1 if during shutdown, any regulator failed to decay below 10% (AVDD/VCOM) or 30% (VGL/VGH) before watchdog timer expires. This is not a fault since the IC still
shuts down afterward.
Bit1 = 1 if the IC has finished a hardware-initiated shutdown (by EN = L briefly) and all registers are restored to default values.
Bit0 = 1 if the IC has finished a power-on reset and all registers are initialized to their default values.
Note that after a Power-On Reset (or a Hard Reset), the output regulator cannot be enabled until bit0 (or bit1) is cleared. This can be done by writing a ‘0x03’ to Register0x1A.
Table 13: Register 0x1B – Latched Over- and Undervoltage Status During Startup
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
VGH > 120%
VGL > 120%
VCOM > 120%
AVDD > 120%
VGH < 80%
VGL < 80%
VCOM < 80%
AVDD < 80%
This is similar to Register 0x17, except it only records OVP/UVP during startup phase. Suppose, under certain unlikely situations, a regulator output rises above 120% or
drops below 80% after it reached 90% but before the IC enters normal operation mode, then it will be recorded.
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Multiple-Output Regulator for
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A8603
DESCRIPTION OF REGULATORS
AVDD Regulator
VCOM Regulator
The AVDD output is driven by a linear regulator, which takes its
input power from the boost output voltage. The target voltage of
AVDD is programmable through Register 0x00 (7 bits). Its range
is between 5 V (Register = 0x00) and 15 V (Register = 0x7F)
in 127 steps, with step resolution = 78.74 mV. A representative
block diagram is shown in Figure 3.
The VCOM output is also driven by a linear regulator similar to the
case of AVDD, except that it takes its input power from the regulated
AVDD output voltage. This arrangement gives VCOM exceptional
stability over full operating temperature range. The target voltage of VCOM is programmable through Register 0x01-02 (9 bits
total). Its range is between 2.5 V (Register=0x0000) and 7.5 V
(Register=0x01FF) in 511 steps, with step resolution = 9.785 mV.
The AVDD circuit monitors the voltage drop across its linear
regulator. If this voltage drop is less than the headroom required
(approximately 2 V between OUT and AVDD), the monitor circuit sends a control signal to cause the boost voltage to increase.
This ensures there is always enough headroom for regulation.
In order to ensure there is enough headroom, AVDD must be at
least 1.5 V higher than VCOM.
If VCOM is not required, the VCOM pin can be left open, but a
small output capacitor (approximately 0.1 μF) must be present to
prevent oscillation.
From boost
output
VOUT
OCP
+
R SC
Fold
Back
Linear Regulator
Enable
Reference
Voltage
–2 V
–
+
PMOS
1.8 V
AVDD
1.8 V
Target Voltage
I2C Register
0x00
7
To boost
controller
DAC
R
250 Ω
CAVDD
(external)
Discharge
AGND
Figure 3: Representative Block Diagram of the
AVDD Regulator
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Multiple-Output Regulator for
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A8603
VGL/VGH Charge Pumps
The A8603 uses a 2× charge pump to generate VGH from boost
voltage. If necessary, a 3× charge pump can be implemented at
the VGH3 pin using external components. See Representative
Block Diagrams as shown in Figures 4 and 5. Depending on the
From boost
output VOUT
magnitude of VGH, using a 3× charge pump may lower the boost
output voltage and hence improve the system efficiency. See
Boost Controller section for details.
Switching Sequence:
• S1 and D1 = on: charging external fly cap
• S2 and D2 = on: dumping to VGH
OCP
Enable
CP11
CP12
External
Fly
Cap
D1
VREF
1.8 V
S1
S2
D2
Linear Regulator
To boost
controller
VGH
VGH3
2× Charge Pump
1.8 V
R
Target Voltage
I2C Register
0x04
7
C VGH
(external)
500
DAC
Discharge
AGND
Figure 4: Representative Block Diagram of the VGH Regulator in 2× Charge Pump Mode
From boost
output VOUT
Switching Sequence:
• S1 and D1 = on: charging up flying caps C1 and C2
• S2 and D2 = on: discharging C1 to VGH and C2 to VGH3
OCP
Enable
CP11
1.8 V
Linear Regulator
CP12
C1
D1
VREF
D2
To boost
controller
C2
S1
S2
VGH
(2× Charge Pump)
2× Charge Pump
D3
VGH3
(3× Charge Pump)
D4
C3
C4
(external)
1.8 V
Target Voltage
I2C Register
0x04
7
R
500
DAC
Discharge
AGND
Figure 5: Representative Block Diagram of the VGH Regulator in 3× Charge Pump Mode
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Multiple-Output Regulator for
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A8603
An inverting charge pump is used to generate the negative voltage
for VGL. A representative block diagram is shown in Figure 6.
From boost
output VOUT
Switching Sequence:
• S1 and D1 = on: charging external cap
• S2 and D2 = on: dumping to VGL
OCP
Enable
CP21
S1
To boost
controller
CP22
External
Fly Cap
S2
D2
External
Silicon Diode
D1
Linear Regulator
–1× Charge
Pump
500 Ω
0V
R
1.8 V
VGL
C VGL
(external)
2R
Discharge
I2C Register
0x03
7
AGND
DAC
Target Voltage
Figure 6: Representative Block Diagram of the VGL Negative Charge Pump Mode
The frequency of the charge pumps is the same as the boost
switching frequency (or external SYNC frequency). When an
external SYNC signal is used, it is internally converted into a
clock signal with the same frequency, but at 50% duty cycle.
The value of the flying capacitor can be calculates as follows:
Recommended values of the external flying capacitor, CFLYx, on
the CPxx pins depends on the switching frequency as shown in the
following table; a voltage rating of 25 V is sufficient.
2. Assuming a flying capacitor ripple voltage of 100 mV, and a
maximum output current of 20 mA, the series resistance is:
Table 14: Recommended Flying Capacitor Values
3. Therefore at an fSW of 2 MHz, the required capacitance,
CFLY2, is 0.1 μF.
Switching Frequency (MHz)
CFLYx (µF)
2
0.1
1
0.22
0.35
0.47
1. The equivalent series resistance of the flying capacitor is:
ESRFLY2 = 1 / ( fSW × CFLY2 )
(2)
RFLY2 ≤ 0.1 (V) / 0.02 (A) = 5 Ω
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Multiple-Output Regulator for
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A8603
Boost Controller
The A8603 contains an integrated DMOS switch and PWM controller to drive a boost converter. The input voltage, VIN, (3.3 V
nominal) is boosted to an intermediate voltage, VOUT, which is
the lowest voltage required to keep all outputs within regula-
tion. The final output voltage is decided by the regulator, which
requires the highest boost voltage. This is illustrated in Figure 7.
18
16
Boost Voltage (V)
14
12
10
8
6
Boost Voltage = highest of:
-VGL + 3.5 V
AVDD + 2.1 V
VGH/2 + 2.9 V
(or VGH/3 + 3.7 V)
4
2
0
-12 -10 -8 -6 -4 -2
0
VGL
2
4
6
AVDD
8 10 12 14 16 18 20 22 24 26 28 30
VGH2
VGH3
Figure 7: Boost Voltage Requirement with Respect to VGL, AVDD and VGH
For example: assume the output requirements for a certain LCD
panel are: VAVDD = 10 V, VVGH = 18 V and VVGL = –7 V, then:
• AVDD (LDO):
VOUT ≥ VAVDD + 2.1 (V) = 12.1 V
• VGH (2× Charge Pump):
VOUT ≥ VVGH / 2 + 2.9 (V) = 11.9 V
• VGL (Inverted Charge Pump):
VOUT ≥ – VVGL + 3.5 (V) = 10.5 V
In this example, AVDD has the highest requirement, so the boost
output voltage will be regulated at a VOUT = 12.1 V approximately. However, if VVGH were increased to 24 V, it would
require higher voltage, and then the boost converter would
increase the boost output voltage to 14.9 V to satisfy the 2×
charge pump. This leads to higher voltage drop across the linear
regulator for AVDD, and hence higher power loss. In such case, it
is worthwhile to consider the option of 3× charge pump for VGH.
• VGH (2× Charge Pump):
VOUT ≥ VVGH / 2 + 2.9 (V) = 14.9 V
• VGH (3× Charge Pump):
VOUT ≥ VVGH / 3 + 3.7 (V) = 11.7 V
So by using 3× charge pump for VGH, the boost voltage is
reduced to 12.1 V (as dominated by AVDD). This results in lower
power loss and hence better system efficiency.
A block diagram of the A8603 boost controller circuit is shown in
Figure 8. Typical values for external COMP components are RZ
= 511 Ω and CZ = 0.22 µF. Note that the boost stage simply provides an intermediate voltage. The actual output voltages (AVDD,
VGL, VGH) are controlled by linear regulators and charge
pumps, which contain their own internal compensation.
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Multiple-Output Regulator for
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A8603
VIN
VOUT
L
CIN
COUT
SW
A8603
Slopecomp
Oscillator
Enable
OVP
DMOS
PWM
Control
Multi-input
Transconductance
Amplifier
RZ
CZ
AVDD
VGL
VGH
OCP
Gm
RSC
COMP
AGND
PGND
Figure 8: Boost Controller Circuit
The boost controller is protected against overvoltage and overcurrent fault conditions.
• The Switch OVP threshold, VSW(OVP), is internally set
at approximately 21 V typical. Under normal operating
conditions, the boost output voltage should always be lower
than 18 V, so only in the event of a fault will SW_OVP be
tripped (for example: boost diode open or VOUT pin open
during startup).
• The switch current is protected by a cycle-by-cycle current
limit (ISWILIM , 2.6 A typical). In the event of a heavy
load or during a transient, the SW peak current may reach
SWILIM level momentarily. In this case, the present on-time
is truncated immediately, but no signal is generated on the
FAULT pin. The switching will continue with the same period.
• In the event of a catastrophic failure (such as shorted
inductor), the SW current may exceed SWILIM2, which is
150% of the SWILIM threshold. In this case, the IC is shut
down immediately.
It is important to note that the A8603 cannot protect the input current in case there is a short from boost output to GND. To do so
requires the use of an input disconnect switch.
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Multiple-Output Regulator for
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A8603
Boost Switching Frequency
The boost stage switching frequency, fSW , of the A8603 can be
programmed by using an external resistor between the FSET pin
to GND, or it can be synchronized to an external clock frequency
between 350 kHz and 2.25 MHz.
During startup, the A8603 senses the FSET pin for any external
SYNC signal. If periodic logic transitions are detected (Low <
0.4 V or High > 1.5 V), this is evaluated as an external clock
signal, and the boost switching frequency is synchronized to it.
If no periodic signal is detected, the bias current flowing through
FSET_SYNC pin is used to determine the switching frequency.
The bias current is set by an external resistor, RFSET , on the
FSET_SYNC pin. The relation between RFSET and switching
frequency is given as:
RFSET = 10.21 / (fSW – 0.0025)
(3)
where RFSET is in kΩ and fSW is in MHz.
This relationship is charted in Figure 9. For example, to get a
switching frequency of 2 MHz requires an RFSET of 5.11 kΩ.
Suppose the A8603 is started up with a valid external SYNC
signal, but the SYNC signal is lost during normal operation. In
that case, one of the following happens
• If the external SYNC signal is high impedance (open), the
A8603 continues normal operation, at the switching frequency
set by RFSET . No FAULT flag is generated
• If the external SYNC signal is stuck at low (shorted to
ground), the A8603 begins a shutdown sequence, at the
switching frequency set by the internal 1 MHz oscillator. The
FAULT pin is pulled low and the internal error counter is
increased by 1.
Note:
To prevent generating a fault when the external SYNC signal
is stuck at low, the circuit shown in Figure 10 can be used.
When the external SYNC signal goes low, the A8603 will continue to operate normally at the switching frequency set by
RFSET. No FAULT flag is generated.
2.2
2.0
Frequency (MHz)
1.8
A8603
External
Synchronization
Signal
1.6
1.4
FSET
1.2
220 pF
1.0
0.8
Schottky
Barrier
Diode
0.6
0.4
RFSET
10.2 kΩ
0.2
0.0
0
5
10
15
RFSET (kΩ)
20
25
Figure 9: Boost Switching Frequency as a Function of
FSET Resistance
Figure 10: Countermeasure to Prevent External Sync
Signal Stuck-at-Low Fault
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A8603
Multiple-Output Regulator for
Automotive LCD Displays
Boost Frequency Dithering
The A8603 has an optional dithering function for the boost
switching frequency. When enabled, the switching frequency is
varied linearly within a certain frequency range, as modulated by
a triangular ramp signal. By spreading the frequency of the boost
converter, the overall system noise magnitude can be greatly
reduced. Note that the frequency dithering function is not available when an external synchronization signal is used at the FSET
pin.
Table 15: Register 0x10 Dithering Feature
Reg0x10 Content
(in binary)
Dithering Feature
(frequency range)
‘00’
0%
‘01’
±5%
‘10’
±10%
‘11’
±15%
The dithering feature is controlled by Register 0x10. Frequency
of the dithering modulation ramp signal is 12 kHz typical.
Frequency
2.2 MHz
2.0 MHz
fSW
1.8 MHz
Time
~80 µs
Figure 11: Switching Frequency Varied Linearly
In this example, Reg0x10 = ‘10’ and the central switching frequency
is fSW = 2.0 MHz. The actual frequency is varied linearly between
fSW –10% and fSW +10% by the modulating frequency at 12 kHz.
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Multiple-Output Regulator for
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A8603
FAULT CONDITIONS
The A8603 has extensive fault detection mechanisms, to protect
against all perceivable faults at the IC level (pin open, pin short
to GND, pin short to neighboring pins, and so forth) and at the
system level (external component open/short, component value
changes from –50% to +100%, and so forth).
Over- and Undervoltage Protections
The FAULT pin of the A8603 has an open-drain pull-down device
internally. An external resistor is required to pull this pin to the
desired logic-high level (such as 5 V or 3.3 V) at no-fault. Choose
a resistor value such that, in case of fault, the current into the
FAULT pin is not more than 1 mA. For example, if the external
supply is 5 V, then the pull-up resistor should be 5 kΩ or higher.
In case of an output short, the output voltage may make a sudden
change that is either +20% over, or –20% under the target voltage. This will trigger the OVP/UVP fault and force the A8603
to shut down. The offending regulator is turned off immediately.
The other outputs are then shut down following normal sequence.
In general, if a fault is detected, the A8603 halts operation and
pulls the FAULT pin low. It then attempts to restart operation
after a delay, tRESTART (programmable between 10 and 200 ms).
Internally there is a Fault counter that keeps track of how many
times any fault has occurred. If the Fault counter reaches maximum retry limit (programmable between 0 and 15), the A8603
stops any further attempts and returns to initial state with all
regulators disabled. The Fault status register can be read through
I2C commands, but internal enable signal is prohibited in this
state. The Fault counter is cleared only by a completed shutdown
sequence after EN = low, or by a power reset (VIN drops below
UVLO).
As an example: If the FSET pin is either open or shorted to GND,
the A8603 will report a fault by asserting FAULT = L once EN =
H. All output regulators are disabled in this case, but the user can
still use an I2C Read command to read the fault status registers,
and find out which type of fault has occurred. See “Diagnostic
Registers” section for details.
All regulator output pins (AVDD, VGL, VGH, VCOM) are
monitored for overvoltage and undervoltage faults during normal
operation.
OVP/UVP detections are disabled during the startup sequence. If
any output fails to reach 90% of its target voltage within a timeout period, tSS(TO) (50 ms typical), a fault is generated and then
the A8603 shuts down.
Each regulator output (AVDD, VGH, VGL and VCOM) is protected by its own independent overcurrent limit. When an output
current exceeds its limit, the corresponding regulator goes into
overcurrent protection mode to protect itself from damage. See
next section for illustrations of the protection characteristics.
If the overcurrent condition persists for 50 ms, all regulators are
turned off following the normal shutdown sequence. This is different from output OVP/UVP fault, where the offending regulator
is shut down immediately, while other regulators are shut down in
sequence.
Overcurrent Protection Mechanisms for AVDD, VCOM, VGH and VGL
VGH, VGL
AVDD
Target
VCOM
Target
Target
3V
0
33%
Output
Current
0
100%
33%
Output
100%
Current
0
Output
Current
100%
Figure 12: Regulator Current Fold-Back in Case of Overcurrent Conditions
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Multiple-Output Regulator for
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A8603
Overcurrent Protection
output voltage has reached target value. In case there is an output
short, or if the output capacitor is much larger than expected, the
OCP mode may last for 50 ms. At this point, an OCP fault is generated. The IC then begins to shut down all regulators according
to programmed shutdown sequence.
Each output regulator has a built-in current limit to prevent damages from overcurrent. During startup, a regulator may initially
operate in overcurrent protection mode while its output capacitor is being charged. Normally, the current will reduce once the
Examples of Various Fault Conditions
Internal
Enable
Watchdog Timer (50 ms)
Cool Down Timer (10-200 ms)
Shutdown
tSU_TO
tRESTART
Target
AVDD
0V
VCOM
Target
0V
0V
VGL
Target
VGH
30%
0V
FAULT
0V
A
B
C
D
E
Sequence of events:
A: User issues I2C command to set INT_EN = H, to enable all output regulators.
B: During startup, VGL is unable to reach its regulation target due to an output short or unexpected heavy load.
C: After Watchdog Timer expired, the A8603 reports that a fault has occurred (by asserting FALUT = L) and begins to shutdown all its output
regulators in normal sequence. Fault counter is incremented by 1.
D: When the last regulator (VGH in this case) has finished shutdown, the A8603 waits for a cooldown period (programmable between 10 and
200 ms).
E: Retry startup as long as the maximum number or retries (programmable between 0 and 15) is not exceeded.
Figure 13: Timing Diagram where VGL Failed to Reach Its Target Voltage at Startup
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Multiple-Output Regulator for
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A8603
Internal
Enable
Startup
Cool Down Timer (10-200 ms)
Shutdown
Normal
Operation
t_RESTART
Target
AVDD
0V
Target
80%
VCOM
0V
0V
VGL
Target
VGH
30%
0V
FAULT
0V
A
B
C
D
E
Sequence of events:
A: User issues I2C command to set INT_EN = H, to enable all output regulators.
B: Startup is completed successfully when the last regulator (VCOM in this case) has reached 90% target voltage.
C: VCOM output voltage drops to below 80% target due to an output short or unexpected heavy load. The A8603 detects an Output_UVP fault
and shuts down VCOM immediately. All other regulators are then shut down in normal sequence.
D: When the last regulator (VGH in this case) has finished shutdown, the A8603 waits for a cooldown period (programmable between 10 and
200 ms).
E: Retry startup as long as the maximum number or retries (programmable between 0 and 15) is not exceeded.
Figure 14: Timing Diagram where VCOM Suffered an Output Undervoltage Fault during Normal Operation
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Multiple-Output Regulator for
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A8603
Internal
Enable
Shutdown
Startup
IC Cools Down
IC Heats Up
Target
AVDD
0V
Target
VCOM
0V
0V
VGL
Target
90%
VGH
30%
0V
TSD
Hysteresis
Junction
Temperature
TSD – Hyst
FAULT
- 0V
A
B
C
D
E
Sequence of events:
A: User issues I2C command to set INT_EN = H, to enable all output regulators.
B: Startup is completed successfully when the last regulator (VGH in this case) has reached 90% target voltage.
C: During operation, should the junction temperature rises to TSD threshold (due to high ambient temperature or unexpected heavy load),
the IC turns off all output regulators immediately without following normal shutdown sequence. FAULT is pulled low and fault counter is
incremented by 1.
D: After shutdown is completed, the IC waits for junction temperature to drop to TSD-Hyst (typically 20°C below TSD) before attempting retry.
E: Retry startup as long as the maximum number or retries (programmable between 0 and 15) is not exceeded.
Figure 15: Timing Diagram Showing a Thermal Shutdown and Restart
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Multiple-Output Regulator for
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A8603
VIN
(power supply)
EN (external
enable)
BIAS (IC
internal supply)
FAULT = L if overcurrent
persists for 50 ms
FAULT
(pull-up to VIN)
50 ms
Normal Operation Phase
(Regulator OCP recorded)
Startup Phase
(Regulator OCP not recorded)
Internal
Enable
t1
AVDD
0
t2
VCOM
0
0
t3
VGL
90%
t≥0
90%
VGH tripped current
limit in normal op phase
t4
VGH
0
VGH operating
at current limit
A
B
C
D
E
F
G
Sequence of events:
A: System controller brings EN = H to enable the A8603.
B: After A8603 performs a POR (Power-On Reset), it pulls down FAULT flag to signal that it is ready for I2C commands.
C: System controller detected FAULT = L and sends in I2C command to clear the POR status bit. This resets FAULT to H (unless there were
other faults detected).
D: After programming the A8603 registers, system controller sets the internal_enable bit to 1, to turn on all output regulators.
E: The last regulator (VGH in this example) starts charging.
F: When all regulators have reached 90% of regulation target, the A8603 declares Startup Phase over and enters into normal operation phase.
However, VGH is still operating at its current limit, to charge its output cap to 100% . Therefore A8603 records this overcurrent status in
Reg0x18, bit3. This is not considered a fault.
G: During normal operation phase, if any regulator shows overcurrent for 50 ms, then the A8603 will pull FAULT = L and shutdown all regulators in sequence.
Figure 16: Timing Diagram Showing when a Regulator Overcurrent Condition is Reported
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Multiple-Output Regulator for
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A8603
Pre-Output Fault Detection
When EN = High and the A8603 output regulators are enabled
through I2C command, a startup sequence is followed before
the regulators are powered up. The sequence checks for extreme
conditions and proceeds as described in Table 16.
General Fault Detection
The faults described in Table 17 are continuously monitored,
whether during startup, normal operation, or shutdown.
Table 16: Pre-Output Fault Detection Sequence
Step Number
Step Description
Step Description
Fault Tripped?
1
Check VIN UVLO
A8603 remains powered-down until VIN is above VUVLO.
No
2
Power-up internal
rail
A8603 initializes.
No
3
Check internal rail
UVLO
BIAS charges internal rail indefinitely, until VBIAS is above UVLO.
No
4
Turn on AVDD
Enable AVDD and check to see if output reaches >90% of target voltage within tSS(TO).
Yes
5
Turn on VGL
Enable VGL and check to see if output reaches >90% of target voltage within tSS(TO).
Yes
6
Turn on VGH
Enable VGH and check to see if output reaches >90% of target voltage within tSS(TO).
Yes
7
Turn on VCOM
Enable VCOM and check to see if output reaches >90% of target voltage within tSS(TO).
Yes
Table 17: General Fault Detection
Fault Description
A8603 Response to Fault
Fault Tripped?
AVDD, VCOM,VGH or VGL 20%
under target
Shutdown using shutdown sequence. Fault counter increased by one,
retry after tRESTART.
Yes: FAULT set during tRESTART.
AVDD, VCOM,VGH or VGL 20% over
target
Over target regulator rail shutdown immediately. Other regulator rails
shutdown using shutdown sequence. Fault counter increase by one
retry after tRESTART.
Yes: FAULT set during tRESTART.
Overcurrent limit for iAVDD, iVCOM, iVGH
or iVGL
Offending regulator rail goes into current fold-back or current limit.
Shutdown using shutdown sequency after tOCP. Fault counter increase
by one, retry after tRESTART.
Yes: FAULT set during tRESTART.
SW_OVP exceeded
Shutdown all regulators immediately without using shutdown sequence.
Fault counter increased by one, retry after tRESTART.
Yes: FAULT set during tRESTART.
External UVLO reached
Shutdown all regulators immediately without using shutdown sequence.
Fault counter reset to 0, retry after tRESTART.
No
Internal (Bias) UVLO
Shutdown all regulators immediately without using shutdown sequence.
Fault counter reset to 0, retry after tRESTART.
No
TSD exceeded
Shutdown all regulators immediately without using shutdown sequence.
Fault counter increase by one, retry after tRESTART.
Yes: FAULT set during tRESTART.
SWILIM2 (150% of cycle-by-cycle
limit) exceeded
Shutdown all regulators immediately without using shutdown sequence.
Fault counter increased by one, retry after tRESTART.
Yes: FAULT set during tRESTART.
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Multiple-Output Regulator for
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A8603
Sleep
System Controller
Clears POR Bit and
Programs Each
Regulator
EN = High and VIN > UVLO
System Controller
Enables All
Regulators through
I2C
2.8 V Internal Rail
(VBIAS) Enabled
VBIAS > 2.6 V
Enable Internal
References
and Oscillator
Power-Up All
Regulators in
Sequence
System Controller Issues
I2C Commands
ICReady = High
Normal
Operation
Initialize Digital
Block. Assert FAULT
Flag to Signal IC
is Ready to Receive
I2C Commands.
FAULT = Low
Waiting for I2C
Commands from
System Controller
Non-Latched Fault
(Group 1 and 2)
No Faults
EN = L
Fault Monitoring
Fault Occured
Power-Down All
Regulators in
Sequence
Reset All I2C
Registers
Power-Down All
Regulators in
Sequence
Fault Diganostics
Latched Fault
(Group 3)
Sleep
Figure 17: Fault Checking During Startup and Normal Operation
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Multiple-Output Regulator for
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A8603
Fault Monitoring
The fault monitoring system prioritizes the fault in three different
categories. Based on the severity of the fault, diagnostic algorithm handle the shutdown sequence of all regulators.
FAULT1 (GROUP1)
If any fault from the below list is detected, the A8603 halts
operation and pulls the FAULT pin low. All regulators shut down
in sequence. It then attempts to restart operation after a delay,
tRESTART (default 100 ms). Internally, there is a fault counter that
keeps tracks of how many times any fault has occurred. If the
fault counter reaches its programmed limit (default 8), the A8603
is completely shutdown. A hardware reset (either by EN = L or
VIN below UVLO) is then required before the A8603 can restart.
Startup Fail
Regulator output voltage fails to reach 90% of its
target voltage within timeout period
Regulator
Undervoltage
Regulator output voltages are below 80% of the
target voltage. This signal is ignored during startup.
Regulator
Overvoltage
Regulator output voltage are above 120% of the
target voltage. This signal is ignored during startup.
Regulator
Overcurrent
Regulator output currents are above the current limit
threshold. This signal is ignored during startup.
FSET Shorted
FSET pin shorted to ground. IC moves to internal
fixed 1 MHz oscillator.
• Each regulator output is protected by its own independent
overcurrent limit. When an output current exceeds its limit,
the corresponding regulator goes in to overcurrent protection
mode to protect itself from damage. If the overcurrent
condition persists for 50 ms, all regulators are turned off
following the normal shutdown sequence.
• Each regulator output is protected by its own overvoltage
fault detection. When an output voltage exceeds its limit, the
corresponding regulator is turned off immediately. The other
outputs then shut down following normal sequence. The same
applies to undervoltage fault detection.
• When FSET pin is shorted to ground, IC begins a shutdown
sequence, at the switching frequency set by the internal 1 MHz
oscillator. The FAULT pin is pulled low and the internal error
counter is increased by 1.
FAULT2 (GROUP2)
When following faults are detected, the A8603 halts operation
and pulls the FAULT pin low. All outputs are shut off immediately. It then attempts to restart operation after a delay, tRESTART
(default 100 ms). Internally, there is a fault counter that keeps
tracks of how many times any fault has occurred. If the fault
counter reaches its programmed limit (default 8), the A8603 is
completely shut down. A hardware reset (either by EN = L or VIN
below UVLO) is then required before the A8603 can restart.
SW Overvoltage
SW pin voltage exceeds SWOVP
SW Overcurrent
SW pin current exceeds ISWILIM2.
Thermal
Shutdown
IC die temperature exceeds TTSD
FAULT3 (GROUP3)
When a supply undervoltage fault is detected, the A8603 shuts
down immediately. All outputs are turned off without following
the shutdown sequence. All digital states are erased. The FAULT
flag will not be asserted. The device will not attempt to restart.
VIN UVLO
VIN (input supply) is below 2.8 V.
BIAS UVLO
VBIAS (internal rail) is below 2.6 V.
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Multiple-Output Regulator for
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A8603
Start
Housekeeping
Startup
Shutdown All
Regulators in
Sequence
Fault
Group 1
Fault
Group 2
Run
Shutdown All
Regulators
Immediately
without
Sequence
End of Shutdown
End of Shutdown
Fault Counter
+1
Counter < Limit
Wait for 100 ms
Counter ≥ Limit
End/Sleep
Figure 18: Fault-Retry Counter
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Multiple-Output Regulator for
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A8603
THERMAL ANALYSIS
The thermal resistance, RθJA, of the QFN-24 thermally enhanced
package is 37°C/W. For long-term reliability, the package junction temperature should be kept at 150°C or below. Assuming a
maximum ambient temperature of 85°C, the power dissipation
budget, PD(max), is:
PD(max) = (TJ(max) – TA(max))/RθJA
D = 1 – VIN /(VOUT + VD)
where D = Duty Cycle of boost switch, VD is the forward
voltage drop of the external boost diode.
Substitute minimum VIN = 3 V, VOUT = 12.1 V, VD = 0.4 V to
get D = 0.76.
PCOND = (0.55 A)2 × 0.7 Ω × 0.76 = 0.16 W
= (150 (°C) – 85 (°C)) / 37 (°C/W) = 1.75 W
The power losses of the IC come from two main contributors: the
boost stage and the output regulators. These losses are calculated
separately, and then summed as follows.
Note that RDS(on) is 0.5 Ω typical, plus 40% for temperature
compensation at 125°C.
4. Estimate switching loss for the internal boost switch:
PSW = ISW × VSW × (tr + tf ) × fSW /2
Boost Stage Power Loss
To estimate the dissipation of the boost stage, calculate and sum
the losses due to switching losses, PSW, and conduction losses in
the switch, PCOND:
Assume tr = tf = 10 ns,
PSW = 0.55 A × 12.5 V × (10 ns + 10 ns) × 2 MHz/2 = 0.14 W
PD(BOOST) = PCOND + PSW
Therefore the total power dissipation on the boost stage is:
As an example, consider the following load conditions:
AVDD
VCOM
VGL
VGH
Boost
Voltage (V)
10
4
-8
18
12.1
Max. Current (mA)
100
4
2
2
110
1. Estimate the maximum output power for boost stage:
POUT(max) = VOUT(max) × IOUT (max)
IOUT = IAVDD + IVCOM + IVGL + 2 × IVGH
Based on the above load conditions, we conclude that Boost
VOUT = 12.1 V (see “Boost Controller” section for explanation)
and IOUT = 110 mA. Therefore POUT(max) = 12.1 V × 0.11 A =
1.33 W
2. Estimate the maximum input current:
IIN = PIN /VIN
PIN = POUT /η
where η is efficiency.
Assume minimum VIN of 3 V and a conservative efficiency
of 80%:
IIN = (1.33 W/0.8)/3 V = 0.55 A.
3. Estimate conduction loss for the internal switch:
PCOND = (IIN)2 × RDS(on) × D
Where ISW = IIN approximately, VSW = VOUT + VD; tr is the
rise time, and tf the fall time, of VSW.
PD(BOOST) = PCOND + PSW = 0.30 W
Output Regulator Power Loss
The output regulator power dissipation is the sum of the individual linear regulators:
PD(REG) = PLDO1 + PLDO2 + PLDO3 + PLDO4
Where LDO1-4 are linear regulators for AVDD, VCOM, VGL
and VGH, respectively.
PLDO1 = (VOUT – VAVDD) × ( IAVDD + IVCOM )
PLDO2 = (VAVDD – VVCOM) × IVCOM
PLDO3 = (VOUT – |VVGL|) × IVGL
PLDO4 = (VOUT – VVGH/2) × 2 × IVGH
Using the previously stated operating conditions, we then have:
PLDO1 = (12.1 V – 10 V) x 104 mA = 218 mW)
PLDO2 = (10 V – 4 V) × 4 mA = 24 mW
PLDO3 = (12.1 V – 8 V) × 2 mA = 8 mW
PLDO4 = (12.1 V – 18 V/2) × 2 × 2 mA = 12 mW
Finally, the IC consumes a bias current of approximately 5 mA
Allegro MicroSystems
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33
A8603
Multiple-Output Regulator for
Automotive LCD Displays
from VIN when output regulators are enabled. This adds power
consumption of approximately 15 mW at minimum VIN. Therefore the sum of power dissipations for all output regulators is
approximately 280 mW.
The total power dissipation of the IC is then the sum of the boost
stage and the linear regulators: 0.30 W + 0.28 W = 0.58 W. This
corresponds to a temperature rise of just 21.5°C. Therefore, at
the highest ambient temperature of 85°C, the estimated junction
temperature is 106.5°C under the above worst-case conditions.
Allegro MicroSystems
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34
Multiple-Output Regulator for
Automotive LCD Displays
A8603
PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000222 Rev. 2 or JEDEC MO-220WGGD.)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.30
0.50
4.00 ±0.15
24
24
1
0.90
1
A
2
2
4.00 ±0.15
2.10
4.10
2.10
25×
D
0.08
C
0.75 ±0.05
C
0.25 +0.05
–0.07
4.10
SEATING
PLANE
C
PCB Layout Reference View
0.02 +0.03
–0.02
0.50 BSC
1
0.40 ±0.10
0.20 MIN
B
2.10 ±0.10
E
XXXX
Date Code
Lot Number
Standard Branding Reference View
Lines 1, 2, 3 = 6 characters
2
Line 1: Part Number
Line 2: 4 digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
1
24
2.10 ±0.10
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
C
Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm
from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances;
when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation
(reference EIA/JEDEC Standard JESD51-5)
D
Coplanarity includes exposed thermal pad and terminals
E
Branding scale and appearance at supplier discretion.
Pin 1 Dot top left
Center align
Figure 20: Package ES, 24-Pin 4 mm × 4 mm QFN with Exposed Thermal Pad
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
35
Multiple-Output Regulator for
Automotive LCD Displays
A8603
For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000222 Rev 2 or JEDEC MO-220WGGD.)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.30
0.50
4.00 ±0.15
24
24
0.90
1
1
A
2
2
4.00 ±0.15
2.10
DETAIL A
24X
2.10
D
0.08
C
0.75 ±0.05
C
0.25
4.10
+0.05
–0.07
4.10
SEATING
PLANE
C
PCB Layout Reference View
+0.03
0.02 –0.02
0.50 BSC
0.14 REF
0.20 REF
0.05 REF
0.40 ±0.10
0.10 REF
0.203 REF
0.40 ±0.10
0.05 REF
B
Detail A
2.10 ±0.10
2
1
1
0.55 REF
24
2.10 ±0.10
0.10 REF
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
C
Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm
from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances;
when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation
(reference EIA/JEDEC Standard JESD51-5)
E
XXXX
Date Code
Lot Number
Standard Branding Reference View
Lines 1, 2, 3 = 6 characters
D
Coplanarity includes exposed thermal pad and terminals
Line 1: Part Number
Line 2: 4 digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
E
Branding scale and appearance at supplier discretion.
Pin 1 Dot top left
Center align
Figure 21: Package ES, 24-Pin 4 mm × 4 mm QFN with Exposed Thermal Pad and Wettable Flank
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
36
Multiple-Output Regulator for
Automotive LCD Displays
A8603
Revision History
Revision
Revision Date
Description of Revision
–
November 17, 2014
1
January 20, 2015
2
March 12, 2015
3
April 13, 2015
4
October 9, 2015
Added A8603KESTR-J to Selection Guide; corrected Terminal List Table and Shutdown Timing
Diagram
5
January 5, 2016
Updated Fault Conditions; corrected Package Outline Drawing
6
March 3, 2016
7
October 24, 2016
Corrected Pad corner in Pinout Diagram (page 4)
8
January 5, 2017
Updated Boost Controller section (pages 20-21); added wettable flank package option drawings
(pages 1 and 36)
9
January 18, 2017
Corrected pins CP11 to CP21 and CP12 to CP22 in Figure 6: Representative Block Diagram of the
VGL Negative Charge Pump Mode (page 19)
10
January 15, 2019
Minor editorial updates
11
January 27, 2020
Minor editorial updates
12
January 28, 2021
Updated Package Outline Drawings (pages 35-36).
Initial Release
Added Appendix A
Removed LP Package option
Corrected Table 13 title
Corrected Packing info in Selection Guide (page 2), Absolute Maximum Rating of FAULT pin
(page 3), and EN pin Pull-Down Resistance (page 7)
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
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37
Multiple-Output Regulator
for Automotive LCD Displays
A8603
APPENDIX A
I2C Interface Description
The A8603 provides an I2C-compliant serial interface that
exchanges commands and data between a system microcontroller
(master) and the A8603 (slave). Two bus lines, SCL and SDA,
provide access to the internal control registers. The clock input on
the SCL pin is generated by the master, while the SDA line functions as either an input or an open drain output for the A8603,
depending on the direction of the data flow.
SDA
The I2C input thresholds depend on the VBIAS voltage of the
A8603. The threshold levels across the operating VBIAS range are
compatible with 3 V logic.
SCL
Start
Condition
Stop
Condition
(A) Start and Stop conditions
Timing Considerations
I2C communication is composed of several steps, in the following
sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
while SCL is high (see figure A-1).
SDA
2. Address Cycle. 7 bits of address, plus 1 bit to indicate write (0)
or read (1), and an acknowledge bit (see figure A-2).
SCL
Change
SDA stable,
(B) Clock and data
bitofsynchronization
data allowed
3. Data Cycles. Reading or writing 8 bits of data followed by an
acknowledge bit (see figure A-2).
data valid
Figure A-1. Bit transfer on the I2C bus
4. Stop Condition. Defined by a positive edge on the SDA line,
while SCL is high (see figure A-1).
It is possible for the Start or Stop condition to occur at any time
during a data transfer. The A8603 always responds by resetting
the data transfer sequence. Except to indicate a Start or Stop condition, SDA must be stable while the clock is high (figure A-2).
SDA can only be changed while SCL is low.
Start
Condition
Read/Write Acknowledge
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
0
Acknowledge
Register Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
0
Acknowledge
Data (MSB byte)
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
A0 R/W AK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 AK D15 D14 D13 D12 D11 D10 D9
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
0
D8 AK
8
9
Acknowledge
Data (LSB byte)
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
D7 D6
SCL
1
2
D5
D4
D3
D2
D1
3
4
5
6
7
0
Stop
Condition
D0 AK
8
9
Figure A-2. Complete data transfer pulse train
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A-1
Multiple-Output Regulator
for Automotive LCD Displays
A8603
¯ ) is set low to indicate a
The state of the Read/Write bit (R/¯W
Write cycle and set high to indicate a Read cycle.
device must release the SDA line before the ninth clock cycle, in
order to allow the handshaking to occur.
The master monitors for an acknowledge bit to determine if the
slave device is responding to the address byte sent to the A8603.
When the A8603 decodes the 7-bit address field as a valid
address, it acknowledges by pulling SDA low during the ninth
clock cycle.
I2C Command Write to the A8603
The master controls the A8603 by programming it as a slave.
To do so, the master transmits data bits to the SDA input of the
A8603, synchronized with the clocking signal the master transmits simultaneously on the SCL input (figure A-3).
During a data write from the master, the A8603 pulls SDA low
during the clock cycle that follows each data byte, in order to
indicate that the data has been successfully received.
A complete transmission begins with the master pulling SDA low
(Start bit), and completes with the master releasing the SDA line
(Stop bit). Between these points, the master transmits a pattern of
¯ ), then the register
address bits with a Write command bit (R/¯W
After sending either an address byte or a data byte, the master
Start
Condition
Write
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
0
Slave
Acknowledge
0
Register Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Slave
Acknowledge
Slave
Acknowledge
0
0
A0 R/W AK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 AK
7
8
9
1
2
3
4
5
6
7
8
9
Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
Stop
Condition
D0 AK
8
9
Write to a single register
Write to multiple registers
Start
Condition
Write
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
0
Slave
Acknowledge
Slave
Acknowledge
0
Register N Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
0
A0 R/W AK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 AK
7
8
9
1
2
3
4
5
6
7
8
9
Slave
Acknowledge
Register N Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
0
D0 AK
8
9
Slave
Acknowledge
Register N+1 Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
D7
D6
D5
D4
D3
D2
D1
SCL
1
2
3
4
5
6
7
0
D0 AK
[Wraps to Register N+1]
8
Register N+n Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
[Wraps to Register N+n]
SDA
D7
D6
D5
D4
D3
D2
D1
SCL
1
2
3
4
5
6
7
9
Slave
Acknowledge
Stop
0
Condition
D0 AK
8
9
Figure A-3. Writing to single and to multiple registers
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A-2
A8603
address, and finally the data. The address therefore consists of
two bytes, comprised of the A8603 chip address, with the write
enable bit, followed by the address of the individual register.
Multiple-Output Regulator
for Automotive LCD Displays
After each byte, the slave A8603 acknowledges by transmitting a
low to the master on the SDA line. After writing data to a register
the master must provide a Stop bit if writing is completed. Otherwise, the master can continue sending data to the device and it
will automatically increase the register value by one for additional data byte. This allows faster data entry but restricts the data
entry to sequential registers.
SDA low (Start bit), and completes with the master releasing the
SDA pin (Stop bit). Between these points, the master transmits
¯ = 1) and
a pattern of chip address with the Read command (R/¯W
then the address of the register to be read. Again, the address
consists of two bytes, comprising the address of the A8603 (chip
address) with the read enable bit, followed by the address of
the individual register. The bus master then executes a Master
Restart, reissues the slave address, then the A8603 exports the
data byte for that register, synchronized with the clock pulse supplied by the master. The master must provide the clock pulses, as
the A8603 slave does not have the capability to generate them.
I2C Command Read from the A8603
The master can read back the register values of the A8603. The
¯ bit of the address byte. To do
Read command is given in the R/¯W
so, the master transmits data bits to the SDA input of the A8603,
synchronized with the clocking signal the master transmits
simultaneously on the SCL input. The pulse train is shown in figure A-4. A complete transmission begins with the master pulling
If the master does not send an non-acknowledge bit (AK = 1)
after receiving the data, the A8603 will continue sending data
from the sequential registers after the addressed one, as shown in
figure A-3. After the master provides an non-acknowledge bit, the
A8603 will stop sending the data. After that, if additional register
reads are required, the process must start over again.
Allegro MicroSystems
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A-3
Multiple-Output Regulator
for Automotive LCD Displays
A8603
Start
Condition
Write
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
0
Slave
Acknowledge
0
Register Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Slave
Acknowledge
0
Master Restart
A0 R/W AK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 AK
7
8
9
1
2
3
4
5
6
7
8
Read
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
1
9
Slave
Acknowledge
0
A0 R/W AK
7
8
9
Register Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Master
Non-Acknowledge
1
D7
D6
D5
D4
D3
D2
D1
D0
AK
1
2
3
4
5
6
7
8
9
Stop
Condition
Read from a single register
Read from multiple registers continuously
Start
Condition
Write
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
0
Slave
Acknowledge
0
Register Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Slave
Acknowledge
0
Master Restart
A0 R/W AK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 AK
7
8
9
1
2
3
4
5
6
7
8
Read
Slave Device Address
0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
A6
A5
A4
A3
A2
A1
SCL
1
2
3
4
5
6
1
9
Slave
Acknowledge
0
A0 R/W AK
7
8
9
Register Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Master
Acknowledge
0
D7
D6
D5
D4
D3
D2
D1
D0
AK
1
2
3
4
5
6
7
8
9
Master
Acknowledge
Register N+1 Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
SDA
D7
D6
D5
D4
D3
D2
D1
SCL
1
2
3
4
5
6
7
0
D0 AK
[Wraps to Register N+1]
8
Register N+n Data
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
[Wraps to Register N+n]
Figure A-4. Reading from single and to multiple registers
SDA
D7
D6
D5
D4
D3
D2
D1
SCL
1
2
3
4
5
6
7
9
Master
Non-Acknowledge
Stop
1
Condition
D0 AK
8
9
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A-4
Multiple-Output Regulator
for Automotive LCD Displays
A8603
I2C-Compatible Interface Timing Diagram
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
SDA
tLOW
SCL
tHIGH
1
2
3
4
5
6
7
1. Start
2. SDA can change state only when SCL = low
3. SDA must be stable before SCL goes high
4, 5. SCL and SDA output fall time < 250 ns
6. Stop
7. Restart
I2C-Compatible Timing Requirements
Characteristics
Symbol
Min.
Typ.
Max.
Units
tBUF
1.3
–
–
µs
Hold Time Start Condition
tHD:STA
0.6
–
–
µs
Setup Time for Start Condition
tSU:STA
0.6
–
–
µs
SCL Low Time
tLOW
1.3
–
–
µs
SCL High Time
tHIGH
0.6
–
–
µs
Data Setup Time
tSU:DAT
100
–
–
ns
Data Hold Time*
tHD:DAT
0
–
900
ns
Setup Time for Stop Condition
tSU:STO
0.6
–
–
µs
tOF
–
–
250
ns
Bus Free Time Between Stop/Start
Output Fall Time from VSCL(H) to VSCL(L)
*For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA
signal in order to bridge the undefined region of the SCL signal falling edge.
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