ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
DESCRIPTION
FEATURES AND BENEFITS
• Accurate power monitoring for AC and DC applications
• UL 60950-1 (ed. 2) and UL 62368-1 (ed. 1) certified for
reinforced isolation up to 517 VRMS in a single package
• Accurate measurements of active, reactive, and apparent
power, as well as power factor
• Separate RMS and instantaneous measurements for both
voltage and current channels
• Two programmable averaging blocks
• 0.85 mΩ primary conductor resistance for low power loss
and high inrush current withstand capability
• Compatible with floating and non-floating GND
• Dedicated voltage or current zero crossing pin
• Fast, user-programmable overcurrent fault pin (5 µs typ.)
• User-programmable undervoltage and overvoltage RMS
thresholds
• 1 kHz bandwidth
• Current sensing range up to 90 A
• Options for I2C or SPI digital interface protocols
PACKAGE
16-pin SOICW (suffix MA)
1 MΩ
1 MΩ
1 MΩ
1 MΩ
1
2
3
4
5
6
7
CB Certificate Number:
US-32210-M1-UL
US-36315-UL
The ACS37800 power monitoring IC offers key power
measurement parameters that can easily be accessed through its
SPI or I2C digital protocol interfaces. Dedicated and configurable
I/O pins for voltage/current zero crossing, undervoltage and
overvoltage reporting, and fast overcurrent fault detection are
available in I2C mode. User configuration of the IC is available
through on-chip EEPROM.
REINFORCED
ISOLATION
N (L)
IP
Allegro’s Hall-effect-based, galvanically isolated current sensing
technology achieves reinforced isolation ratings (4800 VRMS)
in a small PCB footprint. These features enable isolated current
sensing without expensive Rogowski coils, oversized current
transformers, isolated operational amplifiers, or the power
loss of shunt resistors.
The ACS37800 is provided in a small low-profile surface
mount SOIC16 wide-body package, is lead (Pb) free, and is fully
calibrated prior to shipment from the Allegro factory. Customer
calibration can further increase accuracy in application.
Not to scale
L (N)
The Allegro ACS37800 power monitoring IC greatly simplifies
the addition of power monitoring to many AC or DC powered
systems. The sensor may be powered from the same supply as
the system’s MCU, eliminating the need for multiple power
supplies. The device’s construction includes a copper conduction
path that generates a magnetic field proportional to applied
current. The magnetic field is sensed differentially to reject
errors introduced by common mode fields.
8
MCU
RSENSE
GND
IP+ ACS37800 VINP
IP+
VINN
IP+
GND
IP+
VCC
IP-
SDA / MISO
IP-
SCL / SCLK
IP-
DIO_0 / MOSI
IP-
DIO_1 / CS
Single Output
Isolated Power
Supply
(Flyback, etc.)
16
VCC
I2C
Only
15
14
RPULLUP
To User
13
12
RPULLUP
11
10
9
Linear
Regulator
Figure 1: Typical Application
ACS37800-DS, Rev. 2
MCO-0001004
February 24, 2021
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
SELECTION GUIDE
Part Number
VCC(typ) (V)
IPR (A)
ACS37800KMACTR-015B5-SPI
5
±15
ACS37800KMACTR-030B3-SPI
3.3
±30
ACS37800KMACTR-030B3-I2C
3.3
±30
ACS37800KMACTR-090B3-I2C
3.3
±90
[1] Contact Allegro
Communication
Protocol
TA (°C)
Packing [1]
–40 to 125
Tape and reel,
1000 pieces per reel,
3000 pieces per box
SPI
I2C
for additional packing options.
ACS
37800 K MAC TR - 015 B
5 - SPI
Communication Protocol
Supply Voltage:
5 – VCC = 5 V
3 – VCC = 3.3 V
Output Directionality:
B – Bidirectional
Current Sensing Range (A)
Packing Designator
Package Designator
Operating Temperature Range
5 Digit Part Number
Allegro Current Sensor
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Notes
Rating
Units
Supply Voltage
VCC
6.5
V
Reverse Supply Voltage
VRCC
–0.5
V
Input Voltage
VINP, VINN
VCC + 0.5
V
Reverse Input Voltage
VRNP, VRNN
–0.5
V
6
V
–0.5
V
Digital I/O Voltage
VDIO
Reverse Digital I/O Voltage
VRDIO
Maximum Continuous Current
ICMAX
TA = 25°C
60
A
TA
Range K
–40 to 125
°C
Operating Ambient Temperature
SPI, I2C, and general purpose I/O
Junction Temperature
TJ(max)
165
°C
Storage Temperature
Tstg
–65 to 170
°C
ISOLATION CHARACTERISTICS
Characteristic
Symbol
Dielectric Strength Test Voltage
VISO
Notes
Agency type-tested for 60 seconds per UL 60950-1
(edition 2) and UL 62368-1 (edition 1); Production tested
at 3000 VRMS for 1 second, in accordance with UL 60950-1
(edition 2) and UL 62368-1 (edition 1)
Working Voltage for Basic Isolation
VWVBI
Maximum approved working voltage for basic (single) isolation
according to UL 60950-1 (edition 2) and UL 62368-1 (edition 1)
Working Voltage for Reinforced Isolation
VWVRI
Maximum approved working voltage for reinforced isolation
according to UL 60950-1 (edition 2) and UL 62368-1 (edition 1)
Clearance
Rating
Unit
4800
VRMS
1480
VPK or VDC
1047
VRMS
730
VPK or VDC
517
VRMS
Dcl
Minimum distance through air from IP leads to signal leads
7.5
mm
Creepage
Dcr
Minimum distance along package body from IP leads to signal
leads
7.9
mm
Distance Through Insulation
DTI
Minimum internal distance through insulation
90
μm
Comparative Tracking Index
CTI
Material Group II
400 to 599
V
ESD RATINGS
Value
Unit
Human Body Model
Characteristic
Symbol
VHBM
Per JEDEC JS-001
Notes
±5
kV
Charged Device Model
VCDM
Per JEDEC JS-002
±1
kV
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions [1]
Value
Units
Package Thermal Resistance
(Junction to Ambient)
RθJA
Mounted on the Allegro ASEK37800 evaluation board with 750
of 4
oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4,
with thermal vias connecting the layers. Performance values include the
power consumed by the PCB.
23
°C/W
Package Thermal Resistance
(Junction to Lead)
RθJL
Mounted on the Allegro ACS37800 evaluation board.
5
°C/W
[1]
mm2
Refer to the Thermal Performance section below.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
FUNCTIONAL BLOCK DIAGRAM
VCC
DIGITAL SYSTEM
Bandgap
Reference
Temperature
Compensation
Logic
Temperature
Sensor
To All
Subcircuits
VINP
ADC
VINN
ADC
IP+
SCL / SCLK
DIO_0 / MOSI
EEPROM +
Charge Pump
V
I
SDA / MISO
I2C/SPI
Communication
Metrology
Engine
DIO_1 / CS
Fault Logic
Hall Sensor Array
GND
IP–
Figure 2: Functional Block Diagram
PINOUT DIAGRAM AND TERMINAL LIST
Terminal List Table
IP+ 1
16 VINP
IP+ 2
15 VINN
IP+ 3
14 GND
IP+ 4
13 VCC
IP-
5
12 SDA / MISO
IP-
6
11 SCL / SCLK
IP-
7
10 DIO_0 / MOSI
IP-
8
9
Pinout Diagram
DIO_1 / CS
Description
Number
Name
1, 2, 3, 4
IP+
Terminals for current being sensed; fused internally
5, 6, 7, 8
IP-
Terminals for current being sensed; fused internally
9
DIO_1 / CS
Digital I/O 1
10
DIO_0 / MOSI
Digital I/O 0
MOSI
11
SCL / SCLK
SCL
SCLK
12
SDA / MISO
SDA
MISO
13
VCC
Device power supply terminal
14
GND
Device ground terminal
15
VINN
Negative input voltage (always connect to GND)
16
VINP
Positive input voltage
I2C
SPI
Chip Select (CS)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Table of Contents
Features and Benefits............................................................ 1
Description........................................................................... 1
Package.............................................................................. 1
Typical Application................................................................. 1
Selection Guide.................................................................... 2
Absolute Maximum Ratings.................................................... 3
Isolation Characteristics......................................................... 3
ESD Ratings......................................................................... 3
Thermal Characteristics......................................................... 3
Functional Block Diagram...................................................... 4
Pinout Diagram and Terminal List............................................ 4
Electrical Characteristics........................................................ 6
15B5 Performance Characteristics.......................................... 8
30B3 Performance Characteristics.......................................... 9
90B3 Performance Characteristics........................................ 10
I2C Operating Characteristics................................................11
SPI Operating Characteristics............................................... 12
Theory of Operation............................................................ 13
Introduction..................................................................... 13
Voltage and Current Measurements................................... 13
Overcurrent Measurement Path......................................... 13
Trim Methods.................................................................. 13
Power Calculations.......................................................... 14
Operational Block Diagram................................................... 15
Configurable Settings....................................................... 16
Configuring the DIO Pins (I2C Devices) ............................. 16
Configuring the Device for AC Applications............................. 19
Device EEPROM Settings................................................. 19
Voltage Measurement....................................................... 19
Current Measurement....................................................... 20
Configuring the Device for DC Applications............................ 21
Device EEPROM Settings................................................. 21
Voltage Measurement....................................................... 21
Current Measurement....................................................... 21
RMS and Power Accuracy vs. Operation Point........................ 21
RMS and Power Output Error vs. Applied Input.................... 21
15B5 IRMS and Power Error ............................................ 22
30B3 IRMS and Power Error ............................................ 22
90B3 IRMS and Power Error ............................................ 22
Digital Communication......................................................... 23
Communication Interfaces................................................. 23
SPI................................................................................. 23
Registers and EEPROM................................................... 23
EEPROM Error Checking and Correction (ECC).................. 25
I2C Slave Addressing........................................................ 25
EEPROM/Shadow Memory Map........................................... 26
Register Details – EEPROM.............................................. 27
Volatile Memory Map........................................................ 32
Register Details – Volatile................................................. 33
Application Information........................................................ 38
Thermal Rise vs. Primary Current...................................... 38
ASEK37800 Evaluation Board Layout................................. 38
Recommended PCB Layout................................................. 39
Package Outline Drawing..................................................... 40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
COMMON ELECTRICAL CHARACTERISTICS [1]: Valid through the full range of TA and VCC = VCC(typ), unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
5 V variant
4.5
5
5.5
V
3.3 V variant
2.97
3.3
3.63
V
–
12
15
mA
0.1
–
–
µF
–
90
–
µs
–250
–
250
mV
35
–
300
Hz
ELECTRICAL CHARACTERISTICS
Supply Voltage
Supply Current
Supply Bypass Capacitor
Power-On Time
VCC
ICC
CBYPASS
VCC(min) ≤ VCC ≤ VCC(max), no load on
output pins
VCC to GND recommended
tPO
VOLTAGE INPUT BUFFER
Differential Input Range
ΔVINR
ΔVIN = VINP – VINN(GND)
Dynamic Input Frequency
fdyn_in
bypass_n_en = 0
VOLTAGE CHANNEL ADC
Sample Frequency
fS_V
–
32
–
kHz
Number of Bits
ADCV_B
–
16
–
bits
ADC Fullscale
ADCV_FS
ΔVIN = ±250 mV, VINN= GND
–27500
–
27500
codes
Sens(V)
ΔVINR(min) < ΔVIN < ΔVINR(max)
–
110
–
LSB / mV
PSEV_O
Ratio of change on VCC to change in
offset at DC, 100% ±10% VCC(typ)
–7
–
7
codes /
%VCC
PSEV_S
Ratio of change on VCC to change in
sensitivity at DC, 100% ±10% VCC(typ)
–0.1
–
0.1
% / %VCC
PSRRV_O
Ratio of change on VCC to change in
offset, 10 Hz to 10 kHz, 10% VCC(pk-pk)
60
70
–
dB
PSRRV_S
Ratio of change on VCC to change in
sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk)
60
75
–
dB
–
1
–
kHz
–
±0.3
–
mV
–
±0.2
–
%
kHz
Sensitivity
Voltage Channel Power Supply Error
Voltage Channel Power Supply Rejection
Ratio
VOLTAGE CHANNEL
Internal Bandwidth
BW
RMS Noise
NV
Linearity Error
Input referred
ELIN_V
CURRENT CHANNEL
Sample Frequency
fS_C
–
32
–
Number of Bits
ADCI_B
–
16
–
bits
ADC Fullscale
ADCI_FS
IP = IPR(min) or IPR(max)
–27500
–
27500
codes
PSEI_O
Ratio of change on VCC to change in
offset at DC, 100% ±10% VCC(typ)
–60
–
60
codes /
%VCC
PSEI_S
Ratio of change on VCC to change in
sensitivity at DC, 100% ±10% VCC(typ)
–0.3
–
0.3
% / %VCC
PSRRI_O
Ratio of change on VCC to change in
offset, 10 Hz to 10 kHz, 10% VCC(pk-pk)
60
65
–
dB
PSRRI_S
Ratio of change on VCC to change in
sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk)
20
40
–
dB
–
1
–
kHz
–
0.85
–
mΩ
Current Channel Power Supply Error
Current Channel Power Supply Rejection
Ratio
Internal Bandwidth
BW
Primary Conductor Resistance
RIP
TA = 25°C
Continued on next page...
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
COMMON ELECTRICAL CHARACTERISTICS [1] (continued): Valid through the full range of TA and VCC = VCC(typ),
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
CURRENT CHANNEL (continued)
RMS Noise
Linearity Error
NI
Input referred
ELIN_I
–
±0.1
–
A
–
±1.5
–
%
–
5
–
μs
–
200
–
kHz
OVERCURRENT FAULT CHARACTERISTICS
Fault Response Time
tRF
Internal Bandwidth
BW
Fault
Hysteresis [2]
Fault Range
Time from IP rising above IFAULT until
VFAULT < VFAULT(max) for a current
step from 0 to 1.2 × IFAULT; 10 kΩ and
100 pF from DIO_1 to ground;
fltdly = 0
IHYST
IFAULT
Set using fault field in EEPROM
–
0.06 × FS
–
A
0.65 × FS
–
2.00 × FS
A
–
250
–
µs
VOLTAGE ZERO CROSSING
Voltage Zero-Crossing Delay
td
DIO PINS
DIO Output High Level
VOH(DIO)
VCC = 3.3 V
3
–
–
V
DIO Output Low Level
VOL(DIO)
VCC = 3.3 V
–
–
0.3
V
DIO Input Voltage for Address Selection 0
VADD0
VCC = 3.3 V
–
0
–
V
DIO Input Voltage for Address Selection 1
VADD1
VCC = 3.3 V
–
1.1
–
V
DIO Input Voltage for Address Selection 2
VADD2
VCC = 3.3 V
–
2.2
–
V
DIO Input Voltage for Address Selection 3
VADD3
VCC = 3.3 V
–
3.3
–
V
[1]
Device may be operated at higher primary current levels (IP), ambient temperatures (TA), and internal leadframe temperatures, provided that the maximum junction
temperature (TJ(max)) is not exceeded.
IP goes above IFAULT, tripping the internal fault comparator, IP must go below IFAULT – IHYST before the internal fault comparator will reset.
[2] After
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800KMAC-015B5 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range,
TA = –40°C to 125°C, CBYPASS = 0.1 µF, and VCC = 5 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
–
5
–
V
–15
–
15
A
–
1833.3
–
LSB/A
GENERAL CHARACTERISTICS
Nominal Supply Voltage
VCC(typ)
NOMINAL PERFORMANCE – FACTORY CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
Sens(I)
IPR(min) < IP < IPR(max)
NOMINAL PERFORMANCE – INPUT REFERRED FACTORY POWER (POWER SEEN BY THE DEVICE) [2]
Active Power Sensitivity
SensPd_act
–
6.15
–
LSB/mW
Imaginary Power Sensitivity
SensPd_img
–
12.31
–
LSB/mVAR
Apparent Power Sensitivity
SensPd_app
–
12.31
–
LSB/mVA
Measured at IP = IPR(max), TA = 25°C to 125°C
–
±1.1
–
%
Measured at IP = IPR(max), TA = –40°C to 25°C
–
±1.5
–
%
IP = 0 A, TA = 25°C to 125°C
–
±720
–
LSB
IP = 0 A, TA = –40°C to 25°C
–
±780
–
LSB
Measured at IP = IPR(max), TA = 25°C to 125°C
–
±2.1
–
%
Measured at IP = IPR(max), TA = –40°C to 25°C
–
±2.7
–
%
Measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±1.2
–
%
Measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±1.2
–
%
ΔVIN = 0 mV, TA = 25°C to 125°C
–
±55
–
LSB
ΔVIN = 0 mV, TA = –40°C to 25°C
–
±55
–
LSB
Measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±1.4
–
%
Measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±1.4
–
%
IP = IPR(max), measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±2.1
–
%
IP = IPR(max), measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±3
–
%
TOTAL OUTPUT ERROR COMPONENTS [3] – CURRENT CHANNEL
Sensitivity Error
Offset Error
Total Output Error
ESENS(I)
EO(I)
ETOT(I)
TOTAL OUTPUT ERROR COMPONENTS [3] – VOLTAGE CHANNEL
Sensitivity Error
Offset Error
Total Output Error
ESENS(V)
EO(V)
ETOT(V)
ACCURACY PERFORMANCE – ACTIVE POWER
Total Output Error
ETOT(P)
Typical values are mean ±3 sigma.
sensitivity characteristics are referred to the inputs seen by the device, i.e. the voltage channel resistor divider must be accounted to determine the system sensitivies.
[3] E
TOT = ESENS + 100 x VOE/(Sens x IP)
[1]
[2] These
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800KMAC-030B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range,
TA = –40°C to 125°C, CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
–
3.3
–
V
–30
–
30
A
–
916.7
–
LSB/A
GENERAL CHARACTERISTICS
Nominal Supply Voltage
VCC(typ)
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
Sens(I)
IPR(min) < IP < IPR(max)
NOMINAL PERFORMANCE – INPUT REFERRED FACTORY POWER (POWER SEEN BY THE DEVICE) [2]
Active Power Sensitivity
SensPd_act
–
3.08
–
LSB/mW
Imaginary Power Sensitivity
SensPd_img
–
6.15
–
LSB/mVAR
Apparent Power Sensitivity
SensPd_app
–
6.15
–
LSB/mVA
TOTAL OUTPUT ERROR COMPONENTS [3] – CURRENT CHANNEL
Sensitivity Error
Offset Error
Total Output Error
ESENS(I)
EO(I)
ETOT(I)
Measured at IP = IPR(max), TA = 25°C to 125°C
–
±1
–
%
Measured at IP = IPR(max), TA = –40°C to 25°C
–
±1.5
–
%
IP = 0 A, TA = 25°C to 125°C
–
±510
–
LSB
IP = 0 A, TA = –40°C to 25°C
–
±570
–
LSB
Measured at IP = IPR(max), TA = 25°C to 125°C
–
±2
–
%
Measured at IP = IPR(max), TA = –40°C to 25°C
–
±2.7
–
%
Measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±0.75
–
%
Measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±0.75
–
%
ΔVIN = 0 mV, TA = 25°C to 125°C
–
±55
–
LSB
ΔVIN = 0 mV, TA = –40°C to 25°C
–
±55
–
LSB
Measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±1
–
%
Measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±1
–
%
IP = IPR(max), measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±2.1
–
%
IP = IPR(max), measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±3
–
%
TOTAL OUTPUT ERROR COMPONENTS [3] – VOLTAGE CHANNEL
Sensitivity Error
Offset Error
Total Output Error
ESENS(V)
EO(V)
ETOT(V)
ACCURACY PERFORMANCE – ACTIVE POWER
Total Output Error
ETOT(P)
Typical values are mean ±3 sigma.
sensitivity characteristics are referred to the inputs seen by the device, i.e. the voltage channel resistor divider must be accounted to determine the system sensitivies.
[3] E
TOT = ESENS + 100 x VOE/(Sens x IP)
[1]
[2] These
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800KMAC-090B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range,
TA = –40°C to 125°C, CBYPASS = 0.1 µF, and VCC = 3.3 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
–
3.3
–
V
–90
–
90
A
–
305.6
–
LSB/A
GENERAL CHARACTERISTICS
Nominal Supply Voltage
VCC(typ)
NOMINAL PERFORMANCE – CURRENT CHANNEL
Current Sensing Range
Sensitivity
IPR
Sens(I)
IPR(min) < IP < IPR(max)
NOMINAL PERFORMANCE – INPUT REFERRED FACTORY POWER (POWER SEEN BY THE DEVICE) [2]
Active Power Sensitivity
SensPd_act
–
1.03
–
LSB/mW
Imaginary Power Sensitivity
SensPd_img
–
2.05
–
LSB/mVAR
Apparent Power Sensitivity
SensPd_app
–
2.05
–
LSB/mVA
TOTAL OUTPUT ERROR COMPONENTS [3] – CURRENT CHANNEL
Sensitivity Error
Offset Error
Total Output Error
ESENS(I)
EO(I)
ETOT(I)
TOTAL OUTPUT ERROR COMPONENTS
Sensitivity Error
Offset Error
Total Output Error
[3] –
Measured at IP = IPR(max), TA = 25°C to 125°C
–
±1
–
%
Measured at IP = IPR(max), TA = –40°C to 25°C
–
±1.5
–
%
IP = 0 A, TA = 25°C to 125°C
–
±180
–
LSB
IP = 0 A, TA = –40°C to 25°C
–
±210
–
LSB
Measured at IP = 45 A, TA = 25°C to 125°C
–
±2
–
%
Measured at IP = 45 A, TA = –40°C to 25°C
–
±2.6
–
%
Measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±0.75
–
%
Measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±0.75
–
%
ΔVIN = 0 mV, TA = 25°C to 125°C
–
±55
–
LSB
ΔVIN = 0 mV, TA = –40°C to 25°C
–
±55
–
LSB
Measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±1
–
%
Measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±1
–
%
IP = 45 A, measured at ΔVIN = ΔVINR(max),
TA = 25°C to 125°C
–
±1.3
–
%
IP = 45 A, measured at ΔVIN = ΔVINR(max),
TA = –40°C to 25°C
–
±2.1
–
%
VOLTAGE CHANNEL
ESENS(V)
EO(V)
ETOT(V)
ACCURACY PERFORMANCE – ACTIVE POWER
Total Output Error
ETOT(P)
Typical values are mean ±3 sigma.
sensitivity characteristics are referred to the inputs seen by the device, i.e. the voltage channel resistor divider must be accounted to determine the system sensitivies.
[3] E
TOT = ESENS + 100 x VOE/(Sens x IP)
[1]
[2] These
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10
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
xKMACTR-I2C OPERATING CHARACTERISTICS [1]: Valid through the full range of TA, VCC = VCC(typ), REXT = 10 kΩ,
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
I2C INTERFACE CHARACTERISTICS [2]
Bus Free Time Between Stop and Start
tBUF
1.3
–
–
µs
Hold Time Start Condition
thdSTA
0.6
–
–
µs
Setup Time for Repeated Start Condition
tsuSTA
0.6
–
–
µs
SCL Low Time
tLOW
1.3
–
–
µs
SCL High Time
tHIGH
0.6
–
–
µs
Data Setup Time
tsuDAT
100
–
–
µs
Data Hold Time
thdDAT
0
–
900
µs
Setup Time for Stop Condition
tsuSTO
0.6
–
–
µs
Logic Input Low Level (SDA, SCL pins)
VIL
–
–
30
%VCC
Logic Input High Level (SDA, SCL pins)
VIH
70
Logic Input Current
IIN
Output Low Voltage (SDA)
VOL
Clock Frequency (SCL pin)
fCLK
Output Fall Time (SDA pin)
tf
I2C Pull-Up Resistance
Total Capacitive Load for Each of SDA and
SCL Buses
[1]
[2]
–
–
%VCC
Input voltage on SDA or SCL = 0 V to VCC
–1
–
1
µA
SDA sinking = 1.5 mA
–
–
0.36
V
kHz
–
–
400
–
–
250
ns
REXT
2.4
10
–
kΩ
CB
–
–
20
pF
REXT = 2.4 kΩ, CB = 100 pF
Validated by characterization and design.
These values are ratiometric to the supply voltage. I2C Interface Characteristics are ensured by design and not factory tested.
tsuSTA
tsuDAT
thdSTA
thdDAT
tsuSTO
tBUF
SDA
SCL
tLOW
tHIGH
Figure 3: I2C Interface Timing
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11
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
xKMATR-SPI OPERATING CHARACTERISTICS [1]: Valid through the full range of TA, VCC = VCC(typ), unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
2.8
–
3.63
V
MOSI, SCLK, CS pins, VCC = 5 V
4
–
5.5
V
MOSI, SCLK, CS pins
–
–
0.5
V
MISO pin, CL = 20 pF, TA = 25°C,
VCC(typ) = 3.3 V
2.8
3.3
3.8
V
MISO pin, CL = 20 pF, TA = 25°C,
VCC(typ) = 5 V
4
5
5.5
V
–
0.3
0.5
V
0.1
–
10
MHz
5.8
–
588
kHz
SPI INTERFACE CHARACTERISTICS
Digital Input High Voltage
VIH
Digital Input Low Voltage
VIL
SPI Output High Voltage
MOSI, SCLK, CS pins, VCC = 3.3 V
VOH
SPI Output Low Voltage
VOL
MISO pin, CL = 20 pF, TA = 25°C
SPI Clock Frequency
fSCLK
MISO pin, CL = 20 pF
SPI Frame Rate
tSPI
Chip Select to First SCLK Edge
tCS
Time from CS going low to SCLK falling
edge
50
–
–
ns
Data Output Valid Time
tDAV
Data output valid after SCLK falling edge
–
40
–
ns
MOSI Setup Time
tSU
Input setup time before SCLK rising edge
25
–
–
ns
MOSI Hold Time
tHD
Input hold time after SCLK rising edge
50
–
–
ns
SCLK to CS Hold Time
tCHD
Hold SCLK high time before CS rising
edge
5
–
–
ns
Loading on digital output (MISO) pin
–
–
20
pF
Load Capacitance
[1]
CL
Validated by characterization and design.
tCHD
tCS
>tCS
CSN
SCLK
tSU
tHD
MOSI
tDAV
MISO
Figure 4: SPI Timing
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12
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
THEORY OF OPERATION
Introduction
current and voltage measurements are stored in the icodes and
vcodes fields. The instantaneous apparent power, which is the
product of icodes and vcodes, is stored in the field pinstant.
The ACS37800 provides a simple solution for voltage, current,
and power monitoring in 60 Hz AC and DC applications and is
particularly well suited for high isolation. The voltage is measured by resistor dividing it down to fit the input range of the
on-board voltage sense amplifier, as well as to add isolation.
The current is measured using the integrated current loop and
galvanically isolated Hall sensor. Both analog signals are then
sampled using high accuracy ADCs before entering the digital
system. Here, the metrology engine is used to determine frequency, calculate RMS values of current, voltage, and power, as
well as provide a range of averaging and configuration options.
One can choose to read out all the different information provided
using SPI or I2C. When using I2C, there are also options for
using some of the digital I/O pins for overcurrent or zero crossing detection. Overall, with a high degree of configurability and
integrated features, the ACS37800 can fit most power monitoring
applications. The following sections will help explain in more
detail these features and configuration options, as well as how to
best use the ACS37800 for particular applications.
Overcurrent Measurement Path
A separate filter on the current ADC is used to create a lower
resolution but higher bandwidth sample rate measurement of the
current to be used for overcurrent detection. This filter outputs a
12-bit word at a 1 MHz update rate and 200 kHz bandwidth. The
overcurrent fault logic compares this auxiliary current value to the
user-defined overcurrent fault threshold, defined by the field fault.
It is important to note that the trim for the main 16-bit current path
is also applied to the overcurrent path, such that the overcurrent
fault has the same level of accuracy as the main signal path.
Trim Methods
The trim logic for the voltage and current channels is depicted in
Figure 5 and Figure 6. Refer to the Register Details section for
more information regarding trim fields. In general, each channel, voltage and current, is trimmed for gain and offset both at
room and over temperature. This trim is done before the icodes
and vcodes registers. The user has the ability to trim the nominal
room temperature value.
Voltage and Current Measurements
The main signal paths for the current and voltage measurement,
through the ADCs and internal filtering, have a bandwidth of
1 kHz and an update rate of 32 kHz. These “instantaneous”
Gain Trim
Delay
Offset Trim
adc_out_v
Z
VchanGainSel
Satura�on
-x
ichan_del_en
+
+
vcodes
vchan_offset_code
+
chan_del_sel
+
vqvo_tc
Factory
Trim
Figure 5: Voltage Channel Trim Flow
Delay
Offset Trim
adc_out_i
Gain Trim
Z-x
+
Satura�on
+
icodes
ichan_del_en
qvo_fine
ch an_del_sel
qvo_tc
+
+
sns_fine
sns_tc
Factory
Trim
Figure 6: Current Channel Trim Flow
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13
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Power Calculations
POWER FACTOR
VOLTAGE ZERO CROSSING
The magnitude of the ratio of the real power to apparent power,
calculated at the end of each cycle is:
Voltage zero crossings are detected with time-based hysteresis
that removes the possibility of noise causing multiple zero crossings to be reported at each true zero crossing.
I RMS AND V RMS
The cycle-by-cycle calculation of the root mean square of both
the current and voltage channels is:
IRMS =
∑ nn == N0 – 1 In2
N
VRMS =
∑ nn == N0 – 1 Vn2
N
where In (icodes) and Vn (vcodes) are the instantaneous measurements of current and voltage, respectively.
|PF| =
PACTIVE
|S|
LEADING OR LAGGING POWER FACTOR
The current leading or lagging the voltage is communicated as a
single bit, posangle. This bit represents the sign of the reactive
power. The sign of the reactive power is determined by comparing the timing of the zero crossings of the current and voltage. As
such, it is only meaningful in the case of a linear load.
The sign of the reactive power, posangle, along with the sign of
the power factor, pospf, can be used to determine whether the
load is inductive or capacitive, as well as whether power is being
generated or consumed. This is shown in the four-quadrant figure
below (refer to Figure 7).
Imaginary
The RMS and power calculations of the ACS37800 are calculated over a window of N samples. By default, this window is
calculated dynamically based on the zero crossings of the voltage
signal. A rising voltage zero crossing triggers the start of a new
window. N then increases with each 32 kHz sample until the next
rising voltage zero crossing, recording the current and voltage
readings at each sample. This ends the calculation window, and
all RMS and power calculations are performed on the saved data.
During this time, the next calculation window is started.
POSPF = 0
POSANG = 0
POSPF = 1
POSANG = 1
Capacitive and
Generating
Inductive and
Consuming
Lagging
Real
APPARENT POWER
Leading
The magnitude of the complex power being measured; calculated
at the end of each cycle is:
|S| = IRMS × VRMS
POSPF = 0
POSANG = 1
POSPF = 1
POSANG = 0
Inductive and
Generating
Capacitive and
Consuming
ACTIVE POWER
∑ nn == N0 – 1 Pn
PACTIVE =
N
Figure 7: Four Quadrant, Power Factor
Pn = In × Vn
REACTIVE POWER
The imaginary component of power being measured, calculated
at the end of each cycle is:
Q=
S2 – PACTIVE2
p
Ap
nt
e
ar
,S
er
I
=V
w
Po
S=
P2+Q2
Ф
Reactive Power, Q = VI sinФ
The real component of power being measured, calculated cycle
by cycle is:
Active Power, P = VI cosФ
Figure 8: Power Triangle
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955 Perimeter Road
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14
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
OPERATIONAL BLOCK DIAGRAM
Voltage and
Current
Measurement
Factory Trimmed
VLINE
RSENSE
Voltage
ADC
ΣRISO + RSENSE
Digital
Filter
vcodes
Channel
Delay
Control
Temperature
Compensation
icodes
IP+
IP–
Overcurrent
Fault
Comparator
Current
ADC
fault out
fault
RMS, and Power
Calculation
Voltage Zero
Crossing
Zero
Crossing
Flag
vrms
vcodes
irms
X
icodes
RMS
and
Power
Calculations
pinstant
pospf
posangle
papparent
pactive
pimag
Averaging and
VRMS Flagging
ovrms
O/UVRMS
Flag
vrms
uvrms
0
irms
vrmsavgonesec
1
vrmsavgonemin
iavgselen
Averaging
0
pactive
1
irmsavgonesec
irmsavgonemin
pavgselen
Register
Voltage data
Current data
pactiveavgonesec
pactiveavgonemin
Output
Operation
FAULT data
Power data
Control
Figure 9: Operational Block Diagram
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955 Perimeter Road
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15
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Configurable Settings
PHASE DELAY
Phase delay may be introduced on either the voltage or current
channel to account for known phase delay at other points in the
system using the ichan_del_en and chan_ del_sel fields. ichan_
del_en determines if the voltage channel or current channel will
be delayed. The chosen channel will be delayed by the configured
amount in chan_del_sel, up to 5° of delay.
AVERAGING CHANNEL
The ACS37800 contains two averaging paths. VRMS, IRMS, and
PACTIVE can be routed to these average blocks as shown in Figure 9
using iavgselen and pavgselen.
AVERAGING TIME
Each averaging path on the ACS37800 consists of two averaging blocks that each allow for a configurable number of averages
based on the EEPROM fields rms_avg_1 and rms_avg_2.
The output of the first averaging block feeds into the input of the
second averaging block. The output of each block is accessible
for each channel.
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
FOR VRMS
This device has programmable overvoltage and undervoltage
RMS flags that will signal when the vrms is above or below the
respective thresholds. The vrms is compared to the overvoltage
and undervoltage RMS thresholds set by the fields overvreg and
undervreg to determine a flag condition. The number of successive sample sets required to trigger either the overvoltage or
undervoltage RMS flag can be set by the vevent_cycs field.
When bypass_n_en = 1, it is important to define the number of
samples used to calculate RMS. This can be done in the field
n. The field n is the number of 32 kHz samples that are used to
calculate the RMS. The minimum effective n that is used when
calculating RMS is 4. If a value of less than 4 is chosen for n,
then 4 is internally used. The first useable RMS calculation on
start up with bypass_n_en = 1 is after 2 × n samples.
Configuring the DIO Pins (I2C Devices)
FLAGS TO BE ROUTED TO THE DIO PINS
When the device is configured to be in I2C mode (comm_sel in
EEPROM = 1), pins 9 and 10 become digital I/O pins, DIO_1
and DIO_0, respectively. The digital I/O pins are low true, meaning that a voltage below the DIO Output Low Level maximum
(VOL(DIO)max) is to be interpreted as logic 1 and a voltage above
DIO Output High Level minimum (VOH(DIO)min) is to be interpreted as a logic 0. The Digital I/O pins can be configured in
EEPROM to represent the following functions:
DIO_O
dio_0_sel value (EEPROM)
0
ZC: zero crossing
1
ovrms: the VRMS overvoltage flag
2
uvrms: The VRMS undervoltage flag
3
The OR of ovrms and uvrms (if either flag is
triggered, the DIO_0 pin will be asserted)
ZC
The overcurrent fault threshold may be set from 0.65 × IPR to
2.0 × IPR. The user sets the trip point with the field fault. The
user can add a digital delay to the overcurrent fault with the field
flt_dly. Up to 32 µs delay can be added to the overcurrent fault.
DIO_0_Sel[0..1]
OCF
UVRMS
OVRMS
OCF_LAT
dio_1_sel value (EEPROM)
0
1
OVRMS
UVRMS
DIO_0 / MOSI
MOSI
UVRMS
BYPASSING THE DYNAMIC FRAMING OF THE RMS
CALCULATION WINDOW
By default, the ACS37800 dynamically calculates the value of
N to be used in the RMS and power calculations based on the
zero crossings on the voltage channel. This functionality can be
disabled using the bypass_n_en field.
DIO_0
OVRMS
The ovrms and uvrms flags can be routed to the DIO pins when
the device is used in I2C mode. See Configuring the DIO Pins.
OVERCURRRENT DETECTION FOR INSTANTANEOUS CURRENT
Function
2
3
Comm_Sel
DIO_1DIO_1
Function
DIO_1 / CS
CS
OCF: Overcurrent fault
DIO_1_Sel[0..1]
Comm_Sel
uvrms: The VRMS undervoltage flag
ZC
DIO_0
ovrms: The VRMS overvoltage flag
MOSI
DIO_0 / MOSI
The OR of ovrms and uvrms, and OCF_LAT [Latched
Overcurrent Fault] (if any of the three flags are
DIO_0_Sel[0..1]
Comm_Sel
triggered, the DIO_1 pin will be asserted)
OCF
DIO_1
UVRMS
OVRMS
OCF_LAT
DIO_1 / CS
CS
DIO_1_Sel[0..1]
Comm_Sel
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16
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ZERO CROSSING OUTPUT CONFIGURATIONS
The dynamic calculation of N for the RMS and power calculations uses exclusively the voltage zero crossing, but both current
and voltage zero crossing can be flagged and reported on the DIO
pins.
Voltage Zero Crossing (VZC)
The voltage zero crossing has two basic modes of operation,
pulse mode and square wave mode.
Pulse Mode – VZC
In pulse mode, a voltage zero crossing is reported as a short
pulse. There are three available configurations to customize the
voltage zero crossing pulse mode operation: rising or falling edge
selection, every edge selection, and pulse width.
Figure 11: zerocrossedgesel = 1, Rising Zero Crossing
Rising Edge or Falling Edge Aligned Pulse
Pulse Every Edge
The EEPROM field zerocrossedgesel is used to select whether
the zero crossing output pulses are aligned to the rising zero
crossing of the voltage channel or the falling zero crossing of the
voltage channel.
The EEPROM field halfcycle_en is used to output a pulse at
every zero crossing.
Figure 12: halfcycle_en = 1, Both Rising and Falling
Zero Crossings Signaled
Figure 10: zerocrossedgesel = 0, Falling Zero Crossing
Pulse Width Selection
The EEPROM field delaycnt_sel is used to select the width of the
voltage zero crossing pulse.
Table 1: delaycnt_sel
Range
Value
Units
0
32
µs
1
256
µs
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17
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Square Wave Mode
Square wave mode can be configured using the EEPROM field
squarewave_en. In square wave mode, a voltage zero crossing
is reported as a square wave that changes state on each reported
zero crossing. The zerocrossedgesel EEPROM field can be used
to align the low to high transition of the flag with either the rising
voltage zero crossing or the falling voltage zero crossing.
The current zero crossing has just one basic mode of operation:
pulse mode.
Pulse Mode – CZC
In pulse mode, a current zero crossing is reported as a short
pulse. There are three available configurations to customize the
current zero crossing pulse mode operation: rising or falling edge
selection, every edge selection, and pulse width.
Rising Edge or Falling Edge Aligned Pulse
The EEPROM field zerocrossedgesel is used to select whether
the zero crossing output pulses are aligned to the rising zero
crossing of the current channel or the falling zero crossing of the
current channel.
Figure 13: zerocrossedgesel = 0, Square Wave Mode
Figure 15: zerocrossedgesel = 0, Falling Zero Crossing
Figure 14: zerocrossedgesel = 1, Square Wave Mode
Current Zero Crossing (CZC)
The current zero crossing function can be enabled using the
EEPROM field zerocrosschansel. When the zero crossing flag
is configured to flag zero crossings of the current path, this has
no effect on the RMS and power calculations; the voltage zero
crossing is still used for these calculations.
Figure 16: zerocrossedgesel = 1, Rising Zero crossing
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18
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Pulse Every Edge
The EEPROM field halfcycle_en is used to output a pulse at
every zero crossing.
Figure 17: halfcycle_en = 1, Both Rising and Falling
Zero Crossings Signaled
CONFIGURING THE DEVICE FOR AC APPLICATIONS
Device EEPROM Settings
For AC power monitoring applications using the ACS37800, the
following device settings are recommended:
DYNAMIC CALCULATION OF N
Set bypass_n_en = 0 (default). This setting enables the device to
dynamically calculate N based off the voltage zero crossings. See
the Register Details – EEPROM section for additional details.
Voltage Measurement
form a resistor divider network where,
𝑉𝑉𝐼𝐼𝐼𝐼 = 𝑉𝑉𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 ∗
RISO1 and RISO2 should be equal. A value of 1 MΩ is appropriate
for many applications, but ultimately, the resistance value used
needs to comply with the required isolation of the system.
VINP
RECOMMENDED APPLICATION CIRCUITS
An important aspect to consider when designing in the
ACS37800 into AC applications is the design of the voltage measurement path. Typically, a resistor divider network is employed
to provide both isolation and transform the high voltage signal
into the ±250 mV signal that the ACS37800 can measure.
There are two basic application circuits recommended based on
the isolation requirements of the system. The first, see Figure 18,
is to be used when the ACS37800 GND and the neutral terminal
of the voltage input are connected. RISO1, RISO2, and RSENSE
𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼1 + 𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼2 + 𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
RISO1
1 MΩ
RISO2
1 MΩ
RSENSE
Vin
VINN
Figure 18: Voltage Channel Application Circuit; Device
GND is Connected to Neutral
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19
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
𝑉𝑉𝐼𝐼𝐼𝐼 = 𝑉𝑉𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 ∗
𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼1 + 𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼2 + 𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼3 + 𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼4 + 𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
RISO1, RISO2, RISO3, and RISO4 should be equal and their value is
determined by the isolation requirements of the system. A value
of 1 MΩ is appropriate for many applications, but ultimately, the
resistance value used needs to comply with the required isolation
of the system.
1 MΩ
RISO2
1 MΩ
RSENSE
If the RSENSE is not sized appropriately, this can lead to the
voltage input to the ACS38700 exceeding the maximum input
range, which can cause the instantaneous voltage measurement to
saturate. This can lead to errors in the RMS calculations as shown
in Figure 20.
Input > Fullscale
Output Fullscale Range
RISO1
VINP
Additionally, the tolerance of the all resistors should be considered when determining RSENSE. The minimum tolerance of the
isolation resistors should be used along with the maximum tolerance of RSENSE.
Vin
Output Saturation
Expected RMS
Another application circuit recommendation for the voltage channel is shown in Figure 19. This is to be used in systems where
the ACS37800 GND and the neutral terminal of the voltage input
are to be isolated. Here, RISO3 and RISO4 are added to the resistor
divider network.
Output RMS
ACS37800
Input Waveform
Output Readpoints
Absolute Output
Readpoints
RISO3
VINN
1 MΩ
RISO4
1 MΩ
Figure 19: Voltage Channel Application; Device GND is
Isolated from Neutral
To determine the value of RSENSE required for a particular application using either of the recommended circuits, the following
equation can be used:
𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 =
∆𝑉𝑉𝐼𝐼𝐼𝐼𝐼𝐼 (𝑀𝑀𝑀𝑀𝑀𝑀)
𝑉𝑉𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿(𝑀𝑀𝑀𝑀𝑀𝑀) − ∆𝑉𝑉𝐼𝐼𝐼𝐼𝐼𝐼 (𝑀𝑀𝑀𝑀𝑀𝑀)
∗ 𝑅𝑅𝐼𝐼𝐼𝐼𝐼𝐼
Where ΔVINR(MAX) = 250 mV, VLINE(MAX) is the maximum VLINE
voltage to be measured, and RISO is the sum of all of the isolation
resistors.
If using the overvoltage detection functionality of the ACS37800,
this should be considering when determining the maximum VLINE
voltage to be measured. For example, in an application when
the nominal VLINE is equal to 120 VRMS and a 50% over-voltage
detection is required, VLINE(MAX) is:
Figure 20: Output Saturation
Current Measurement
For the current path, there are two current ranges to consider: the
range of RMS current to be measured and the range required for
overcurrent fault detection.
When considering the range of RMS current to be measured, the
Current Sensing Range (IPR) is not to be exceeded. This can lead
to saturation, as shown in Figure 20, and lead to error in the RMS
calculations.
The overcurrent fault detection can exceed IPR and is defined as
Fault Range Max, IFAULT(MAX). Once the current exceeds IPR, the
RMS calculations will no longer be accurate.
120 VRMS × √2 × 1.5 = 255 V,
where the √2 is used to approximate the peak voltage assuming a
sinusoidal input.
Allegro MicroSystems
955 Perimeter Road
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20
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
CONFIGURING THE DEVICE FOR DC APPLICATIONS
OR FOR APPLICATIONS WITH NO VOLTAGE ZERO CROSSING
The follow recommendations are provided for DC applications,
as well as any other applications where there is no voltage zero
crossing. Possible applications include current sensing only,
sensing of a rectified voltage signal, or applications where the
nominal frequency on the voltage channel is greater than 300 Hz.
Device EEPROM Settings
For DC power monitoring applications using the ACS37800 or
applications only using the current measurement capability of the
ACS37800, the following device settings are recommended.
FIXED SETTING OF N
Set bypass_n_en = 1. This setting disables the dynamic calculation of n based off voltage zero crossings and sets n to a fixed
value, which is set using EERPOM field n. See the Register
Details – EEPROM section for additional details.
Voltage Measurement
RECOMMENDED APPLICATION CIRCUITS
The recommended application circuit for the voltage channel in
DC operation is the same as the AC application circuit where
Device GND is connected to Neutral (refer to Figure 18).
Current Measurement
The same considerations for AC applications can be used for the
current path for DC applications.
RMS AND POWER ACCURACY VS. OPERATION POINT
When using the ACS37800 to measure for RMS calculations and
power monitoring, it is important to consider the error specifications of the device.
For DC applications, the impact of offset and gain error on the
final output is straightforward, but for RMS and power calculations, the impact of any errors, specifically offset errors, becomes
dependent on the magnitude of the applied signal.
Figure 21 shows an example system where the maximum measurable power is ~1.3 kW, based on the system design. The overtemperature offset performance of the ACS37800 causes an error
in the measured power that is larger when the applied power is
close to 0 W.
The offset performance of the voltage channel is such that its
contribution to this error is negligible. The current RMS measurement and the power calculations are where this error is observed.
Measured Line Power (W)
RMS and Power Output Error vs. Applied
Input
Figure 21: Line Power Applied (W) vs. Measured Line
Power (W), 15B5 Device
The following figures (Figure 22 through Figure 27) display the
measurement error for the RMS current and active power for
each available device variant.
Allegro MicroSystems
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21
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
15B5 IRMS and Power Error
°
°
°
°
°
°
Figure 22: IRMS Error [A] vs. Applied IRMS [A]
°
°
°
Figure 24: IRMS Error [A] vs. Applied IRMS [A]
90B3 IRMS and Power Error
°
°
°
Figure 25: Line Power Error [W] vs. Applied Line Power
[W]
°
°
°
°
°
°
Figure 23: Line Power Error [W] vs. Applied Line Power [W]
30B3 IRMS and Power Error
Figure 26: IRMS Error [A] vs. Applied IRMS [A]
Figure 27: Line Power Error [W] vs. Applied Line Power [W]
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955 Perimeter Road
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22
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
DIGITAL COMMUNICATION
Communication Interfaces
Registers and EEPROM
The ACS37800 supports communication over 1 MHz I2C and
10 MHz SPI. However, the communication protocol is fixed during factory programming. The ACS37800 MISO pin continues to
drive the MISO line when CS goes high. This may prevent other
devices from communicating properly. It is recommended that the
ACS37800 be the only device on the SPI bus if using SPI communication.
WRITE ACCESS
The ACS37800 supports factory and customer EEPROM space as
well as volatile registers. The customer access code must be sent
prior to writing these customer EEPROM spaces. In addition, the
device includes a set of free space EEPROM registers that are
accessible with or without writing the access code.
SPI
READ ACCESS
All EEPROM and volatile registers may be read at any time
regardless of the access code.
The SPI frame consists of:
• The Master writes on the MOSI line the 7-bit address of the
register to be read from or written to.
EEPROM
• The next bit on the MOSI line is the read/write (RW) indicator.
A high state indicates a Read and a low state indicates a Write.
At power up, all shadow registers are loaded from EEPROM,
including all configuration parameters. The shadow registers can
be written to in order to change the device behavior without having to perform an EEPROM write. Any changes made in shadow
memory are volatile and do not persist through a reset event.
• The device sends a 32-bit response on the MISO line. The
contents correspond to the previous command.
• On the MOSI line, if the current command is a write, the
32 bits correspond to the Write data, and in the case of a read,
the data is ignored.
WRITING
The Timing Diagram for an EEPROM write is shown in Figure 28
and Figure 29.
CSN
SCLK
0
MOSI
1
5
6
REGISTER ADDRESS
MISO
0
RW
1
30
31
WRITE DATA OR DC
PREVIOUS CMD DATA
Figure 28: EEPROM Write – SPI Mode
SDA
SA[6:0]
ST
A[6:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
Slave W A 0 Register A Register A Register A Register A Register A
address
C
address C Data C Data C Data C Data C
K
K [7:0] K [15:8] K [23:16] K [31:24] K
SP
Figure 29: EEPROM Write – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
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23
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
READING
The timing diagram for an EEPROM read is shown in Figure 30
and Figure 31.
CSN
SCLK
0
MOSI
1
5
REGISTER ADDRESS
MISO
6
0
RW
1
30
31
WRITE DATA OR DC
PREVIOUS CMD DATA
Figure 30: EEPROM Read – SPI Mode
For SPI, the read data will be sent out
during the above command.
SDA
SA[6:0]
ST
A[6:0]
Slave W A 0 Register A ST
address
C
address C
K
K
SA[6:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
Slave R A Register A Register A Register A Register N
address
C Data C Data C Data C Data A
K [7:0] K [15:8] K [23:16] K [31:24] C
K
SP
Figure 31: EEPROM Read – I2C Mode
Blue represents data sent by the master and
orange is the data sent by the slave.
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955 Perimeter Road
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24
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
EEPROM Error Checking and Correction (ECC)
Hamming code methodology is implemented for EEPROM
checking and correction (ECC). ECC is enabled after power-up.
The ACS37800 analyzes message data sent by the controller and
the ECC bits are added. The first 6 bits sent from the device to
the controller are dedicated to ECC. The device always returns
32 bits.
EEPROM ECC Errors
If for any reason the external slave address setting feature is not
desired, the DIO polling can be disabled by setting the i2c_dis_
slv_addr. When this bit is set, the ACS37800 will automatically
use the number stored in i2c_slv_addr as the I2C slave address
regardless of the voltage on the DIO pins. Note that the device
must be repowered for these changes to take effect.
Table 2: DIO Startup Voltage Addressing
A6 A5 A4 A3 A2 A1 A0
Slave Address
(decimal)
DIO_1
DIO_2
0
0
0
0
1
1
0
0
0
0
0
96
Bits
Name
Description
31:28
–
No meaning
0
0
0
1
1
1
0
0
0
0
1
97
00 = No Error
01 = Error detected and message corrected
10 = Uncorrectable error
11 = No meaning
0
0
1
0
1
1
0
0
0
1
0
98
0
0
1
1
1
1
0
0
0
1
1
99
0
1
0
0
1
1
0
0
1
0
0
100
0
1
0
1
1
1
0
0
1
0
1
101
0
1
1
0
1
1
0
0
1
1
0
102
0
1
1
1
1
1
0
0
1
1
1
103
1
0
0
0
1
1
0
1
0
0
0
104
1
0
0
1
1
1
0
1
0
0
1
105
1
0
1
0
1
1
0
1
0
1
0
106
1
0
1
1
1
1
0
1
0
1
1
107
1
1
0
0
1
1
0
1
1
0
0
108
1
1
0
1
1
1
0
1
1
0
1
109
1
1
1
0
1
1
0
1
1
1
0
27:26
ECC
25:0
D[25:0]
EEPROM data
I2C Slave Addressing
The ACS37800 supports I2C communication over the SCL and
SDA lines at speeds of up to 400 kHz. When the device first
powers on, it measures the voltage level on the two DIO pins. It
converts both voltage levels into a 4-bit code for a total of sixteen
slave addresses. Table 2 shows the sixteen possible I2C configurations that can be set with externally applied voltage. If both
pins are pulled to VCC, then the internal slave address stored in
EEPROM is used. By default, the value of i2c_slv_addr is programmed at the Allegro factory to 127, but this can be changed
with programming by the customer.
1
1
1
1
EE EE EE EE EE EE EE
110
EEPROM
value
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25
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
MEMORY MAP
Bits
iavgselen
delaycnt_sel
delaycnt_sel
n
3
2
1
0
ichan_del_en
i2c_slv_addr
qvo_fine
rms_avg_2
undervreg
4
vevent_cycs
sns_fine
fault
halfcycle_en
squarewave_en
zerocrossedgesel
0x1F
zerocrosschansel
0x1E
bypass_n_en
fltdly
overvreg
dio_1_sel
crs_sns
vchan_offset_code
0x1D
Shadow
halfcycle_en
squarewave_en
zerocrosschansel
n
0x1B
0x1C
undervreg
5
rms_avg_1
ichan_del_en
ECC
fault
i2c_dis_slv_addr
0x0F
fltdly
6
rms_avg_1
overvreg
vevent_cycs
i2c_dis_slv_addr
ECC
7
rms_avg_2
chan_del_sel
0x0E
vchan_offset_code
dio_0_sel
ECC
8
qvo_fine
chan_del_sel
0x0D
9
sns_fine
dio_0_sel
ECC
crs_sns
dio_1_sel
0x0C
iavgselen
ECC
EEPROM
0x0B
zerocrossedgesel
pavgselen
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
bypass_n_en
Address
EEPROM/Shadow Memory
i2c_slv_addr
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26
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register Details – EEPROM
Register 0x0B/0x1B
Bits
Name
Default Value
Description
8:0
qvo_fine
Device Specific
Offset fine trimming on current channel
18:9
sns_fine
Device Specific
Fine gain trimming on the current channel
21:19
crs_sns
Selection Specific
22
iavgselen
0
Current Averaging selection
23
pavgselen
0
Power Averaging selection
31:26
ecc
–
Error Code Correction
Coarse gain setting
qvo_fine
crs_sns
Offset adjustment for the current channel. This is a signed 9-bit
number with an input range of –256 to 255. With a step size
of 64 LSB, this equates to an offset trim range of –16384 to
16320 LSB, which is added to the icodes value. The current channel’s offset trim should be applied before the gain is trimmed.
qvo_fine is further described in Table 3.
Coarse gain adjustment for the current channel. This gain is
implemented in the analog domain before the ADC. This is a
3-bit number that allows for 8 gain selections. Adjustments to
crs_sns may impact the device’s performance over temperature.
Datasheet limits apply only to the factory settings for crs_sns.
The gain settings map to 1×, 2×, 3×, 3.5×, 4×, 4.5×, 5.5×, and 8×.
crs_sns is further described in Table 5.
Table 3: qvo_fine
Range
Value
Units
–256 to 255
–16,384 to 16,320
LSB
sns_fine
Gain adjustment for the current channel. This is a signed 9-bit
number with an input range of –256 to 255. This gain adjustment
is implemented as a percentage multiplier centered around 1 (i.e.
writing a 0 to this field multiplies the gain by 1, leaving the gain
unaffected). The fine sensitivity parameter ranges from 50% to
150% of IP. The current channel’s offset trim should be applied
before the gain is trimmed. sns_fine is further described in Table 4.
Table 5: crs_sns
Range
Value
Units
0
1×
–
1
2×
–
2
3×
–
3
3.5×
–
4
4×
–
5
4.5×
–
6
5.5×
–
7
8×
–
iavgselen
Table 4: sns_fine
Range
Value
Units
–256 to 255
50 to 100
%
Current Averaging selection enable. 0 will select vrms for averaging. 1 will select irms for averaging.
pavgselen
Power Averaging selection enable. 0 will select vrms for averaging. 1 will select pactive for averaging.
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27
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x0C/0x1C
Bits
Name
Default Value
Description
6:0
rms_avg_1
0
Average of the rms voltage or current – stage 1
16:7
rms_avg_2
0
Average of the rms voltage or current – stage 2
24:17
vchan_offset_code
Device Specific
Controls the room offset for the voltage channel
31:26
ecc
–
Error Code Correction
rms_avg_1
vchan_offset_code
Number of averages for the first averaging stage (vrmsavgonesec
or irmsavgonesec). The value written into this field directly maps
to the number of averages ranging from 0 to 127. For optimal
performance, an even number of averages should be used. The
channel to be averaged is selected by the current average select
enable bit (iavgselen). rms_avg_1 is further described in Table 6.
This controls the offset of the voltage channel at room.
Table 8: vchan_offset_code
Range
Value
Units
–128 to 127
–2048 to 2032
codes
Table 6: rms_avg_1
Range
Value
Units
0 to 127
0 to 127
number of averages
rms_avg_2
Number of averages for the second averaging stage (vrmsavgonemin or irmsavgonemin). This stage averages the outputs of the first
averaging stage. The value written into this field directly maps to
the number of averages ranging from 0 to 1023. For optimal performance, an even number of averages should be used. The channel to be averaged is selected by the current average select enable
bit (iavgselen). rms_avg_2 is further described in Table 7.
Table 7: rms_avg_2
Range
Value
Units
0 to 1023
0 to 1023
number of averages
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955 Perimeter Road
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28
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
Register 0x0D/0x1D
Bits
Name
Default Value
Description
7
ichan_del_en
0
Enable phase delay on voltage or current channel
11:9
chan_del_sel
0
Sets phase delay on voltage or current channel
20:13
fault
70
Sets the overcurrent fault threshold
23:21
fltdly
0
Sets the overcurrent fault delay
31:26
ecc
–
Error Code Correction
ichan_del_en
Table 12: fltdly
Enables delay for either the voltage or current channel. Setting to
1 enables delay for the current channel. ichan_del_en is further
described in Table 9.
Range
Value
Units
0
0
µs
1
0
µs
2
4.75
µs
Units
3
9.25
µs
13.75
µs
Table 9: ichan_del_en
Range
Value
0
0 – voltage channel
LSB
4
1
1 – current channel
LSB
5
18.5
µs
6
23.25
µs
7
27.75
µs
chan_del_sel
Sets the amount of delay applied to the voltage or current channel (set
by ichan_del_en). chan_del_sel is further described in Table 10.
Table 10: chan_del_sel
Range
Value
Units
0 to 7
0 to 219
µs
fault
Over-current fault threshold. This is an unsigned 8-bit number
with an input range of 0 to 255, which equates to a fault range of
65% to 200% of IP. The factory setting of this field is 70. fault is
further described in Table 11.
Table 11: fault
Range
Value
Units
0 to 255
56 to 225
% of IP
fltdly
Fault delay setting of the amount of delay applied before flagging
a fault condition. fltdly is further described in Table 12.
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29
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x0E/0x1E
Bits
Name
Default Value
Description
5:0
vevent_cycs
0
Sets the number of qualifying cycles needed to flag overvoltage or undervoltage
13:8
overvreg
0
Sets the overvoltage fault threshold
19:14
undervreg
0
Sets the undervoltage fault threshold
20
delaycnt_sel
0
Sets the width of the voltage zero-crossing output pulse
21
halfcyclc_en
0
Sets the zero crossing flag triggering on half or full cycle (default: full cycle)
22
squarewave_en
0
Sets the zero crossing pulse characteristics (default: pulse)
23
zerocrosschansel
0
Sets the channel that triggers the zero crossing flag (default: voltage)
24
zerocrossedgesel
0
Sets the edge that triggers zero crossing flag
31:26
ecc
–
Error Code Correction
vevent_cycs
delaycnt_sel
Sets the number of cycles required to assert the ovrms flag or
the uvrms. This is an unsigned 6-bit number with an input range
of 0 to 63. The value in this field directly maps to the number of
cycles. vevent_cycs is further described in Table 13.
Selection bit for the width of pulse for a voltage zero-crossing
event. When set to 0, the pulse is 32 µs. When set to 1, the
pulse is 256 µs. When the squarewave_en bit is set, this field is
ignored. delaycnt_sel is further described in Table 16.
Table 13: vevent_cycs
Table 16: delaycnt_sel
Range
Value
Units
Range
0 to 63
1 to 64
cycles
overvreg
Value
Units
0
32
µs
1
256
µs
Sets the threshold of the overvoltage rms flag (ovrms). This is a
6-bit number ranging from 0 to 63. This trip level spans the entire
range of the vrms register. The flag is set if the rms value is above
this threshold for the number of cycles selected in vevent_cycs.
overvreg is further described in Table 14.
halfcycle_en
Table 14: overvreg
squarewave_en
Range
Value
Units
0 to 63
0 to 65536
LSB
undervreg
Sets the threshold of the undervoltage rms flag (uvrms). This is
a 6-bit number ranging from 0 to 63. This trip level spans one
entire range of the vrms register. The flag is set if the rms value is
below this threshold for the number of cycles selected in vevent_
cycs. undervreg is further described in Table 15.
Table 15: undervreg
Range
Value
Units
0 to 63
0 to 65536
LSB
Setting for the zero crossing flag. When set to 0, the voltage
zero-crossing will be indicated on every edge determined by
zerocrossingedgesel. When set to 1, the voltage zero-crossing will
be indicated on both rising and falling edges.
Setting for the zero crossing flag. When set to 0, the zero-crossing event will be indicated by a pulse on the DIO pin. When set
to 1, the zero-crossing event will be indicated by a level change
on the DIO pin.
zercrossingchansel
Determines which channel will trigger the zero crossing flag. 0
is the voltage channel. 1 is the current channel with zero crossing flag for rising and falling with only one customizable register
delaycnt_sel.
zerocrossingedgesel
This determines whether the zero crossing flag triggers on rising
or falling. Note: if halfcycle_en = 1, this setting does not matter.
Allegro MicroSystems
955 Perimeter Road
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30
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x0F/0x1F
Bits
Name
Default Value
Description
8:2
i2c_slv_addr
127
9
i2c_dis_slv_addr
0
Disable I2C slave address selection circuit
I2C slave address selection
11:10
dio_0_sel
0
Digital output 0 multiplexor selection bits
13:12
dio_1_sel
0
Digital output 1 multiplexor selection bits
23:14
n
0
Sets the number of samples used in RMS calculations when bypass_n_en = 1
24
bypass_n_en
0
Set whether RMS is calculated based on voltage zero crossing or n samples from the
above registers
31:26
ecc
–
Error Code Correction
i2c_slv_addr
i2c_dis_slv_addr
I2C
Settings for the
slave address externally. When i2c_dis_slv_
addr is set to 0, the voltage on the DIO pins are measured at
power on and are used to set the device’s slave address.
Each DIO pin has 4 voltage “bins” which may be used to set
the I2C slave address. These voltages may be set using resistor divider circuits from VCC to GND. i2c_slv_addr is further
described in Table 17.
Table 17: i2c_slv_addr
DIO_1
(decimal)
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
DIO_0
(decimal)
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Slave Address
(decimal)
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
EEPROM value
When i2c_dis_slv_addr is set to 1, the address is set through
EEPROM field i2c_slv__addr[6:0]. This enables or disables the
analog I2C slave address feature at power on. When this bit is set,
the I2C slave address will map directly to i2c_slv_addr.
dio_0_sel
Determines which flags are output on the DIO0 pin. Only used
when the device is in I2C programming mode.
dio_1_sel
Determines which flags are output on the DIO1 pin. Only used
when the device is in I2C programming mode.
Ratio of VCC on DIO Pin
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31
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
9
8
7
vrms
pimag
pactive
0x22
pospf
irms
0x21
posangle
0x20
pfactor
6
5
3
2
1
faultout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
faultlatched
Bits
overvoltage
Address
Volatile Memory
4
0
papparent
0x23
0x24
0x25
numptsout
0x26
irmsavgonesec
vrmsavgonesec
0x27
irmsavgonemin
vrmsavgonemin
0x28
pactavgonesec
pactavgonemin
icodes
vcodes
0x2B
0x2C
0x2D
vzerocrossout
pinstant
undervoltage
0x2E
0x2F
access_code
customer_access
VOLATILE
0x29
0x2A
0x30
0x31
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32
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register Details – Volatile
Register 0x20
Bits
Name
Description
15:0
vrms
Voltage RMS value
31:16
irms
Current RMS value
vrms
irms
RMS voltage output. This field is an unsigned 16-bit fixed point
number with 16 fractional bits, where ΔVIN(MAX) = 0.84, and
ΔVIN(min) = –0.84. To convert the value (input voltage) to line
voltage, divide the input voltage by the RSENSE and RISO voltage
divider ratio using actual resistor values.
RMS current output. This field is a signed 16-bit fixed point number with 15 fractional bits, where IIP(MAX) = 0.84, and IIP(MIN)=
-0.84.
Table 18: vrms
Register
Range
Valid Range
Value
Units
0 to ~1
0 to ~0.84
[0 to ~1] × ΔVIN(MAX) ×1.19
mV
Table 19: irms
Register
Range
Valid Range
Value
Units
0 to ~1
0 to ~0.84
[0 to ~1] × IPR(MAX) ×1.19
A
Register 0x21
Bits
Name
Description
15:0
pactive
Active power
31:16
pimag
Reactive power
pactive
pimag
Active power output. This field is a signed 16-bit fixed point
number with 15 fractional bits, where positive MaxPow = 0.704,
and negative MaxPow = –0.704. To convert the value (input
power) to line power, divide the input power by the RSENSE and
RISO voltage divider ratio using actual resistor values.
Reactive power output. This field is an unsigned 16-bit fixed
point number with 16 fractional bits, where MaxPow = 0.704. To
convert the value (input power) to line power, divide the input
power by the RSENSE and RISO voltage divider ratio using actual
resistor values.
Table 20: pactive
Table 21: pimag
Register
Range
Valid Range
Value
Units
Register
Range
Valid Range
Value
Units
–1 to ~1
–0.704 to ~0.704
[1 to ~1] × MaxPow × 1.42
mW
0 to ~1
0 to ~0.704
[0 to ~1] × MaxPow × 1.42
mVA
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955 Perimeter Road
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33
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x22
Bits
Name
Description
15:0
papparent
26:16
pfactor
Apparent power magnitude
27
posangle
Sign of the power angle
28
pospf
Sign of the power factor
Power factor
papparent
posangle
Apparent power output magnitude. This field is an unsigned
16-bit fixed point number with 16 fractional bits, where MaxPow
= 0.704. To convert the value (input power) to line power, divide
the input power by the RSENSE and RISO voltage divider ratio
using actual resistor values.
Bit to represent leading or lagging. A 0 represents the current
leading and a 1 represents the current lagging.
Table 22: papparent
Register
Range
Valid Range
Value
Units
0 to ~1
0 to ~0.704
[0 to ~1] × MaxPow × 1.42
mVAR
pospf
Sign bit to represent if the power is being generated (0) or consumed (1).
pfactor
Power factor output. This field is a signed 11-bit fixed point number with 10 fractional bits. It ranges from –1 to ~1 with a step
size of 2-10. pfactor is further described in Table 23.
Table 23: pfactor
Range
Value
Units
–1 to ~1
–1 to ~1
–
Register 0x25
Bits
Name
9:0
numptsout
Description
Number of samples of current and voltage used for calculations
numptsout
Number of points used in the rms calculation. This will be the
dynamic value that is evaluated internal to the device based on
full cycle zero crossings of the voltage channel. numptsout is
further described in Table 24.
Table 24: numptsout
Range
Value
Units
0 to 1023
0 to 1023
samples
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955 Perimeter Road
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34
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x26
Bits
Name
Description
15:0
vrmsavgonesec
Averaged voltage RMS value; duration set by rms_avg_1.
This register will be zero if iavgselen = 1
31:16
irmsavgonesec
Averaged current RMS value; duration set by rms_avg_1.
This register will be zero if iavgselen = 0
vrmsavgonesec
irmsavgonesec
Voltage RMS value averaged according to rms_avg_1. This register will be zero if iavgselen = 1.
Current RMS value averaged according to rms_avg_1. This register will be zero if iavgselen = 0.
Register 0x27
Bits
Name
Description
15:0
vrmsavgonemin
Averaged voltage RMS value; duration set by rms_avg_2.
This register will be zero if iavgselen = 1
31:16
irmsavgonemin
Averaged current RMS value; duration set by rms_avg_2.
This register will be zero if iavgselen = 0
vrmsavgonemin
irmsavgonemin
Voltage RMS value averaged according to rms_avg_2. This register will be zero if iavgselen = 1.
Current RMS value averaged according to rms_avg_2. This register will be zero if iavgselen = 0.
Register 0x28
Bits
Name
15:0
pactavgonesec
Description
Active Power value averaged over up to one second; duration set by rms_avg_1
pactavgonesec
Active power value averaged according to rms_avg_1.
Register 0x29
Bits
Name
15:0
pactavgonemin
Description
Active Power value averaged over up to one minute; duration set by rms_avg_2
pactavgonemin
Active power value averaged according to rms_avg_2.
Allegro MicroSystems
955 Perimeter Road
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35
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x2A
Bits
Name
Description
15:0
vcodes
Instantaneous voltage measurement
31:16
icodes
Instantaneous current measurement
vcodes
This field contains the instantaneous voltage measurement before
any RMS calculations are done. It is a 16-bit signed fixed point
number with 15 fractional bits, where ΔVIN(MAX) = 0.84 and
ΔVIN(min) = –0.84. To convert the value (input voltage) to line
voltage, divide the input voltage by the RSENSE and RISO voltage
divider ratio using the resistor values.
Table 25: vcodes
Register
Range
Valid Range
Value
Units
–1 to ~1
-0.84 to ~0.84
[–1 to ~1] × ΔVIN(MAX) ×1.19
mV
icodes
This field contains the instantaneous current measurement before
any RMS calculations are done. This field is a signed 16-bit fixed
point number with 15 fractional bits, where IIP(MAX) = 0.84, and
IIP(MIN)= –0.84.
Table 26: icodes
Register
Range
Valid Range
Value
Units
–1 to ~1
-0.84 to ~0.84
[–1 to ~1] × IPR(MAX) ×1.19
A
Register 0x2C
Bits
Name
15:0
pinstant
Description
Instantaneous power – Multiplication of vcodes and icodes
pinstant
This field contains the instantaneous power measurement before
any RMS calculations are done. This field is a signed 16-bit fixed
point number with 15 fractional bits, where postive MaxPow =
0.704, and negative MaxPow = –0.704. To convert the value
(input power) to line power, divide the input power by the RSENSE
and RISO voltage divider ratio using the resistor values.
Table 27: pinstant
Register
Range
Valid Range
Value
Units
–1 to ~1
–0.704 to ~0.704
[–1 to ~1] × MaxPow × 1.42
mVAR
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
36
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Register 0x2D
Bits
Name
0
zerocrossout
Description
Zero-crossing output
1
faultout
2
faultlatched
Current fault output
Current fault output latched
3
overvoltage
Overvoltage flag
4
undervoltage
Undervoltage flag
zerocrossout
overvoltage
Flag for the zero-crossing events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel. This flag will still follow the halfcycle_en and squarewave_en settings.
Flag for the overvoltage events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel and will only be set
when fault is present.
faultout
undervoltage
Flag for the overcurrent events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel and will only be set
when fault is present.
Flag for the undervoltage events. This will be present and active
regardless of DIO_0_sel and DIO_1_sel and will only be set
when fault is present.
faultlatched
Flag for the overcurrent events. This bit will latch and will remain
1 as soon as an overcurrent event is detected. This can be reset by
writing a 1 to this field. This will be present and active regardless
of DIO settings.
Register 0x2F
Bits
Name
31:0
access_code
Description
Access code register:
Customer code: 0x4F70656E
Register 0x30
Bits
Name
0
customer_access
Description
Customer write access enabled.
0 = Non-Customer mode.
1 = Customer mode.
Allegro MicroSystems
955 Perimeter Road
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37
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
THERMAL PERFORMANCE
The thermal capacity of the ACS37800 should be verified by the
Thermal Rise vs. Primary Current
Self-heating due to the flow of current should be considered during the design of any current sensing system. The sensor, printed
circuit board (PCB), and contacts to the PCB will generate heat
as current moves through the system.
The thermal response is highly dependent on PCB layout, copper
thickness, cooling techniques, and the profile of the injected current.
The current profile includes peak current, current “on-time”, and
duty cycle. While the data presented in this section was collected
with direct current (DC), these numbers may be used to approximate
thermal response for both AC signals and current pulses.
The plot in Figure 32 shows the measured rise in steady-state die
temperature of the ACS37800 versus continuous current at an ambient temperature, TA, of 25 °C. The thermal offset curves may be
directly applied to other values of TA. Conversely, Figure 33 shows
the maximum continuous current at a given TA. Surges beyond the
maximum current listed in Figure 33 are allowed given the maximum junction temperature, TJ(MAX) (165℃), is not exceeded.
end user in the application’s specific conditions. The maximum
junction temperature, TJ(MAX) (165℃), should not be exceeded.
Further information on this application testing is available in
the DC and Transient Current Capability application note on the
Allegro website.
ASEK37800 Evaluation Board Layout
Thermal data shown in Figure 32 and Figure 33 was collected
using the ASEK37800 Evaluation Board (TED-0003306). This
board includes 750 mm2 of 4 oz. copper (0.0694 mm) connected
to pins 1 through 4, and to pins 5 through 8, with thermal vias
connecting the layers. Top and Bottom layers of the PCB are
shown below in Figure 34.
Change in Die Temperature
(°C)
140
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
Continuous Current (A)
Continuous Current (A)
Figure 32: Self Heating in the MA Package
Due to Current Flow
80
70
60
50
40
30
20
10
0
25
50
75
100
125
150
175
Ambient Temperature (°C)
Figure 33: Maximum Continuous Current at a Given TA
Figure 34: Top and Bottom Layers
for ASEK37800 Evaluation Board
Gerber files for the ASEK37800 evaluation board are available
for download from the Allegro website. See the technical documents section of the ACS37800 device webpage.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
38
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
RECOMMENDED PCB LAYOUT
NOT TO SCALE
All dimensions in millimeters.
15.75
9.54
0.65
1.27
Package Outline
Slot in PCB to maintain >8 mm creepage
once part is on PCB
2.25
7.25
1.27
3.56
17.27
Current
Out
Current
In
21.51
Perimeter holes for stitching to the other,
matching current trace design, layers of
the PCB for enhanced thermal capability.
Figure 35: Recommended PCB Layout
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
39
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
ACS37800
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MS-013AA)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
8°
0°
E
10.30 ±0.20
16
0.33
0.20
D
D1
D2
7.50 ±0.10
10.30 ±0.33
A
1
1.27 1.40 REF
0.40
2
D 0.90
Branded Face
0.25 BSC
SEATING PLANE
16×
C
2.65 MAX
0.10
C
GAUGE PLANE
SEATING
PLANE
0.30
0.10
1.27 BSC
0.51
0.31
0.65
1.27
16
XXXXXXX
Lot Number
2.25
1
9.50
B
Standard Branding Reference View
Lines 1, 2 = 12 characters
Line 1: Part Number
Line 2: First 8 characters of Assembly Lot Number
1
C
2
PCB Layout Reference View
A
Terminal #1 mark area
B
Branding scale and appearance at supplier discretion
C Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
D
Hall elements (D1, D2), not to scale
E
Active Area Depth 0.293 mm
Figure 36: Package MA, 16-Pin SOICW
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
40
ACS37800
Isolated, Digital Output, Power Monitoring IC
with Zero-Crossing Detection, Overcurrent and Overvoltage Flagging
Revision History
Number
Date
Description
–
November 30, 2020
Initial release
1
January 27, 2021
Updated Part Numbering schematic (page 2), Supply Bypass Capacitor unit, Current Channel Power Supply
Error test conditions (page 6), Figure 4 (page 12), Figure 9 (page 15), and Figure 21 (page 21).
2
February 24, 2021
Removed TUV certificate mark (page 1)
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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41