ACS761ELFTR-20B-T

ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Features and Benefits ▪ Hall-effect current monitor—no external sense resistor required ¯ ¯¯¯ ¯ PGO ¯D ▪ PGOOD and ¯¯ ¯ ¯¯ O¯ indication ▪ Analog output voltage (factory trimmed for gain and offset) proportional to applied current ▪ External high-side FET gate drive ▪ 240V*A power fault protection with user-selectable delay ▪ Overcurrent fault protection with user-selectable delay ▪ Fault protection isolates failed supply from output in < 2 μs ▪ 1.5 mΩ internal conductor resistance ▪ Active low latched Fault indicator output signal ▪ User controlled soft start / hot-swap function ▪ Logic enable input pin ▪ 10.8 to 13.2 V, single-supply operation ▪ 2 kV ESD protection for all pins Description The ACS761 combines Allegro® Hall-effect current sense technology with a hot-swap controller resulting in a more efficient integrated controller for 12 V applications. By eliminating the need for a shunt resistor, the I2R losses in the power path are reduced. When the ACS761 is externally enabled, and the voltage rail is above the internal UVLO threshold, the internal charge pump drives the gate of the external FET. When the load voltage reaches its target value PGOOD is asserted high. When a fault is detected, the gate is disabled while simultaneously alerting the application that a fault has occurred. The integrated protection in the ACS761 incorporates three levels of fault protection, which includes a Power Fault with user-selectable delay, an Overcurrent Fault threshold with userselectable delay, and Short Circuit protection, which disables the gate in less than 2 μs. These faults are indicated to the host system via the Fault pin and are cleared upon reasserting enable high. Package: 24 pin QSOP (suffix LF) Approximate Scale Typical Application 1 2 IP 3 4 CIN Enable REN CEN VOUT RV1 5 6 7 8 9 10 11 12 IP+ IP+ IP+ IP+ IP+ IP+ EN VIOUT NC CG OCDLY OPDLY IP– IP– IP– IP– IP– IP– GATE GND PGOOD FB+ PGOOD FAULT 24 23 22 21 20 19 18 17 16 15 14 13 RG RFB 100 kΩ RS1 100 kΩ RFAULT 100 kΩ 3.3 V S1 CLOAD VLOAD ACS761 CG COCD COPD 761ELF20B-DS, Rev. 4 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Selection Guide Part Number Package Packing* 2500 pieces/reel ACS761ELFTR-20B-T QSOP24 surface mount *Contact Allegro for additional packing options Absolute Maximum Ratings Characteristic Forward Voltage, IPx pins* GATE Drive Output Voltage* FB+ Forward Voltage* EN Forward Voltage* All Other Pins Forward Voltage Reverse DC Voltage, All Pins* Reverse Transient DC Voltage, All Pins* Current Sense Output Current Source Current Sense Output Current Sink Operating Ambient Temperature Maximum Junction Temperature Storage Temperature * With respect to GND. Symbol VCC VGATE VFB+ VEN VIN VR Vr IVIOUT(Source) IVIOUT(Sink) TA TJ(max) Tstg VCC to VIOUT Range E VIOUT to GND Notes Rating 24 32 24 32 8 –0.5 –5 1 1 –40 to 85 165 –65 to 165 Units V V V V V V V mA mA ºC ºC ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Pin-out Diagram IP+ 1 IP+ 2 IP+ 3 IP+ 4 IP+ 5 IP+ 6 EN 7 VIOUT 8 NC 9 CG 10 OCDLY 11 OPDLY 12 24 IP– 23 IP– 22 IP– 21 IP– 20 IP– 19 IP– 18 GATE 17 GND 16 PGOOD 15 FB+ 14 PGOOD 13 FAULT Terminal List Table Number 1-6 7 8 9 10 11 12 13 14 15 16 17 18 19-24 Name IP+ EN VIOUT NC CG OCDLY OPDLY ¯ ¯ ¯¯ ¯ ¯ L¯ ¯ FAU¯ T ¯¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯¯ PGOOD FB+ PGOOD GND GATE IP– Function Primary sampled current conduction path input; power input pins: connected to VCC. Enable pin. The falling edge on the EN pin clears an overpower, overcurrent, or short circuit fault. Analog output. Output voltage on this pin is proportional to the current flowing from the IP+ pins to the IP– pins. No connect. Connection to ground is recommended. Terminal for CG capacitor. May be used to adjust the turn-on time and soft start control of an external MOSFET, S1. Voltage on this pin limits inrush current through MOSFET S1. Set via external capacitance, CG, connected between this pin and GND. This capacitor is charged by an internal 20 μA current source. Terminal for external capacitor, COCD, Used to adjust delay for overcurrent shutdown, set via the external capacitor, COCD, connected between this pin and GND. Terminal for external capacitor, COPD, Used to adjust delay for overpower shutdown, set via the external capacitor, COPD, connected between this pin and GND. Active low; output signal for device short circuit and overpower faults. Connect a pull-up resistor between this pin and the 3.3 V rail. Active low; output signal indicating load voltage has risen to the proper level. Input of positive feedback on output voltage. Used to determine overpower fault threshold by difference between FB+ and GND pins. Active high; output signal indicating load voltage has risen to the proper level. Terminal for ground connection. Terminal for external MOSFET, S1. Provides output voltage to drive S1. Current through S1 is controlled at startup by external capacitance connected between the CG pin and GND. Primary sampled current conduction path output; power output pins. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Functional Block Diagram +12 V Load S1 EN 100 kΩ CG GATE PGOOD FB+ Charge Pump IP+ Hall Current Drive Dynamic Offset Cancellation Power Calculator VREF Signal Recovery – + Short Circuit Detection IP– OPDLY OCDLY Zero Current Output Voltage Adjustment PGOOD / Fault Logic FAULT +12 VIN – + – + Bias and VREG UVLO PGOOD OPDLY OCDLY VIOUT Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC OPERATING CHARACTERISTICS valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted Characteristic General Electrical Characteristics Source Current Linear Sensing Range Primary Conductor Resistance Supply Voltage Supply Current Undervoltage Lockout (UVLO) Symbol ISOURCE IP RPRIMARY VCC ICC VUVLOH VUVLOL tUVLOE UVLO Delay to Chip Enable/ Disable tUVLOD FB+ Input Resistance RFB Current Sense Performance Characteristics VIOUT Analog Output Propagation tPROP Time VIOUT Analog Output 10-90% Rise tr Time VIOUT Load Capacitance CLOAD VIOUT Load Resistance RLOAD VIOUT Analog Signal Bandwidth1 VIOUT Analog Signal Sensitivity Sensitivity Slope Over Temperature VIOUT Analog Noise Level2 VIOUT Analog Nonlinearity Zero Current Output Voltage Zero Current Output Slope Over Temperature Output Voltage Saturation3 VIOUT Total Error % of IP f3dB Sens ∆SensTA VNOISE(PP) ELIN VIOUT(Q) ∆IOUT(Q)TA VOL VOH ETOT Test Conditions TA = 25°C, VIOUT connected to GND Current flows from IP+ to IP- pins TA = 25°C Voltage applied to IP+ pins VCC rising and CG pin current source turns on, EN pin = high VCC falling and CG pin current source turns off, EN pin = high Enabling, measured from rising VCC > VUVLOH to VGATE > 1 V, EN pin = high Disabling, measured from falling VCC < VUVLOL to VGATE < 1 V, EN pin = high TA = 25°C TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND = 100 pF TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND = 100 pF Min. – 0 – 10.8 – – 7.0 – – – – – – 20 –3 dB, Ip = 10 A peak-to-peak, TA = 25°C, no external device filter, capacitance from VIOUT to GND = 100 pF TA = 25°C Over full ambient operating temperature range TA = 0°C to 25°C TA = 25°C to 85°C Mean peak-to-peak, TA = 25°C, 50 kHz external device filter Over full ambient operating temperature range and linear sensing range TA = 0°C to 85°C TA = 0°C to 25°C TA = 25°C to 85°C TA = 25°C TA = 25°C TA = 25°C, IP = 20 A TA = 0°C to 85°C, IP = 20 A – – 63 – – – – 0.18 – – – – – –4 Typ. 250 – 1.5 12 8 – – 700 1 240 2 5 – – 50 65 – 0.042 0.027 20 ±0.5 0.2 –0.148 –0.057 0.15 3.71 VENH IC disabled when VEN < VENL CX in μF, where Cx is the largest capacitance among: CG, COCD, and COPD IFAULT = 3 mA sink current VFAULT = 3.3 V – 2 – 8 × CX – – 100 – – – – – – – 0.55 – 0.4 1 kΩ V V ms V μA Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC OPERATING CHARACTERISTICS (continued) valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted Characteristic Symbol Gate Drive Performance Characteristics Nominal Gate Voltage VGATE Gate Voltage Tolerance ΔVGATE Average GATE Drive Current IGD Charge Pump Switching Frequency fCP GATE Rise Time GATE Sink Resistance7 GATE Sink Steady State Resistance7 GATE Shutdown Delay tGR RGsink RGsink(ss) tGSD Test Conditions TA = 25°C TA = 25°C VCC = 12 V, TA = 25°C TA = 25°C TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF, measured from VGATE = 0 to 15 V, CG pin open, no output load capacitance < 5 μs after gate voltage falls low > 80 μs after gate voltage falls low Min. – – 30 – – – – Typ. VCC + 10 – 50 1 1 20 100 Max. – ±2 70 – – 30 – Units V V μA MHz ms Ω kΩ Measured from fault event to start of GATE pull down – 200 – ns Measured from VGATE = 90% of maximum to VGATE < 1 V, GATE Maximum Fall Time tGF while EN pin switched from high to low, assuming external – 800 – ns MOSFET S1 gate capacitance = 5.8 nF CG Output Current ISLEW TA = 25°C 18 20 22 μA 1 The small signal, ac bandwidth of this device is approximately 90 kHz. 2 This is the 6 σ noise voltage. 3 This test requires currents sufficient to swing the output driver between the fully off state and the saturated state. Assumes that the VIOUT pin is connected to an analog-to-digital converter that saturates at 2.5 V. The VIOUT signal is linear above 2.5 V, however, this test is NOT intended to indicate a range of linear operation. 4 This is the minimum delay time achievable without C OPD or COCD. Longer delay time can be achieved by using COPD or COCD. See Functional Description section for details. Voltage trip point for both the OPDLY and the OCDLY pins is 3.85 V. 5 This parameter is internally programmed and cannot be controlled by the end user. 6 The FAULT output signal is latched. After a latched fault event, the device will be reset only when either: (a) V EN drops below VENL, or (b) the power to the device (applied to the IP+ pins) is toggled off and then back on. 7 The gate resistance switches to high impedance approximately 15 to 45 μs after the gate voltage falls low after a fault. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Functional Description Soft Start and Fault Characteristics Gate turn on rise time, tGR. Set by external capacitance, CG, on the CG pin, such that CG = 7.5 × tGR , where CG is in F and tGR is rise time in seconds. For example, a 3.9 F capacitor connected from the CG pin to GND (without an output load) will yield a rise time of approximately 500 ms: CG  7.5 × 0.5 s = 3.75 F,  3.9 F (a common capacitor value). When the CG pin is kept open, the ACS761 has a minimum tGR of 1 ms typical. It is important to select values for CG and the FET load resistance (RLOADFET) that ensure safe power consumption during FET activation. The combination of a large FET current consumption caused by RLOADFET, and a long gate voltage slew caused by CG, could cause the overall FET power consumption to be outside of its safe operating area during FET activation. IPF fault signal delay, tIPF . This is the delay from high current level fault sense to the start of turn-off of the external MOSFET S1 turn-off. Set by external capacitance, COCD, on the OCDLY pin, such that COCD = 5.17 × trOCD ; where COCD is in F and trOCD is rise time in seconds. When the OCDLY pin is kept open, the IC has a minimum fault delay, tIPFLmax, of 8 s maximum. Load power fault signal delay, tPFL. This is the delay from maximum power level fault, PF(th), sense to the start of external MOSFET S1 turn-off. Set by external capacitance, COPD, on the OPDLY pin, such that COPD = 5.17 × trOPD ; where COPD is in F and trOPD is rise time in seconds. The IC has a minimum fault delay when the OPDLY pin kept open of 10 s typical. Accuracy Characteristics Sensitivity, Sens. The change in device output in response to a 1 A change through the primary conductor. Sens is the product of the magnetic circuit sensitivity (G/A) and the linear IC amplifier gain (mV/G). The linear IC amplifier gain is trimmed at Allegro final test to optimize the sensitivity (mV/A) for the full-scale current range of the device. Noise, VNOISE(PP). The product of the linear IC amplifier gain (mV/G) and the noise floor for the Allegro Hall effect linear IC. Dividing the noise (mV) by the sensitivity (mV/A) provides the smallest current that the device is able to resolve. Nonlinearity, ELIN. The linearity of the VIOUT signal is the degree to which the voltage output from the sensor varies in direct proportion to the primary sensed current, up to 20 A. Nonlinearity reveals the maximum deviation in the slope of the device transfer function compared to the slope of the ideal transfer curve for this transducer. The following equation is used to derive the linearity: 100 1– {[ (VIOUT_full-scale amperes – VIOUT(Q)) 2 (VIOUT_half-scale amperes – VIOUT(Q)) [{ , where full-scale current is 20 A, and half-scale current is 10 A. Zero Current Output Voltage, VIOUT(Q). The output of the sensor when the primary current, IP , is 0 A. Variation in VIOUT(Q) can be attributed to the resolution of the Allegro linear IC quiescent voltage trim and thermal drift. VIOUT Total Error, ETOT. The maximum percentage deviation of the actual output from its ideal value, based on an ideal sensitivity of 65 mV/A over the operating ambient temperature range. PGood Indication. The PGood indication is active high when valid power is applied to the device. PGood activates approximately 500 ms after the FB+ voltage reaches its VPGOODON threshold. PGood will not release until 500 ms after the FB+ voltage drops below its VPGOODOFF threshold. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Overpower Fault Operation The timing diagram in figure 1 shows characteristic operation of the ACS761 when the power consumed from the 12 V system bus exceeds Overpower Fault Threshold, PF(th). The system power supply bus reaches the nominal steady state level of 12 V before the EN pin (Enable pin, active high) of the ACS761 transitions to the high state at time tEN1. Note that, when the EN pin is in the low state, the GATE pin is actively pulled low. However, as shown in the timing diagram, the voltage on the GATE pin increases with a positive slope after the EN pin transitions to the high state. The ramp rate of the GATE pin is controlled by the value of the capacitor connected to the CG pin. At a certain GATE voltage, current begins to flow through the external protection MOSFET, S1, and this current increases as the GATE voltage increases. The voltage at the VIOUT pin, which is the current device output voltage of the ACS761, proportionally tracks the current that flows through the MOSFET. In the timing diagram, the system is in normal, steady state operation up until the time tINIT_F. At tINIT_F , the current load on the 12 V power supply increases from 19.2 to 22 A and the ACS761 internally registers an overpower fault condition. At this time, the voltage on the OPDLY pin increases with a constant slope. (This slope is controlled by the value of the capacitor connected to the OPDLY pin). This voltage continues to increase with a constant slope until either: • The OPDLY pin voltage reaches a threshold of 3.85 V (if this ¯ ¯¯¯ occurs, the ¯ ¯ ¯ ¯ ¯ signal is latched in the low state), or FAULT • The power consumption of the system falls below PF(th) (at which time the OPDLY pin voltage is pulled to ground) An overpower fault event is detected at tOP_F. At this time, ¯ ¯¯¯ the ¯ ¯ ¯ ¯ ¯ signal transitions to the low state and the GATE FAULT ¯ ¯¯¯ pin is pulled to ground. The ¯ ¯ ¯ ¯ ¯ signal is latched and the FAULT chip will pull down the GATE voltage until the EN pin of the 1.83 V 0.2 V VIOUT Voltage 22 A Load Current /IP GATE Voltage 0.4 V ≈0V 0V 0V 3.85 V Threshold 0V 0V 12 V tEN1 tINIT_F t0P_F Time Figure 1. Timing Diagram for Overpower Fault tRESET OCDLY Pin Voltage Voltage on IP+ Pins CG Pin Voltage VLOAD to Load OPDLY Pin Voltage 5.5 V FAULT EN 3.3 V 5.5 V 12 V 19.2 V 22 V 1.648 V 0A 0V 3.3 V Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC ACS761 transitions to the low state and then back to the high state. As shown in the timing diagram, certain ACS761 signals ¯ ¯¯¯ (the ¯ ¯ ¯ ¯ ¯ signal and the OPDLY pin voltage) are reset when FAULT the EN pin transitions to the low state. These signals are reset in order to guarantee normal device operation (soft start and fault monitoring) when the EN signal transitions back to the high state. Soft Short Circuit Fault Operation The timing diagram in figure 2 shows the characteristic operation of the ACS761 when the current load on the 12 V system bus jumps from the 19-to-20 A level to the 40 A level. The 40 A load is typically indicative of a soft short circuit on the ILOAD side of the external MOSFET. In figure 2, the system power supply bus reaches the nominal steady state level of 12 V before the EN pin (Enable pin, active high) of the ACS761 transitions to the high state at time tEN1. Note that when the EN pin is in the low state, the GATE pin is actively pulled low. However, as shown in the timing diagram, the voltage on the GATE pin increases with a positive slope after the EN pin transitions to the high state. The ramp rate of the GATE pin is controlled by the value of the capacitor connected to the CG pin. At a certain GATE voltage, current begins to flow through the external protection MOSFET, S1, and this current increases as the GATE voltage increases. The voltage at the VIOUT pin, which is the current device output voltage of the ACS761, proportionally tracks the current that flows through the MOSFET. In the figure 2, the system is in normal, steady state operation up until the time tINIT_F. At tINIT_F the current load on the 12 V power supply increases from 19.2 A to 40 A , reached at t40A_F at which the ACS761 internally registers both an overpower fault and an overcurrent fault. At tINIT_F, the voltage on the OPDLY and OCDLY pins increases with a constant slope. The slope of the voltage on the two delay pins is controlled by the value of the capacitor connected to each pin. In this case the capacitor on the OCDLY pin is smaller than the capacitor on the OPDLY pin and the voltage on the OCDLY pin ramps much faster than the voltage on the OPDLY pin (both pins are connected to separate 20 μA current 3V 0.2 V 40 A 0A 0V 3.3 V 0.4 V ≈0V 0V 0V 0V 3.85 V Threshold tINIT_F t40A_F Time tRESET OCDLY Pin Voltage Voltage on IP+ Pins 5.5 V CG Pin Voltage VLOAD to Load OPDLY Pin Voltage Load Current /IP GATE Voltage FAULT EN VIOUT Voltage 1.648 V 19.2 V 22 V 3.3 V 5.5 V 12 V 0V 12 V tEN1 Figure 2. Timing Diagram for 30 to 40 A Load Fault Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC sources). The voltages on each delay pin continues to increase with a constant slope until: • either the OPDLY or the OCDLY pin voltage reaches a thresh¯¯ ¯ ¯ ¯ ¯ ¯¯¯ old of 3.85 V (if this occurs, the FAULT signal is latched in the low state), or • the current load of the system falls below 20 A for the OPDLY pin and 40 A for the OCDLY pin. In figure 2 a short circuit fault event is detected at t40A_F . At ¯¯ ¯ ¯ ¯ ¯ ¯¯¯ this time, the FAULT signal transitions to the low state and the ¯ ¯¯¯ GATE pin is pulled to ground. The ¯ ¯ ¯ ¯ ¯ state is latched and FAULT the chip will pull down the GATE voltage until the EN pin of the ACS761 transitions to the low state and then back to the high state. As shown in the timing diagram, certain ACS761 signals ¯¯ ¯ ¯ ¯ ¯ ¯¯¯ (the FAULT signal and the OCDLY pin voltage) are reset when the EN pin transitions to the low state. These signals are reset in order to guarantee normal device operation (soft start and fault monitoring) when the EN signal transitions back to the high state. Hard Short Circuit Fault Operation The timing diagram in figure 3 specifically shows characteristic operation of the ACS761 when the device is powered on (via the EN pin) and a 50 m short circuit is present from load side of the external MOSFET, S1, to ground. In figure 3 the system power supply bus reaches the nominal steady state level of 12 V before the EN pin of the ACS761 transitions to the high state at time tEN1. The voltage on the GATE pin increases with a positive slope after the EN pin transitions to the high state. The ramp rate of the GATE pin is controlled by the value of the capacitor connected to the CG pin. In the example shown below a small capacitor is connected to the CG pin and the pin ramps to 5.5 V in < 10 s. In panel A of figure 3, the device is enabled into a 50 m short circuit. Therefore, as the GATE voltage increases the current through the external MOSFET increases at a rapid rate. In this example, it is assumed that there is no capacitor on the OCDLY pin. When the current through the MOSFET exceeds 5.25 V 0.2 V 40 A 0V 3.3 V VIOUT Voltage Load Current /IP GATE Voltage FAULT 0.4 V EN 1.648 V 0.2 V 130 A 40 A VIOUT Voltage Load Current /IP GATE Voltage FAULT 0.4 V EN 1.648 V 0A 22 V 0V 3.3 V 3.3 V ≈0V 5.5 V 12 V 0V 0V 0V 5.5 V 0V 12 V 19.2 A 22 V 3.3 V 5.5 V 12 V ≈0V 0V 0V 0V 3.85 V Threshold tEN1 CG Pin Voltage VLOAD to Load OPDLY Pin Voltage OCDLY Pin Voltage Voltage on IP+ Pins t40A_F tGATE_LOW CG Pin Voltage VLOAD to Load 3.85 V Threshold 3.85 V Threshold OPDLY Pin Voltage OCDLY Pin Voltage Voltage on IP+ Pins tEN1 t40A_F t130A_F tGATE_LOW tRESET 40 A but < 130 A) may flow through the MOSFET for tens of microseconds before the Short Circuit Fault Threshold trips. ¯ ¯¯¯ When tripped, the ¯ ¯ ¯ ¯ ¯ signal is latched and the chip will pull FAULT down the GATE voltage until the EN pin of the ACS761 transitions to the low state and then back to the high state. Certain ACS761 signals (soft start and fault monitoring related) are reset when the EN pin transitions to the low state. These signals are reset in order to guarantee normal device operation when the EN signal transitions to the high state. Determining the Root Cause of an ACS761 Fault Event The Fault Condition Truth Table provides system debugging information in the event of a fault event during use of the ACS761. Note that for all of the fault conditions listed, it is possible to monitor the voltages of various ACS761 output pins and ¯ ¯¯¯ determine the cause of the ACS761 ¯ ¯ ¯ ¯ ¯ event. FAULT Fault Condition Truth Table Pin Logic State EN Pin High High High ¯ ¯¯ ¯ ¯ ¯ UL ¯ ¯ FA¯ ¯ T Pin Low Low Low OPDLY Pin High Low Low OCDLY Pin Low High Low Probable Root Cause Device Overpower Fault Threshold, PF(th), exceeded Device IP Overcurrent Fault Threshold, IOC, exceeded Device IP Short Circuit Fault Threshold, IPF, exceeded Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Application Information Current Mode Operation The ACS761 can be set to ignore a Power Mode fault condition to operate in pure Current Mode. This can be done by grounding the OPDLY pin to disable the overpower fault condition. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 ACS761ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC Package LF, 24-pin QSOP 8.66 ±0.10 24 8º 0º 0.25 0.15 2.30 3.91 ±0.10 A 5.99 ±0.20 5.00 1.27 0.41 1 2 Branded Face 24X 0.20 C 0.30 0.20 0.635 BSC 0.25 MAX 1.75 MAX C 1.04 REF 0.25 BSC SEATING PLANE GAUGE PLANE 0.40 B 0.635 PCB Layout Reference View SEATING PLANE NNNNNNNNNNNNN TLF-AAA LLLLLLLLLLL For Reference Only, not for tooling use (reference JEDEC MO-137 AE) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC7351 SOP63P600X175-24M) Standard Branding Reference View N = Device part number T = Temperature code LF = (Literal) Package type A = Amperage All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion Copyright ©2008-2009, Allegro MicroSystems, Inc. The products described herein are manufactured under one or more of the following U.S. patents: 5,619,137; 5,621,319; 6,781,359; 7,075,287; 7,166,807; 7,265,531; 7,425,821; or other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14