APS11900
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
2
-
FEATURES AND BENEFITS
• ASIL A functional safety
□ Developed in accordance with ISO 26262:2011
(pending assessment)
□ Internal diagnostics and a defined Safe State
□ A2-SIL™ documentation available
• Highly programmable
□ Magnetic polarity, switch points, and hysteresis
□ Temperature coefficient (supports SmCo, NdFeB, and
ferrite magnets)
□ Output polarity and current levels
• Reduces module bill of materials (BOM) and assembly
cost
□ Integrated overvoltage clamp (40 V load dump) and
reverse-battery diode
□ Integrated series resistor and bypass capacitor
(UC package)
□ Enables PCB-less sensor modules
• Automotive-grade ruggedness and fault tolerance
□ Extended AEC-Q100 qualification
□ Operation from –40°C to 175°C junction temperature
□ 3 to 24 V operating voltage range
□ High EMC/ESD immunity
□ Overtemperature indication
PACKAGES
3-pin SOT23-W (LH)
3-pin ultramini SIP (UA)
DESCRIPTION
APS11900 devices are highly programmable, two-wire planar
Hall-effect sensor integrated circuits (ICs) developed in accordance
with ISO 26262:2011 (pending assessment). They include internal
diagnostics and support a functional safety level of ASIL A. The
enhanced two-wire current-mode interface provides interconnect
open/short diagnostics and adds a Safe State to communicate
diagnostic information while maintaining compatibility with
legacy two-wire systems. Two-wire sensors are well-suited to
safety applications, especially those involving long wire harnesses.
Programming can be performed at end of line to optimize the
sensor on a per unit or per module basis. The user can select the
magnetic switch points, temperature coefficient, and hysteresis,
and whether the device responds to north or south magnetic fields
(unipolar switch) or both (bipolar latch or omnipolar switch). The
response can be matched to SmCo, NdFeB, or low-cost ferrite
magnets. There is a choice of two output current levels and either
output polarity. In addition to a benchtop programmer (ASEK)
for development and evaluation, universal software drivers are
available to facilitate programming in a production environment.
Continued on the next page…
TYPICAL APPLICATIONS
• Automotive and industrial safety systems
• Seat position detection
• Seat belt buckles
• Hood/trunk/door latches
• Sunroof/convertible top/tailgate/liftgate actuation
• Brake/clutch pedals
• Electric power steering (EPS)
• Transmissions and shift selectors
• Wiper motors
3-pin SIP (UC)
Not to scale
VCC
VINT
68 Ω
0.1 µF
Regulator
UVLO
EEPROM
Controller
ICC Adjust
0.01 µF
Clock Generator
UC Package
Only
Switch Point
Control
Dynamic Offset
Cancellation
LH and UA
Packages
Only
Output
Polarity
Amp
Low-Pass
Filter
Functional Block Diagram
APS11900-DS, Rev. 6
MCO-0000401
Temp
Comp
GND
October 27, 2021
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
DESCRIPTION (continued)
APS11900 sensors are engineered to operate in the harshest
environments with minimal external components. They are qualified
beyond the requirements of AEC-Q100 Grade 0 and will survive
extended operation at 175°C junction temperature. These monolithic
ICs include on-chip reverse-battery protection, overvoltage protection
(40 V load dump), ESD protection, overtemperature detection, and an
internal voltage regulator for operation directly from an automotive
battery bus. These integrated features reduce the end-product billof-materials (BOM) and assembly cost.
The available SIP package with integrated discrete components
(UC) enables PCB-less applications by incorporating all of the EMC
protection components into the IC package. Other package options
include industry-standard surface-mount SOT (LH) and throughhole SIP (UA) packages. All three packages are RoHS-compliant
and lead (Pb) free with 100% matte-tin-plated leadframes.
For situations where a functionally equivalent but factory-programmed
two-wire switch or latch is preferred, refer to the APS11500 and
APS12400 device families, respectively.
SELECTION GUIDE
Operating Ambient Temperature,
TA (°C)
Part Number
Package
Packing [1]
APS11900LLHALT
3-pin SOT23-W surface mount
7-inch reel, 3000 pieces/reel
APS11900LLHALX
3-pin SOT23-W surface mount
13-inch reel, 10000 pieces/reel
APS11900LUAA
3-pin SIP through-hole
Bulk, 500 pieces/bag
APS11900LUCDTN
3-pin SIP through-hole
with integrated passive components
13-inch reel, 4000 pieces/reel
[1] Contact Allegro
–40 to 150
for additional packing options.
SPECIFICATIONS
RoHS
COMPLIANT
ABSOLUTE MAXIMUM RATINGS
Rating
Unit
Supply Voltage [1]
Characteristic
Symbol
VCC
40
V
Reverse Supply Voltage
VRCC
–23
V
Magnetic Flux Density
Notes
B
Unlimited
G
Maximum Number of EEPROM
Write Cycles
EEPROMW(max)
100
cycles
Maximum Junction Temperature
TJ(max)
165
°C
175
°C
–65 to 170
°C
Storage Temperature
For 500 hours
Tstg
[1] This
rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings
specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.
INTERNAL DISCRETE COMPONENT RATINGS (UC Package Only)
Characteristics
Component
Symbol
Test Conditions
Resistor
RSERIES
In series with VCC
Capacitor
CSUPPLY
Connected between VCC and GND
Rated Nominal
Rated
Resistance/Capacitance Voltage
Rated
Tolerance
Rated Temp.
Range
Rated Power
Handling
68 Ω
50 V
±15%
–
1/8 W
100 nF
50 V
±10%
X7R
–
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
PINOUT DIAGRAMS AND TERMINAL LIST TABLES
3
Terminal List Table (LH, UA Packages)
Number
Package Name
Function
LH
UA
1
VCC
VCC
Supply voltage
2
GND
GND
Ground terminal
3
GND
GND
Ground terminal
Note: For best performance, tie Pins 2 and 3 together
close to the IC.
1
2
1
LH Package, 3-Pin SOT23W Pinout
2
3
UA Package, 3-Pin SIP Pinout
Terminal List Table (UC Package)
Number
1
Package Name
UC
Function
VCC
Supply voltage
2
VINT
This pin reflects the internal
voltage, VINT, after the
internal series resistor. This
pin should be kept floating.
3
GND
Ground terminal
100 nF
68 Ω
1
2
3
UC Package, 3-Pin SIP Pinout
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
CBYP = 0.01 µF, unless otherwise specified
Characteristics
Supply Voltage
Symbol
–
24
V
4.4 [4]
–
24
V
LH and UA
packages
–
2.6
–
V
UC package
–
3.5
–
V
LH and UA
packages
–
2.3
–
V
UC package
–
3.2
–
V
5
–
6.9
mA
ICC(L2)
2
–
5
mA
ICC(H)
12
–
17
mA
Safe current state; indicates overtemperature or
EEPROM error
–
–
1.8
mA
No bypass capacitor; CL [5] = 20 pF
LH and UA
packages
–
50
–
mA/µs
–
0.22
–
mA/µs
UC package
–
0.22
–
mA/µs
–
–
70
µs
ISAFE
dI/dt
After POK, when VCC drops below this
voltage, output is forced to POS
ICC(L1) is the default ICC(L) current
CBYP = 100 nF; CL [5] = 20 pF
Internal bypass capacitor; CL
Chopping Frequency
3.0
After power-on, as VCC increases, output
is forced to POS until this voltage is
reached
ICC(L1)
Power-On State
Unit
UC package
VCC(UV)EN
[7]
Max.
Operating, TJ < 165°C
Undervoltage Lockout [4]
Power-On Time [6]
Typ. [3]
Operating, TJ < 165°C
VCC(UV)DIS
Output Slew Rate
Min.
LH and UA
packages
VCC
Supply Current
Test Conditions
tPO
POS
[5]
t < tPO, VCC ≥ VCC(UV)EN
fC
Output Jitter (p-p)
= 20 pF
VCC ≥ VCC(min), B > BOP(max), B < BRP(min)
ICC(H)
mA
–
800
–
kHz
1 kHz square wave signal
–
5
–
µs
ON-BOARD PROTECTION
Supply Zener Clamp Voltage
VZ
ICC = ICC(H) + 1 mA, TA = 25°C
40
–
–
V
Reverse Supply Zener Clamp
Voltage
VRZ
ICC = –1 mA
–
–
–23
V
Overtemperature Shutdown
TSD
Temperature increasing
–
205
–
°C
Overtemperature Hysteresis
TJHYS
–
25
–
°C
Typical data is at TA = 25°C and VCC = 12 V unless otherwise noted; for design information only.
UC minimum VCC is higher to accommodate voltage drop in the internal series resistor. UC package minimum VCC is higher to accommodate
voltage drop in the internal series resistor. This also affects the VCC(UV).
[5] C – scope capacitance.
L
[6] Measured from V
CC ≥ VCC(min) to valid output.
[7] Power-on state is defined only when V
CC slew rate 1 V/s or greater
[3]
[4]
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
CBYP = 0.01 µF, unless otherwise specified
Characteristics
Initial Operate Point
BOP(init)
Programmable Magnetic
Operating Point
Average Magnetic Step
Symbol
Size [11]
BOP(range)
Test Conditions
Min.
Typ. [9]
Max.
Unit [10]
TA = 25°C
60
Switch Mode, TA = 25°C; 8 bits
±10
80
100
G
–
±600
Latch Mode, TA = 25°C; 8 bits
±20
G
–
±600
G
BOP(STEP)
TA = 25°C
2
3
4.5
G
BHYS(init)
TA = 25°C
5
15
30
G
Average Hysteresis
Step Size [12]
BHYS(STEP)
TA = 25°C
1.5
3
5
G
Programmable Hysteresis in
Switch Mode
BHYS(range)
TA = 25°C; 5 bits. Switch mode only. In latch mode,
hysteresis is 2 × BOP
15
–
70
G
TA = 25°C
45
–
85
G
00: Flat
–
0
–
%/°C
01: SmCo
–
–0.035
–
%/°C
10: NdFeB
–
–0.12
–
%/°C
11: Ferrite. This is the default value.
–
–0.2
–
%/°C
TA = –40°C; default programming, ferrite temperature
coefficient
65
–
113
G
TA = 150°C; default programming, ferrite temperature
coefficient
49
–
80
G
TA = –40°C; default programming: BOP(init) = 80 G (typ) at
25°C and ferrite temperature coefficient
51
–
98
G
TA = 150°C; default programming: BOP(init) = 80 G (typ) at
25°C and ferrite temperature coefficient
36
–
72
G
TA = –40°C; default programming, ferrite temperature
coefficient
5
–
30
G
TA = 150°C; default programming, ferrite temperature
coefficient
5
–
30
G
Initial Hysteresis
Initial Release Point
Switch Point Temperature
Coefficient
Initial Operate Point Over
Temperature
Initial Release Point Over
Temperature
Initial Hysteresis Over
Temperature
BRP(init)
TCSEL
BOP(init)_T
BRP(init)_T
BHYS(init)_T
Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and a positive value for south-polarity magnetic fields.
[11] B
OP(STEP) is a calculated average from the cumulative programmed bits.
[12] B
HYS(STEP) is a calculated average from the cumulative programmed bits.
[9]
[10]
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
PROGRAMMING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
CBYP = 0.01 µF, unless otherwise specified
Characteristics
Symbol
Switch Point Magnitude
Selection Bits
BOPSEL
Magnetic Polarity Bits
BOPPOL
Unipolar/Omnipolar
Selection Bit
Switch/Latch Selection Bit
UNI
LATCH
Test Conditions
The default value is 0 for south polarity.
These bits configure whether the device operates like a
unipolar or omnipolar switch or latch.
Bit
Description
UNI
LATCH
0
X
Omnipolar Switch
1
0
Unipolar Switch (default setting)
1
1
Latch
Min.
Typ.
Max.
Unit
–
8
–
bit
–
1
–
bit
–
1
–
bit
–
1
–
bit
Magnetic Hysteresis
HYS
If configured as a latch, this selection is ignored and the
hysteresis is 2 × BOPSEL
–
5
–
bit
Output Current Level Selection
ICCL
If this bit = 0, ICCL = ICCL1. This is the default value.
If this bit = 1, ICCL = ICCL2.
–
1
–
bit
The default value is 11 for Ferrite temperature coefficient.
–
2
–
bit
The default value is 0 for Standard output polarity.
See Figure 1.
–
1
–
bit
CUSTID
The default value is 0.
–
10
–
bit
LOCK
The default value is 0.
–
1
–
bit
Temperature Coefficient
Output Polarity Bits
Customer ID
Device Lock Bits
TCSEL
POL
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
RθJA
Package Thermal Resistance
Value
Unit
Package LH, on 1-layer PCB based on JEDEC standard
228
°C/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
110
°C/W
Package UA, on 1-layer PCB with copper limited to solder pads
165
°C/W
Package UC, on 1-layer PCB with copper limited to solder pads
270
°C/W
*Additional thermal information available on the Allegro website.
Maximum Allowable VCC (V)
Power Derating Curve
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
VCC(max)
2-layer PCB, LH package
(RθJA = 110 °C/W)
1-layer PCB, Package UC
(RθJA = 270°C/W)
1-layer PCB, UA package
(RθJA = 165 °C/W)
1-layer PCB, LH package
(RθJA = 228°C/W)
20
40
60
80
100
VCC(min)
120
140
160
180
Ambient Temperature (°C)
Power Dissipation, PD (mW)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Package LH, 2-layer PCB
(RθJA = 110°C/W)
Package UA, 1-layer PCB
(RθJA = 165°C/W)
Package LH, 1-layer PCB
(RθJA = 228°C/W)
Package UC, 1-layer PCB
(RθJA = 270°C/W)
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
CHARACTERISTIC PERFORMANCE DATA
ICC(H) vs. TA
ICC(H) vs. VCC
17
16
VCC (V)
15
3
12
14
15
13
24
12
-50
-20
10
40
70
100
130
Supply Current, ICC(H) (mA)
Supply Current, ICC(H) (mA)
17
16
TA (°C)
15
-40
14
25
150
13
12
160
0
5
10
Ambient Temperature, TA (°C)
ICC(L1) vs. TA
6.5
VCC (V)
6.25
3
6
12
5.75
15
5.5
24
5.25
-20
10
40
70
100
130
Supply Current, ICC(L1) (mA)
Supply Current, ICC(L1) (mA)
6.75
-50
160
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40
25
150
0
5
10
ICC(L2) vs. TA
15
20
25
30
ICC(L2) vs. VCC
5
4.5
VCC (V)
4
3
3.5
12
3
15
2.5
24
-50
-20
10
40
70
100
130
Supply Current, ICC(L2) (mA)
Supply Current, ICC(L2) (mA)
30
Supply Voltage, VCC (V)
5
4.5
-40
3.5
25
3
150
2.5
2
160
TA (°C)
4
0
5
Ambient Temperature, TA (°C)
10
1.75
1.75
1.5
VCC (V)
1.25
1
3
0.75
24
0.5
0.25
-20
10
40
70
100
Ambient Temperature, TA (°C)
130
160
Supply Current, ISAFE (mA)
2
-50
20
25
30
ISAFE vs. VCC
2
0
15
Supply Voltage, VCC (V)
ISAFE vs. TA
Supply Current, ISAFE (mA)
25
TA (°C)
Ambient Temperature, TA (°C)
2
20
ICC(L1) vs. VCC
7
5
15
Supply Voltage, VCC (V)
1.5
TA (°C)
1.25
-40
1
0.75
25
0.5
150
0.25
0
0
5
10
15
20
25
30
Supply Voltage, VCC (V)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
BHYS(STEP) vs. TA
Magnetic Flux Density, BHYS (G)
Magnetic Flux Density, BOP(STEP) (G)
BOP(STEP) vs. TA
4.5
4
3.5
3
2.5
2
-50
-20
10
40
70
100
130
160
5
4.5
4
3.5
3
2.5
2
1.5
-50
-20
10
Ambient Temperature, TA (°C)
105
95
VCC (V)
85
75
3
65
24
55
-50
-20
10
40
70
100
130
160
95
TA (°C)
85
-40
75
25
65
150
55
45
0
5
67
3
56
24
45
70
100
130
Magnetic Flux Density, BRP(init) (G)
Magnetic Flux Density, BRP(init) (G)
VCC (V)
78
40
160
TA (°C)
78
-40
67
25
56
150
45
34
0
5
20
3
15
24
10
70
100
Ambient Temperature, TA (°C)
130
160
Magnetic Flux Density, BHYS(init) (G)
Magnetic Flux Density, BHYS(init) (G)
VCC (V)
40
10
15
20
25
BHYS(init)_T vs. VCC
25
10
25
89
BHYS(init)_T vs. TA
-20
20
Supply Voltage, VCC (V)
30
-50
15
100
Ambient Temperature, TA (°C)
5
10
BRP(init)_T vs. VCC
89
10
160
105
BRP(init)_T vs. TA
-20
130
Supply Voltage, VCC (V)
100
-50
100
115
Ambient Temperature, TA (°C)
34
70
BOP(init)_T vs. VCC
Magnetic Flux Density, BOP(init) (G)
Magnetic Flux Density, BOP(init) (G)
BOP(init)_T vs. TA
115
45
40
Ambient Temperature, TA (°C)
30
25
TA (°C)
20
-40
15
25
150
10
5
0
5
10
15
20
25
Supply Voltage, VCC (V)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
FUNCTIONAL DESCRIPTION
Functional Safety
Operation
The APS11900 was designed in accordance with the international
standard for automotive functional safety, ISO 26262:2011
(pending assessment). This product achieves
an ASIL (Automotive Safety Integrity Level)
2
rating of ASIL A according to the standard. The
APS11900 is classified as a SEooC (Safety
Element out of Context) and can be easily
integrated into safety-critical systems requiring
higher ASIL ratings that incorporate external diagnostics or use
measures such as redundancy. Safety documentation will be
provided to support and guide the integration process. Contact
your local FAE for A2-SIL™ documentation: www.allegromicro.
com/ASIL.
The APS11900 devices are two-wire EEPROM-based fieldprogrammable planar Hall-effect devices. The user can select
whether the device should respond to a north or south magnetic
field (unipolar) or both (bipolar or omnipolar). There is a choice
of two output current levels, ICC(L1) and ICC(L2), and the user can
determine which output state applies, ICC(L) or ICC(H), when the
magnetic field is present.
-
The difference between the magnetic operate and release points
is the hysteresis, BHYS. Hysteresis allows clean switching of the
output even in the presence of external mechanical vibration and
electrical noise. The user can program the desired hysteresis level
when configured as a switch. When configured as a latch, the
hysteresis is automatically set to double the programmed operating point, BOP.
The APS11900 has internal diagnostics to check the voltage
supply (an undervoltage lockout regulator) and to detect
overtemperature conditions. See the Diagnostics section for more
information.
BHYS
0
BOPS
Switch to High
0
B+
BHYS
ICC(L)
0
BOPS
BRPN
B-
BRPS
BRPN
BOPS
BRPN
Switch to Low
Switch to Low
Switch to Low
ICC(L)
ICC(L)
BRPS
0
ICC(H)
Switch to Low
Switch to High
BHYS
0
BOPN
BOPN
B-
I+
ICC(H)
ICC(H)
Switch to High
ICC(L)
Unipolar South
Switch to High
ICC(H)
B+
BHYS
Omnipolar
I+
ICC(L)
0
BHYS
BHYS
Unipolar North
Reversed
Output
Polarity
(POL = 1)
Switch to Low
Switch to High
Switch to High
BHYS
0
B+
BRPS
BRPN
ICC(L)
0
ICC(H)
Switch to High
ICC(L)
B-
Unipolar South
Switch to High
0
BRPS
0
BOPN
BOPN
B-
Switch to Low
ICC(L)
I+
ICC(H)
ICC(H)
BOPS
ICC(H)
Omnipolar
Switch to Low
Standard
Output
Polarity
(POL = 0)
I+
Switch to Low
Unipolar North
Figure 1 shows the potential unipolar and omnipolar options that
APS11900 can be configured for when it is used as a switch.
Figure 2 shows the output options when configured as a latch.
The direction of the applied magnetic field is perpendicular to the
branded face for the APS11900. See Figure 3 for an illustration.
B+
BHYS
Figure 1: Hall Switch Magnetic and Output Current Polarity Options
B- indicates increasing north polarity magnetic field strength, and B+ indicates increasing south polarity magnetic field strength.
Allegro MicroSystems
955 Perimeter Road
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10
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
Latch
I+
ICC(H)
Switch to Low
Switch to High
ICC(L)
0
BOP
B-
BRP
Standard
Output
Polarity
BOPPOL | POL
00
11
B+
BHYS
Latch
I+
Switch to High
ICC(H)
Switch to Low
ICC(L)
BRP
B-
0
BOP
Reversed
Output
Polarity
BOPPOL | POL
01
10
B+
BHYS
Figure 2: Hall Latch Magnetic and Output Current Polarity Options
B- indicates increasing north polarity magnetic field strength, and B+ indicates increasing south polarity magnetic field strength.
A
Y
X
Z
B
Y
X
C
Y
X
Z
Z
Figure 3: Magnetic Sensing Orientations
APS11900 LH (Panel A), UA (Panel B), and UC (Panel C)
Allegro MicroSystems
955 Perimeter Road
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11
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
Power-On Behavior
The APS11900 has an internal voltage regulator with undervoltage lockout. As the device powers up, it stays in the power-on
state (POS) of ICC(H) until the supply voltage exceeds VCC(UV)
DIS. Then the device reads the device configuration registers
from EEPROM and checks that the EEPROM values are valid by
comparing the calculated Error Correction Code (ECC) for each
register against the stored ECC. After tPO, the current consumption is ICC(L) or ICC(H), according to the magnetic field and the
device configuration, as shown in Figure 1 and Figure 2.
Similarly, when the supply voltage decreases, the device returns
to the power on state (POS) when the supply voltage drops below
VCC(UV)EN, as shown in Figure 4.
When the device powers on in the hysteresis range (less than BOP
and higher than BRP), the output corresponds to the power-on
state. In this case, the correct state is attained after the first excursion beyond BOP or BRP.
Key
VCC for LH, UA;
VINT for UC
V
+ mA
ICC(H)(max)
ICC(H) (min)
ICC(L) (max)
ICC(L)(min)
Fault
ICC(H) Range
Fault
ICC(L) Range
Fault
ISAFE
0
Overtemp, ECC Error
Fault
ISAFE Range
Temperature Coefficient and Magnet Selection
0
POS
ICC(H)
ICC
Any value of ICC between the allowed ranges for ICC(H) and ICC(L)
indicates a general fault condition.
Figure 5: Interpreting ICC for System-Level Diagnostics
POS
VCC(min)
VCC(UV)DIS
VCC(UV)EN
V
power-on and after an overtemperature event. There is a LOCK
bit which should be set once end-of-line programming has been
completed. Setting the LOCK bit prevents any change in device
configuration in the field.
Current Undefined
tPO
Output according to
device se�ngs, based
on B
t
POS
Current
Undefined
ICC(Lx)
t
Figure 4: Power-On/UVLO Behavior
Diagnostic Features
When properly supplied, APS11900 always has current flowing at
a specified level: either ICC(H), ICC(L), or ISAFE. Any current outside of these narrow ranges is a fault condition. If there is a short,
current increases so that ICC > ICC(H) (max), outside the valid ICC(H)
range. If there is an open, the current lowers below the ICC(L) (min),
outside the valid output current range. In this way, connectivity
issues between the ECU and the sensor can easily be detected.
Additionally, the APS11900 has an overtemperature feature: if
the junction temperature increases beyond TJF, then the current
is reduced to ISAFE. The device current also changes to ISAFE
if there is an error in the EEPROM ECC which is checked at
The APS11900 allows the user to select the magnetic temperature coefficient to compensate for drifts of SmCo, NdFeB, and
ferrite magnets over temperature—as indicated in the specifications table on page 5. This compensation improves the magnetic
system performance over the entire temperature range. For
example, the magnetic field strength from ferrite decreases as the
temperature increases from 25°C to 150°C. This lower magnetic
field strength means that a lower switching threshold is required
to maintain switching at the same distance from the magnet to the
sensor. Correspondingly, higher switching thresholds are required
at cold temperatures, as low as –40°C, due to the higher magnetic
field strength from the ferrite magnet.
For example, the typical ferrite compensation is –0.2%/°C.
With a 25°C temperature BOP switch point of 80 G, the switch
point changes nominally by –0.2%/°C × 80 × (150°C – 25°C) =
–20 G to 80 G – 20 G = 60 G at 150°C. And at –40°C, the switch
point changes by –0.2%/°C × 80 × (–40°C – 25°C) = 10 G to
80 G + 10 G = 90 G. The APS11900 compensate the switching
thresholds over temperature as described above. It is recommended that system designers evaluate their magnetic circuit over
the expected operating temperature range to ensure the magnetic
switching requirements are met.
Allegro MicroSystems
955 Perimeter Road
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12
APS11900
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
Applications
For the LH and UA packages, an external bypass capacitor (from
0.01 µF to 0.1 µF) should be connected (in close proximity to
the Hall element) between the supply and ground of the device
to reduce both external noise and noise generated by the chopper stabilization. Some applications may require additional EMC
immunity, which is achieved with an enhanced protection circuit.
For example, increasing the bypass capacitor from 0.01 µF to
0.1 µF improves immunity to Powered ESD (ISO 10605) and
Direct Capacitive Coupling.
A series resistor and a 0.1 µF bypass capacitor is integrated into
the UC package, making it easy to achieve an EMC-robust design
with no external components or PCB required.
Note that the bypass capacitor selection directly affects the slew
rate. See the Electrical Characteristics table for the typical slew
rate with 0.1 µF bypass capacitor. A 0.01 µF bypass capacitor slew rate is ten times faster. Typical application circuits are
shown in “Figure 6: Typical Application Circuits” on page 14.
Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, AN27701
• Hall-Effect Devices: Guidelines For Designing Subassemblies
Using Hall-Effect Devices, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and ThroughHole, AN26009
• www.allegromicro.com/ASIL
All are provided on the Allegro website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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13
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
V+
ECU
VCC
APS11900
R SENSE
V SENSE
V+
C BYP
0.1 µF
VCC
C BYP
0.1 µF
A119x
APS11900
GND
V SENSE
ECU
R SENSE
GND
(A) Low-Side Sensing (LH, UA package)
(B) High-Side Sensing (LH, UA package)
ECU
VCC
V+
R SENSE
APS11900
V SENSE
68 Ω
V+
VINT
VCC
APS11900
68 Ω
0.1 µF
VINT
GND
ECU
0.1 µF
V SENSE
R SENSE
GND
(C) Low-Side Sensing (UC package)
(D) High-Side Sensing (UC package)
Figure 6: Typical Application Circuits
Allegro MicroSystems
955 Perimeter Road
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14
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
Chopper Stabilization Technique
A limiting factor for switch point accuracy when using Halleffect technology is the small-signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize
Hall offset.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and package stress. This offset reduction technique is based on a signal
modulation-demodulation process. “Figure 7: Model of Chopper
Stabilization Circuit (Dynamic Offset Cancellation)” illustrates
how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset causing the magnetically induced signal to recover its original spectrum at baseband while the DC offset becomes a highfrequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative
chopper-stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate that
produces higher accuracy, reduced jitter, and faster signal processing. Additionally, filtering is more effective and results in a
lower noise analog signal at the sensor output. Devices such as the
APS11900 that use this approach have an extremely stable quiescent Hall output voltage, are immune to thermal stress, and have
precise recoverability after temperature cycling. This technique is
made possible through the use of a BiCMOS process which allows
the use of low offset and low noise amplifiers in combination with
high-density logic and sample-and-hold circuits.
Regulator
Hall Element
Amp
Sample and
Hold
Clock/Logic
Low-Pass
Filter
Figure 7: Model of Chopper Stabilization Circuit
(Dynamic Offset Cancellation)
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15
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
POWER DERATING
The device must be operated below the maximum junction
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties
of the application.
Thermal Resistance (junction to ambient), RθJA, is a figure of
merit summarizing the ability of the application and the device to
dissipate heat from the junction (die), through all paths to ambient air. RθJA is dominated by the Effective Thermal Conductivity,
K, of the printed circuit board which includes adjacent devices
and board layout. Thermal resistance from the die junction to
case, RθJC, is a relatively small component of RθJA. Ambient air
temperature, TA, and air motion are significant external factors in
determining a reliable thermal operating point.
The following three equations can be used to determine operation
points for given power and thermal conditions.
PD = VIN × IIN
(1)
∆T = PD × RθJA
(2)
TJ = TA + ∆T
(3)
For example, given common conditions: TA = 25°C, VCC = 12 V,
ICC = 6 mA, and RθJA = 110°C/W for the LH package, then:
PD = VCC × ICC = 12 V × 6 mA = 72 mW
∆T = PD × RθJA = 72 mW × 110°C/W = 7.92°C
TJ = TA + ∆T = 25°C + 7.92°C = 32.92°C
Determining Maximum VCC
For a given ambient temperature, TA, the maximum allowable power dissipation as a function of VCC can be calculated.
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA.
Example: VCC at TA = 150°C, package UA, using low-K PCB.
Using the worst-case ratings for the device, specifically: RθJA =
165°C/W, TJ (max) = 165°C, VCC (max) = 24 V, and ICC (max) =
17 mA, calculate the maximum allowable power level, PD (max).
First, using equation 3:
∆T (max) = TJ (max) – TA = 165°C – 150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, from equation 2:
PD (max) = ∆T (max) ÷ RθJA = 15°C ÷ 165°C/W = 91 mW
Finally, using equation 1, solve for maximum allowable VCC for
the given conditions:
VCC (est) = PD (max) ÷ ICC (max) = 91 mW ÷ 17 mA = 5.4 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VCC (est).
If the application requires VCC > VCC(est) then RθJA must by
improved. This can be accomplished by adjusting the layout,
PCB materials, or by controlling the ambient temperature.
Determining Maximum TA
In cases where the VCC (max) level is known, and the system
designer would like to determine the maximum allowable ambient temperature TA (max), for example, in a worst-case scenario
with conditions VCC (max) = 24 V, ICC (max) = 17 mA, and RθJA
= 228°C/W for the LH package using equation 1, the largest possible amount of dissipated power is:
PD = VIN × IIN
PD = 24 V × 17 mA = 408 mW
Then, by rearranging equation 3 and substituting with equation 2:
TA (max) = TJ (max) – ΔT
TA (max) = 165°C – (408 mW × 228°C/W)
TA (max) = 165°C – 93°C = 72°C
Finally, note that the TA (max) rating of the device is 150°C and
performance is not guaranteed above this temperature for any
power level.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
16
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
PROGRAMMING GUIDELINES
Overview
Programming is accomplished by sending a series of input voltage pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL).
The APS11900 family allows the user to write to volatile configuration registers, called shadow registers, to “try” the configuration. Then the device configuration can be written to EEPROM,
nonvolatile memory.
Shadow registers are reset after cycling the supply voltage.
EEPROM has a limited number of write cycles. For this reason,
it is recommended to use the Shadow registers (“Try Mode”) to
determine the correct device configuration.
After the desired device configuration has been determined, write
the values into the device EEPROM and write the lock bit to
prevent further access to the EEPROM.
After power-on, the EEPROM registers are read and the values
are written into the shadow registers as described in the section
“Power-On Behavior” on page 12 of this datasheet.
The following functionality is available through the APS11900
programming interface:
Function
Description
Shadow Register Write
Write volatile configuration registers in “Try Mode”.
Shadow Register Read
Read volatile configuration registers in “Try Mode”.
EEPROM Register Write
Write configuration to non-volatile memory
(EEPROM). Note that EEPROM has limited write
cycles as described in the Absolute Maximum
Specifications table.
EEPROM Register Read
Read non-volatile configuration registers
(EEPROM).
EEPROM Margining
Procedure to validate that the EEPROM bank was
written successfully.
Increment BOP
This mode allows the user to increment BOPSEL
each time a HV pulse is sent.
Decrement BOP
This mode allows the user to decrement BOPSEL
each time a HV pulse is sent.
Increment BHYS
This mode allows the user to increment BHYS
each time a HV pulse is sent.
Decrement BHYS
This mode allows the user to decrement BHYS
each time a HV pulse is sent.
Although any programmable variable power supply can be used
to generate the pulse waveforms, Allegro highly recommends
using the Allegro Sensor IC Evaluation Kit, ASEK-20, available
through your local Allegro sales representative. The manual for
the kit is available for download on the Allegro MicroSystems
website.
For detailed programming instructions, refer to the APS11900
Customer EEPROM Programming manual.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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17
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
Package LH, 3-Pin SOT23W
For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000628, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.125
2.975 –0.075
1.49
Die Rotation
Error 4° Max
+0.020
0.180–0.053
0.96
+0.10
2.90 –0.20
2.40
0.70
+0.19
1.91 –0.06
0.25 MIN
0.38 NOM
Hall Element
(not to scale)
Package Centerline
to Die Centerline ±0.20
8× 10° ±5°
0.25 BSC
Seating Plane
Gauge Plane
0.95 BSC
Lead Foot Centerline
To Package Centerline ±0.18
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branded Face
0.41 ±0.04
C
0.95
PCB Layout Reference View
0.55 REF
0.57 ±0.04
3×
1.00
Package Centerline
to Die Centerline ±0.15
2
1
0.10
4°±4°
Active Area Depth
0.28 ±0.04 mm
3
+0.10
0.05 –0.05
0.40 ±0.10
1.00 ±0.13
SEATING
PLANE
C
XXX
1
Standard Branding Reference View
Line 1 = 3 characters
Line 1: Last 3 digits of Part Number
Branding scale and appearance at supplier discretion
Allegro MicroSystems
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18
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
Package UA, 3-Pin SIP
For Reference Only – Not For Tooling Use
(Reference DWG-0000404, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
Mold gate and tie bar
protrusion zone
Ejector pin flash
protrusion
R0.25 MAX (2×)
5° (2×)
0.56 MAX
NNN
45° (2×)
0.10 MAX
1.52 ±0.05
1.68 MAX
5° (2×)
1
Standard Branding Reference View
+0.08
4.09 –0.05
= Supplier emblem
N = Last three digits of device part number
3.00 ±0.05
2.05 NOM
Mold gate and tie bar
protrusion zone
+0.08
3.02 –0.05
Branding scale and appearance
at supplier discretion.
0.15 MAX
Ejector pin
(far side)
Including gate and
tie bar burrs
3.10 MAX
Sensor element location tolerance
Standard ±0.20
+0.05
0.08 –0.00
0.50 ±0.08 Active Area Depth
Ejector pin flash
protrusion
Sensor element location tolerance
Standard ±0.20
1.44 NOM
Hall Element
(not to scale)
45°
10° (3×)
1.02 MAX
0.79 REF
0.51 REF
0.05 NOM
0.05 NOM
14.99 ±0.25
+0.03
0.41 –0.06
0.10 MAX
0.10 MAX
Dambar Trim Detail
1.27 NOM (2×)
+0.05
0.43 –0.07 (3×)
Allegro MicroSystems
955 Perimeter Road
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19
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
Package UC, 3-Pin SIP
For Reference Only – Not for Tooling Use
(Reference DWG-0000409, Rev. 3)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.545 REF× 2
1.36 REF
B
+0.05
0.10
–0.10
0.15 REF
4×10°
+0.06
4.00
–0.05
0.25 REF × 4
1.50 ±0.05
Detail A
C
Detail A
1.5
4.00
Mold Ejector
Pin Indent
+0.06
–0.07
E
Branded
Face
45°
R 0.20 All Corners
E
A
0.25 REF
0.42 ±0.05
0.30 REF
XXXXX
Date Code
1.27 REF × 2
1
18.00 ±0.10
2
Standard Branding Reference View
0.85 ±0.05
Lot Number
3
Line 1, 2, 3: Max. 5 characters per line
Line 1: 5-digit Part Number
Line 2: 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
12.20 ±0.10
0.25
+0.07
–0.03
Plating Included
A Dambar removal protrusion (12×)
0.38 REF
B
0.25 REF
Gate and tie burr area
C Active Area Depth, 0.38 ±0.05 mm
0.85 ±0.05
1.80
D Branding scale and appearance at supplier discretion
+0.06
–0.07
F
4.00 +0.06
–0.05
R 0.30 All Corners
E
Hall element (not to scale)
F
Molded Lead Bar to prevent damage to leads during shipment
1.50 ±0.05
Allegro MicroSystems
955 Perimeter Road
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20
Two-Wire End-of-Line Programmable
Hall-Effect Switch/Latch
APS11900
REVISION HISTORY
Number
Date
Description
–
March 23, 2018
Initial release
1
April 18, 2018
2
February 4, 2019
3
April 1, 2019
Updated ASIL status (page 1 and 10)
4
April 20, 2020
Updated selection guide (page 2) and minor editorial updates
5
August 26, 2020
Corrected Output Current Selection Level test conditions and added figure note to Output Polarity Bits test
conditions (page 6).
6
October 27, 2021
Updated package drawings (pages 18-20)
Corrected supply current values and plots (pages 4 and 8)
Minor editorial updates
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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21
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