APS12200, APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
2
-
FEATURES AND BENEFITS
• Symmetrical latch switch points
• ASIL A functional safety compliance (pending assessment)
• Automotive-grade ruggedness and fault tolerance
□ Extended AEC-Q100 qualification
□ Reverse-battery and 40 V load dump protection
□ Operation from –40°C to 175°C junction temperature
□ High EMC immunity, ±12 kV HBM ESD
□ Output short-circuit and overvoltage protection
□ Superior temperature stability
□ Resistant to physical stress
• Operation from unregulated supplies, 2.8 to 24 V
• Chopper stabilization
• Solid-state reliability
• Industry-standard packages and pinouts
PACKAGES:
Not to scale
3-pin SIP
(suffix UA)
DESCRIPTION
The APS12200, APS12210, and APS12230 are three-wire, planar
Hall-effect sensor integrated circuits (ICs). These devices were
developed in accordance with ISO 26262:2011 and support a
functional safety level of ASIL A (pending assessment).
This family of precision Hall-effect latch ICs feature extended
AEC-Q100 qualification and are ideal for high-temperature
operation up to 175°C junction temperatures. In addition,
the APS12200/10/30 include a number of features designed
specifically to maximize system robustness, such as reversebattery protection, output current limiter, overvoltage, and
EMC protection.
The single silicon chip includes: a voltage regulator, a Hall
plate, small signal amplifier, chopper stabilization, Schmitt
trigger, and a short-circuit-protected open-drain output. A
south pole of sufficient strength turns the output on; a north
pole of sufficient strength is necessary to turn the output off.
The devices include on-board transient protection for all pins,
permitting operation directly from a vehicle battery or regulator
with supply voltages from 2.8 to 24 V.
Two package styles provide a choice of through-hole or surface
mounting. Package type LH is a modified 3-pin SOT23W
surface-mount package, while UA is a three-pin ultramini SIP
for through-hole mounting. Both packages are lead (Pb) free
and RoHS compliant, with 100% matte-tin-plated leadframes.
3-pin SOT23W
(suffix LH)
Functional Block Diagram
VCC
REGULATOR
Hall
Element
DYNAMIC OFFSET
CANCELLATION
TO ALL SUBCIRCUITS
LOW-PASS
FILTER
HALL
AMP.
SAMPLE, HOLD &
AVERAGING
SCHMITT
TRIGGER
VOUT
CONTROL
CURRENT
LIMIT
GND
APS12200-10-30-DS, Rev. 3
MCO-0000382
July 21, 2021
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
SELECTION GUIDE
Part Number
Packing [1]
Mounting
Branding
APS12200LLHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A14
APS12200LLHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A14
APS12200LUAA
Bulk, 500 pieces/bag
3-pin SIP through hole
A15
APS12210LLHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A16
APS12210LLHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A16
APS12210LUAA
Bulk, 500 pieces/bag
3-pin SIP through hole
A17
APS12230LLHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A19
APS12230LLHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A19
APS12230LUAA
Bulk, 500 pieces/bag
3-pin SIP through hole
A20
BRP (Min)
BOP (Max)
–35 G
35 G
–80 G
80 G
–180 G
180 G
RoHS
COMPLIANT
[1] Contact Allegro
[2] Available
for additional packing options.
through authorized Allegro distributors only.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Forward Supply Voltage
Symbol
Notes
Rating
Units
VCC
30
V
Reverse Supply Voltage [1]
VRCC
–18
V
Output Off Voltage [1]
VOUT
30
V
Output
[1]
Current [2]
IOUT
60
mA
Reverse Output Current
IROUT
–50
mA
B
Unlimited
–
165
°C
Magnetic Flux
Density [3]
Maximum Junction Temperature
Storage Temperature
ESD Voltage [4]
TJ(max)
For 500 hours
Tstg
175
°C
–65 to 170
°C
VESD(HBM)
Human Body Model according to AEC-Q100-002
±12
kV
VESD(CDM)
Charged Device Model according to AEC-Q100-011
±1
kV
VESD(SYS)
ISO 10605, System Level
±15
kV
[1] This
rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings,
specific to the respective transient voltage event.
[2] Through short-circuit current limiting device.
[3] Guaranteed by design.
[4] System level ESD rating based on characterization performed under ISO 10605:2008 (2 kΩ / 330 pF) with the application circuit
shown in Figure 4.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
GND
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
2
3
VOUT
VOUT
1
GND
2
VCC
1
VCC
3
Package UA
Package LH
Terminal List
Name
Number
Description
Package LH
Package UA
Connects power supply to chip
1
1
VOUT
Output from circuit
2
3
GND
Ground
3
2
VCC
VSUPPLY
RLOAD =
1 kΩ
APS122XX
1
CBYP =
0.1 µF
VCC
VOUT
2
VOUT
GND
3
Figure 1: Typical Application Diagram
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage, ambient temperature range TA = –40°C to 150°C, and with
CBYP = 0.1 µF (unless otherwise specified)
Characteristics
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit [2]
2.8
–
24
V
1
2
3
mA
ELECTRICAL CHARACTERISTICS
Forward Supply Voltage
VCC
Supply Current
ICC
Output Leakage Current
IOUTOFF
Output Saturation Voltage
VOUT(SAT)
Output Off Voltage
VOUTOFF
Power-On Time
Power-On State, Output [3]
tON
POS
Operating, TJ < 175°C
VOUTOFF = 24 V, B < BRP
–
–
10
µA
IOUT = 20 mA, B > BOP
–
200
500
mV
B < BRP
–
–
24
V
VCC ≥ VCC(min), B < BRP(min) – 10 G,
B > BOP(max) + 10 G
–
–
25
µs
VCC ≥ VCC(min), t < tON
Low
–
Chopping Frequency
fC
–
800
–
kHz
Output Rise Time [4]
tr
RLOAD = 1 kΩ, CL = 20 pF
–
0.2
2
µs
Output Fall Time [4]
tf
RLOAD = 1 kΩ, CL = 20 pF
–
0.1
2
µs
30
–
60
mA
30
–
–
V
VRCC = –18 V, TA = 25°C
–
–
–5
mA
ICC = ICC(max) + 3 mA, TA = 25°C
30
–
–
V
APS12200
5
20
35
G
TRANSIENT PROTECTION CHARACTERISTICS
Output Short-Circuit Current Limit
Output Zener Clamp Voltage
Reverse Battery Current
Supply Zener Clamp Voltage
IOM
VZoutput
IRCC
VZ
IOUT = 3 mA, TA = 25°C, Output Off
MAGNETIC CHARACTERISTICS
Operate Point
Release Point
BOP
BRP
APS12210
25
50
80
G
APS12230
100
150
180
G
APS12200
–35
–20
–5
G
APS12210
–80
–50
–25
G
APS12230
–180
–150
–100
G
APS12200
10
40
70
G
APS12210
50
100
160
G
Hysteresis
BHYS
APS12230
200
300
360
G
Symmetry
BSYM
BOP + BRP
–27.5
–
27.5
G
Magnetic Offset
BOFF
(BOP + BRP) / 2
–13.75
–
13.75
G
[1] Typical
data are at TA = 25°C and VCC = 12 V.
G (gauss) = 0.1 mT (millitesla).
[3] Guaranteed by device design and characterization.
[4] C = oscilloscope probe capacitance.
L
[2] 1
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions
RθJA
Package Thermal Resistance
Value
Units
Package LH, 1-layer PCB with copper limited to solder pads
228
°C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
connected by thermal vias
110
°C/W
Package UA, 1-layer PCB with copper limited to solder pads
165
°C/W
Power Derating Curve
Maximum Allowable VCC (V)
TJ(max) = 175°C; ICC = ICC(max), IOUT = 0 mA (Output Off)
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
VCC(max)
Package LH, 2-layer PCB
(RθJA = 110 °C/W)
Package UA, 1-layer PCB
(RθJA = 165 °C/W)
Package LH, 1-layer PCB
(RθJA = 228 °C/W)
VCC(min)
25
45
65
85 105 125 145
Temperature (°C)
165
185
TJ(max)
Power Dissipation, PD (mW)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Package LH, 2-layer PCB
(RθJA = 110°C/W)
Package UA, 1-layer PCB
(RθJA = 165°C/W)
Package LH, 1-layer PCB
(RθJA = 228°C/W)
25
45
65
85
105
125
145
165
185
Temperature (°C)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
CHARACTERISTIC PERFORMANCE DATA
Electrical Characteristics
Average Supply Current versus Supply Voltage
Average Supply Current versus Ambient Temperature
4.0
4.0
3.5
3.5
TA (°C)
2.5
-40
2.0
25
1.5
3.0
ICC (mA)
ICC (mA)
3.0
150
1.0
2
6
10
14
VCC (V)
18
22
0.0
26
24
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Low Output Voltage versus Ambient Temperature for IOUT = 20 mA
Average Low Output Voltage versus Supply Voltage for IOUT = 20 mA
500
450
450
400
400
350
TA (°C)
300
-40
250
25
200
150
150
100
VOUT(SAT) (mV)
VOUT(SAT) (mV)
12
1.5
0.5
500
VCC (V)
350
300
2.8
250
200
12
150
24
100
50
0
2.8
2.0
1.0
0.5
0.0
VCC (V)
2.5
50
2
6
10
14
VCC (V)
18
22
26
0
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
CHARACTERISTIC PERFORMANCE DATA (continued)
APS12200 Magnetic Characteristics
Average Operate Point versus Ambient Temperature
Average Operate Point versus Supply Voltage
35
35
30
TA (°C)
25
-40
20
25
15
BOP (G)
BOP (G)
30
2.8
20
12
15
150
24
10
10
5
VCC (V)
25
5
2
6
10
14
VCC (V)
18
22
26
-60
-15
-40
-20
25
-25
60
TA (°C)
80
100
120
140
160
VCC (V)
-15
2.8
-20
12
24
-30
-35
2
6
10
14
VCC (V)
18
22
26
-60
Average Switchpoint Hysteresis versus Supply Voltage
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Switchpoint Hysteresis versus Ambient Temperature
70
70
60
TA (°C)
50
-40
40
25
30
BHYS (G)
60
BHYS (G)
40
-25
150
-30
150
VCC (V)
50
2.8
40
12
24
30
20
20
10
2
6
10
14
VCC (V)
18
22
26
-60
Average BOP + BRP Symmetry versus Supply Voltage
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average BOP + BRP Symmetry versus Ambient Temperature
25
25
20
20
10
TA (°C)
5
-40
0
-5
25
-10
150
-15
BSYM (G)
15
15
BSYM (G)
20
-10
TA (°C)
BRP (G)
BRP (G)
-10
VCC (V)
10
5
2.8
0
12
-5
24
-10
-15
-20
-20
-25
0
-5
-5
10
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
-35
-40
-25
2
6
10
14
VCC (V)
18
22
26
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
160
7
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
CHARACTERISTIC PERFORMANCE DATA (continued)
APS12210 Magnetic Characteristics
Average Operate Point versus Ambient Temperature
TA (°C)
-40
25
BOP (G)
BOP (G)
Average Operate Point versus Supply Voltage
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
150
2
6
10
14
VCC (V)
18
22
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
26
VCC (V)
2.8
12
24
-60
-40
25
BRP (G)
BRP (G)
TA (°C)
150
2
6
10
14
VCC (V)
18
22
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
26
25
BHYS (G)
BHYS (G)
-40
150
6
10
14
VCC (V)
18
22
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
26
60
TA (°C)
80
100
120
140
160
12
24
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
VCC (V)
2.8
12
24
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average BOP + BRP Symmetry versus Ambient Temperature
25
20
20
10
TA (°C)
5
-40
0
-5
25
-10
150
-15
BSYM (G)
15
15
BSYM (G)
40
2.8
Average BOP + BRP Symmetry versus Supply Voltage
25
VCC (V)
10
5
2.8
0
12
-5
24
-10
-15
-20
-20
-25
20
Average Switchpoint Hysteresis versus Ambient Temperature
TA (°C)
2
0
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-40
-25
2
6
10
14
VCC (V)
18
22
26
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
160
8
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
CHARACTERISTIC PERFORMANCE DATA (continued)
APS12230 Magnetic Characteristics
Average Operate Point versus Ambient Temperature
Average Operate Point versus Supply Voltage
TA (°C)
-40
25
BOP (G)
BOP (G)
180
175
170
165
160
155
150
145
140
135
130
125
120
115
110
105
100
150
2
6
10
14
VCC (V)
18
22
180
175
170
165
160
155
150
145
140
135
130
125
120
115
110
105
100
26
VCC (V)
2.8
12
24
-60
-40
25
BRP (G)
BRP (G)
TA (°C)
150
2
6
10
14
VCC (V)
18
22
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
26
25
BHYS (G)
BHYS (G)
-40
150
6
10
14
VCC (V)
18
22
360
350
340
330
320
310
300
290
280
270
260
250
240
230
220
210
200
26
60
TA (°C)
80
100
120
140
160
12
24
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
VCC (V)
2.8
12
24
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average BOP + BRP Symmetry versus Ambient Temperature
25
20
20
TA (°C)
10
5
-40
0
-5
25
-10
150
-15
BSYM (G)
15
15
BSYM (G)
40
2.8
Average BOP + BRP Symmetry versus Supply Voltage
25
VCC (V)
10
5
2.8
0
12
-5
24
-10
-15
-20
-20
-25
20
Average Switchpoint Hysteresis versus Ambient Temperature
TA (°C)
2
0
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
360
350
340
330
320
310
300
290
280
270
260
250
240
230
220
210
200
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
-40
-25
2
6
10
14
VCC (V)
18
22
26
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
160
9
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
FUNCTIONAL DESCRIPTION
OPERATION
The output of these devices switches low (turns on) when a magnetic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see Figure 2). After turn-on, the output voltage is VOUT(SAT) . The output transistor is capable of continuously
sinking up to 30 mA. When the magnetic field is reduced below
the release point, BRP , the device output goes high (turns off)
to VOUTOFF. The difference in the magnetic operate and release
points is the hysteresis, BHYS , of the device. This built-in hysteresis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
POWER-ON BEHAVIOR
Device power-on occurs once tON has elapsed. During the
time prior to tON, and after VCC ≥ VCC(min), the output state is
VOUT(SAT) (Low). After tON has elapsed, the output will correspond with the applied magnetic field for B > BOP or B < BRP.
See Figure 3 for an example.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an output state of VOUT(SAT). The correct state is attained after the first excursion beyond BOP or BRP .
POS
Removal of the magnetic field will leave the device output
latched on if the last crossed switch point is BOP, or latched off if
the last crossed switch point is BRP.
B > BOP, BRP < B < BOP
V
B < BRP
VOUTOFF
VOUT
0
BOP
B–
VOUT
Output State
Undefined for
VCC< VCC(min)
POS
VOUT(SAT )
t
V
VOUT(SAT)
BRP
0
Switch to Low
Switch to High
VOUTOFF
B+
BHYS
VCC
V+
VCC (min)
0
t ON
t
Figure 3: Power-On Timing Diagram
Figure 2: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates increasing north polarity field strength.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
10
APS12200,
APS12210,
and APS12230
FUNCTIONAL SAFETY
High-Temperature Precision Hall-Effect Latches
VPULL-UP
VSUPPLY
2
-
The APS12200, APS12210, and APS12230
were developed in accordance with
ISO 26262:2011 as a hardware Safety Element out of Context (SEooC) with ASIL A capability (pending
assessment) for use in automotive safety-related systems when
integrated and used in the manner prescribed in the applicable
safety manual and datasheet. The APS12200, APS12210, and
APS12230 can be easily integrated into safety-critical systems
requiring higher ASIL ratings that incorporate external diagnostics or use measures such as redundancy. Safety documentation
will be provided to support and guide the integration process. For
further information, contact your local Allegro field applications
engineer or sales representative.
RLOAD =
1 kΩ
A
RS =
100 Ω
APS122XX
1
VCC
VOUT
VOUT
2
A
CBYP =
0.1 µF
A
GND
3
COUT =
4.7 nF
RS and C OUT are recommended for maximum
robustness in an automotive environment.
Figure 4: Enhanced Protection Circuit
APPLICATIONS
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from
internal circuitry. As is shown in Figure 1: Typical Application
Circuit, a 0.1 µF capacitor is required. In applications where
maximum robustness is required, such as in an automobile, additional measures may be taken. In Figure 4: Enhanced Protection
Circuit, a resistor in series with the VCC pin and a capacitor on
the VOUT pin enhance the EMC immunity of the device. It is
up to the user to fully qualify the Allegro sensor IC in their end
system to ensure they achieve their system requirements.
These devices are sensitive in the direction perpendicular to the
branded face, as depicted in Figure 5. For further information,
extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
Figure 5: Sensing Configurations
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
11
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
CHOPPER STABILIZATION
A limiting factor for switch point accuracy when using Halleffect technology is the small signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize Hall
offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on a
signal modulation-demodulation process. Figure 6 illustrates how
it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset, causing the magnetically induced signal to recover its original spectrum at baseband while the DC offset becomes a highfrequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative chopper stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate
that produces higher accuracy, reduced jitter, and faster signal
processing. Additionally, filtering is more effective and results in
a lower noise analog signal at the sensor output. Devices such as
the APS12200, APS12210, and APS12230 that use this approach
have an extremely stable quiescent Hall output voltage, are
immune to thermal stress, and have precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process which allows the use of low offset and
low noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Regulator
Hall Element
Amp
Sample and
Hold
Clock/Logic
Low-Pass
Filter
Figure 6: Model of Chopper Stabilization
(Dynamic Offset Cancellation)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
12
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
POWER DERATING
The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is a relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The resulting power dissipation capability directly reflects upon
the ability of the device to withstand extreme operating conditions. The junction temperature mission profile specified in the
Absolute Maximum Ratings table designates a total operating life
capability based on qualification for the most extreme conditions,
where TJ may reach 175°C.
The silicon IC is heated internally when current is flowing into
the VCC terminal. When the output is on, current sinking into the
VOUT terminal generates additional heat. This may increase the
junction temperature, TJ, above the surrounding ambient temperature. The APS12200, APS12210, and APS12230 are permitted
to operate up to TJ = 175°C. As mentioned above, an operating
device will increase TJ according to equations 1, 2, and 3 below.
This allows an estimation of the maximum ambient operating
temperature.
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 2 mA, VOUT = 185 mV, IOUT = 20 mA (output
on), and RθJA = 165°C/W, then:
PD = (VCC × ICC) + (VOUT × IOUT) =
(12 V × 2 mA) + (185 mV × 20 mA) =
24 mW + 3.7 mW = 27.7 mW
ΔT = PD × RθJA = 27.7 mW × 165°C/W = 4.6°C
TJ = TA + ΔT = 25°C + 4.6°C = 29.6°C
A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA.
For example, given the conditions RθJA = 228°C/W, TJ(max) =
175°C, VCC(max) = 24 V, ICC(max) = 3 mA, VOUT = 500 mV,
and IOUT = 25 mA (output on), the maximum allowable operating
ambient temperature can be determined.
The power dissipation required for the output is shown below:
PD(VOUT) = VOUT × IOUT = 500 mV × 25 mA = 12.5 mW
The power dissipation required for the IC supply is shown below:
PD(VCC) = VCC × ICC = 24 V × 3 mA = 72 mW
Next, by inverting using equation 2:
ΔT = PD × RθJA = [PD(VOUT) + PD(VCC)] × 228°C/W =
(12.5 mW + 72 mW) × 228°C/W =
84.5 mW × 228°C/W = 19.3°C
Finally, by inverting equation 3 with respect to voltage:
TA(est) = TJ(max) – ΔT = 175°C – 19.3°C = 155.7°C
In the above case, there is sufficient power dissipation capability
PD = VIN × IIN
(1) to operate up to TA(est). The example indicates that TA(max)
can be as high as 155.7°C without exceeding TJ(max). Howe ΔT = PD × RθJA
(2) ver, the TA(max) rating of the devices is 150°C; the APS12200,
APS12210, and APS12230 performance is not guaranteed above
TJ = TA + ΔT (3) T = 150°C.
A
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
13
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
Package LH, 3-Pin (SOT-23W)
+0.12
2.98 –0.08
1.49 D
4°±4°
3
A
+0.020
0.180–0.053
0.96 D
+0.10
2.90 –0.20
+0.19
1.91 –0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Gauge Plane
8X 10° REF
B
PCB Layout Reference View
Branded Face
C
1.00 ±0.13
0.95 BSC
Standard Branding Reference View
+0.10
0.05 –0.05
A14
0.40 ±0.10
1
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Active Area Depth, 0.28 mm REF
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
APS12200LLHA
A16
1
APS12210LLHA
A19
1
APS12230LLHA
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
14
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
Package UA, 3-Pin SIP
+0.08
4.09 –0.05
45°
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B
E
C
2.04
1.52 ±0.05
+0.08
3.02 –0.05
1.44
E
10°
Mold Ejector
Pin Indent
E
Branded
Face
A
1.02
MAX
1
2
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element (not to scale)
45°
D Standard Branding Reference View
0.79 REF
A15
1
3
APS12200LUAA
+0.03
0.41 –0.06
14.99 ±0.25
A17
1
+0.05
0.43 –0.07
APS12210LUAA
A20
1
APS12230LUAA
1.27 NOM
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
15
APS12200,
APS12210,
and APS12230
High-Temperature Precision Hall-Effect Latches
Revision History
Number
Date
Description
–
March 6, 2018
Initial release
1
February 11, 2019
2
May 28, 2019
Updated Typical Application Diagram (page 3), Functional Safety section (page 11), and Power Derating
section (page 13).
3
July 21, 2021
Updated ASIL Status to pending assessment
Minor editorial updates
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems
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www.allegromicro.com
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