APS12450
2
-
Three-Wire Hall-Effect Latch with Advanced Diagnostics
FEATURES AND BENEFITS
• Functional safety
□□ Developed in accordance with ISO 26262:2011 to meet
ASIL B requirements (pending assessment)
□□ Integrated background diagnostics for:
○○ Signal path
○○ Regulator
○○ Hall plate and bias
○○ Overtemperature detection
○○ Nonvolatile memory
□□ Defined fault state
• Multiple product options
□□ Magnetic polarity, switchpoints, and hysteresis
□□ Temperature coefficient
□□ Output polarity
• Reduces module bill-of-materials (BOM) and assembly cost
□□ ASIL B sensor can replace redundant sensors
□□ Integrated overvoltage clamp and reverse-battery diode
Continued on the next page…
PACKAGES
3-pin SOT23-W (LH)
DESCRIPTION
The APS12450 three-wire planar Hall-effect sensor integrated
circuits (ICs) were developed in accordance with ISO 26262:2011
as a hardware safety element out of context with ASIL B
capability (pending assessment) for use in automotive safetyrelated systems when integrated and used in the manner
prescribed in the applicable safety manual and datasheet. The
enhanced three-wire interface provides interconnect open/
short diagnostics and a fault state to communicate diagnostic
information while maintaining compatibility with legacy
three-wire systems. The continuous background diagnostics
are transparent to the host system and results in a reduced
fault tolerant time.
The APS12450 product options include magnetic switchpoints,
temperature coefficient, and output polarity. The response can
be matched to SmCo, NdFeB, or low-cost ferrite magnets. For
situations where a functionally equivalent three-wire switch
device is preferred, refer to the APS11450.
Continued on the next page…
TYPICAL APPLICATIONS
3-pin ultramini SIP (UA)
•
•
•
•
•
•
•
Not to scale
Automotive and industrial safety systems
Seat/window motors
Sun roof/convertible top/tailgate/liftgate actuation
Brake and clutch by wire actuators
Engine management actuators
Electric power steering (EPS)
Transmission shift actuator
VCC
REGULATOR
DYNAMIC OFFSET
CANCELLATION
To All Subcircuits
Low-Pass
Filter
HALL
AMP.
SAMPLE, HOLD &
AVERAGING
Schmitt Output
(Internal)
VOUT
SYSTEM DIAGNOSTICS
OUTPUT
CONTROL
CLOCK LOGIC
GND
Functional Block Diagram
APS12450-DS, Rev. 1
MCO-0000562
April 23, 2019
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
FEATURES AND BENEFITS (continued)
DESCRIPTION (continued)
• Automotive-grade ruggedness and fault tolerance
□□ Extended AEC-Q100 Grade 0 qualification
○○ Operation to 175°C junction temperature
□□ 3 to 30 V operating voltage range
□□ ±8 kV HBM ESD
□□ Overtemperature indication
APS12450 sensors are engineered to operate in the harshest
environments with minimal external components. They are qualified
beyond the requirements of AEC-Q100 Grade 0 and will survive
extended operation at 175°C junction temperature.
These monolithic ICs include on-chip reverse-battery protection,
overvoltage protection (e.g., 40 V load dump), ESD protection,
overtemperature detection, and an internal voltage regulator for
operation directly from an automotive battery bus. These integrated
features reduce the end-product bill-of-materials (BOM) and
assembly cost.
Package options include industry-standard surface-mount SOT (LH)
and through-hole SIP (UA) packages. Both packages are RoHScompliant and lead (Pb) free with 100% matte-tin-plated leadframes.
SELECTION GUIDE [1]
Part Number
Package
Packing
APS12450LLHALX-0SLA
3-pin SOT23W surface mount
13-in. reel, 10,000 pieces/reel
APS12450LLHALT-0SLA
3-pin SOT23W surface mount
7-in. reel, 3000 pieces/reel
APS12450LUAA-0SLA
3-pin SIP through-hole
bulk, 500 pieces/bag
APS12450LLHALX-1SLA
3-pin SOT23W surface mount
13-in. reel, 10,000 pieces/reel
APS12450LLHALT-1SLA
3-pin SOT23W surface mount
7-in. reel, 3000 pieces/reel
APS12450LUAA-1SLA
3-pin SIP through-hole
bulk, 500 pieces/bag
APS12450LLHALX-3SLA
3-pin SOT23W surface mount
13-in. reel, 10,000 pieces/reel
APS12450LLHALT-3SLA
3-pin SOT23W surface mount
7-in. reel, 3000 pieces/reel
APS12450LUAA-3SLA
3-pin SIP through-hole
bulk, 500 pieces/bag
[1] Contact Allegro
Output Polarity
(B > BOP)
Temperature
Coefficient
Magnetic
Operate Point,
BOP (typ)
Low
0%/°C
22 G
Low
0%/°C
50 G
Low
0%/°C
150 G
MicroSystems for options not listed in the selection guide.
RoHS
COMPLIANT
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Complete Part
Number Format
Allegro Iden�fier (Device Family)
APS – Digital Posi�on Sensor
Configura�on Op�ons
APS12450 L L H A L T - 0 S L C
Allegro Device Number
12450 – ASIL B Hall-effect Latch
Temperature Coefficient
A – Flat
B – -0.035 %/°C
C – -0.12 %/°C
D – -0.2 %/°C
Output Polarity for B > BOP
H – High (Output Off)
L – Low (Output On)
Opera�ng Mode
S – Unipolar South Sensing
N – Unipolar North Sensing
Device Switch Threshold Magnitude
0 – 22 G BOP, -22 G BRP (typ.)
1 – 50 G BOP, -50 G BRP (typ.)
3 – 150 G BOP, -150 G BRP (typ.)
Instruc�ons (Packing)
LT – 7-in. reel, 3,000 pieces/reel (LH Only)
LX – 13-in. reel, 10,000 pieces/reel (LH Only)
TN – 13-in. reel, 4,000 pieces/reel (UA Only)
(no op�on code) – bulk, 500 pieces/bag (UA only)
Package Designa�on
LHA – 3-pin SOT23W Surface Mount
UAA – 3-pin SIP Through-Hole
Ambient Opera�ng Temperature Range
L – -40°C to +150°C
ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply
Symbol
Notes
Rating
Unit
Voltage [2]
VCC
35
V
Reverse Supply Voltage
VRCC
–30
V
Forward Output Voltage
VOUT
30
V
Reverse Output Voltage
VROUT
–0.3
V
Output Current Sink
Maximum Junction Temperature
Storage Temperature
IOUT(SINK)
TJ(MAX)
Tstg
VCC to VOUT
For 500 hours
12
mA
165
°C
175
°C
–65 to 170
°C
[2] This
rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings
specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
Three-Wire Hall-Effect Latch with Advanced Diagnostics
GND
PINOUT DIAGRAMS AND TERMINAL LIST
LH Package, 3-Pin SOT23W Pinout
2
3
VOUT
1
GND
2
VCC
1
VOUT
3
VCC
APS12450
UA Package, 3-Pin SIP Pinout
Terminal List Table
Name
Pin Number
Function
LH
UA
VCC
1
1
Supply voltage
VOUT
2
3
Output
GND
3
2
Ground
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max),
unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
SUPPLY AND STARTUP
Supply Voltage [2]
VCC
Supply Current
ICC
Power-On Time [3]
ton
Power-On State
POS
Output Rise Time
tRISE
Output Fall Time
tFALL
Output On Voltage
VOUT(LOW)
Output Off Voltage
VOUT(HIGH)
Output Off Voltage Overshoot [4]
Operating, TJ < 165°C
VCC > VCC(min), B < BRP(min) – 10 G,
B > BOP(max) + 10 G
3.0
–
30
V
–
–
4.5
mA
–
–
150
µs
4
15
µs
t < ton(max)
VOUT(FAULT)
See Applications Circuit, Figure 9;
VPU = VCC, RPU = 3 kΩ, COUT = 1 nF, IOUT < 12 mA
Output ratiometric to VPU;
VPU = VCC, τ < 3 µs [5], IOUT < 12 mA
2
–
2
4
15
µs
10
20
30
%
70
80
90
%
VOUT(HIGH)OVER
Overshoot percentage relative to VPU (see Figure 8);
VPU = VCC, τ < 3 µs [5], IOUT < 12 mA
–
2
–
%
tVOUT(H)OVER
Duration of output voltage overshoot (VOUT(HIGH)OVER)
–
–
5
µs
ON-BOARD PROTECTION
Fault Reaction Time
tDIAG
–
25
60
µs
Diagnostics Fault Retry Time [6]
tDIAGF
–
2
–
ms
VPU
–
V
Fault Mode Output Voltage
(Fault State)
VOUT(FAULT)
Overtemperature Shutdown
TSD
Overtemperature Hysteresis
TJHYS
VPU = VCC, τ < 3 µs, IOUT < 12 mA
Temperature increasing
> VOUT(HIGH)
MAX
–
205
–
°C
–
25
–
°C
[1] Typical
data is at TA = 25°C and VCC = 12 V and is for design information only.
[2] V
CC represents the voltage between the VCC pin and the GND pin.
[3] Power-On Time (t
ON) is measured from VCC = VCC(min) to 50% of the output transition
from VPU to final value. Adding a bypass capacitor will
increase Power-On Time.
[4] The overshoot specification pertains only to conditions where the overshoot is greater than the V
OUT(HIGH)MAX specification.
[5] τ is the time constant of the RC circuit; τ = R
PU × COUT.
[6] The diagnostics fault retry repeats continuously until a fault condition is no longer observed. See Diagnostics Mode Operation section for details.
TRANSIENT PROTECTION CHARACTERISTICS: Valid for TA = 25°C and CBYP = 0.1 µF, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
ICC(max) + 3 mA
35
–
–
V
PROTECTION
Forward Supply Zener
Clamp Voltage
VZ
Reverse Supply Zener
Clamp Voltage
VRCC
ICC = –1 mA
–
–
–30
V
Reverse Supply Current
IRCC
VRCC = –30 V
–
–
–5
mA
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max),
unless otherwise specified
Characteristics
Sensitivity Temperature
Coefficient
Symbol
Test Conditions
Relative to sensitivity
at 25°C
TCSENS
Min.
Operate Point
Release Point
Hysteresis
BRP
BHYS
Symmetry
BSYM
Jitter [3]
–
Unit [2]
–
0
–
%/°C
(B) SmCo
–
–0.035
–
%/°C
(C) NdFeB
–
–0.12
–
%/°C
–
–0.2
–
%/°C
–
10
–
kHz
APS12450–0SxA
5
22
40
G
APS12450–1SxA
15
50
90
G
f(-3dB)
BOP
Max.
(A) Flat
(D) Ferrite
Analog Signal Bandwidth
Typ. [1]
APS12450–3SxA
100
150
180
G
APS12450–0SxA
–40
–22
–5
G
APS12450–1SxA
–90
–50
–15
G
APS12450–3SxA
–180
–150
–100
G
APS12450–0SxA
10
45
80
G
APS12450–1SxA
30
100
180
G
APS12450–3SxA
200
300
360
G
BOP + BRP
-30
–
30
G
–
0.25
–
%
BOP = 22 G, B = 100 GPK-PK, 1000 Hz
Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
1 G (gauss) = 0.1 mT (millitesla).
[3] Output edge repeatability as a percentage of the period.
[1]
[2]
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
Value
Unit
Package LH, on 1-layer PCB based on JEDEC standard
228
°C/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
110
°C/W
Package UA, on 1-layer PCB with copper limited to solder pads
165
°C/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
VOUT(HIGH) vs. VCC
90
88
88
86
86
Output Voltage, VOUT(HIGH) (%)
Output Voltage, VOUT(HIGH) (%)
VOUT(HIGH) vs. TA
90
84
82
80
78
76
V CC (V)
74
3
72
70
-20
10
40
70
100
130
82
80
78
TA (°C)
76
-40
74
25
72
30
-50
84
70
160
150
0
5
10
15
Ambient Temperature, TA (°C)
28
28
26
26
24
22
20
18
16
V CC (V)
14
3
12
-20
10
40
70
100
130
20
18
TA (°C)
16
-40
14
10
160
25
150
0
5
10
100
100
Output Voltage, VOUT(FAULT) (%)
Output Voltage, VOUT(FAULT) (%)
102
98
96
94
V CC (V)
3
30
-20
40
70
-40
92
100
130
160
25
150
0
5
10
3.5
Diag Fault Retry Time, tDIAGF (ms)
Diag Fault Retry Time, tDIAGF (ms)
3.5
3
2.5
2
1.5
V CC (V)
3
30
-20
10
40
20
25
30
35
tDIAGF vs. VCC
4
-50
15
Supply Voltage, VCC (V)
tDIAGF vs. TA
0
35
TA (°C)
94
4
0.5
30
96
Ambient Temperature, TA (°C)
1
25
98
90
10
20
VOUT(FAULT) vs. VCC
VOUT(FAULT) vs. TA
-50
15
Supply Voltage, VCC (V)
102
90
35
22
Ambient Temperature, TA (°C)
92
30
24
12
30
-50
25
VOUT(LOW) vs. VCC
30
Output Voltage, VOUT(LOW) (%)
Output Voltage, VOUT(LOW) (%)
VOUT(LOW) vs. TA
30
10
20
Supply Voltage, VCC (V)
70
100
Ambient Temperature, TA (°C)
130
160
3
2.5
2
1.5
TA (°C)
1
-40
25
0.5
0
150
0
5
10
15
20
25
30
35
Supply Voltage, VCC (V)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA (continued)
I CC vs. TA
I CC vs. VCC
4.5
4
4
3.5
3.5
Supply Current, I CC (mA)
Supply Current, I CC (mA)
4.5
3
2.5
2
V CC (V)
3
1.5
12
1
24
0.5
0
-20
2
TA (°C)
1.5
-40
1
25
0.5
30
-50
3
2.5
10
40
70
100
130
150
0
160
0
5
10
15
Ambient Temperature, TA (°C)
20
25
30
35
Supply Voltage, VCC (V)
ton vs. TA
tRISE & tFALL vs. TA
150
15
Rise & Fall Time, tRISE & tFALL (µs)
135
Power-on Time, ton (µs)
120
105
90
75
60
45
30
15
0
-50
-20
10
40
70
100
Ambient Temperature, TA (°C)
130
160
12.5
10
7.5
5
2.5
0
Fall
Rise
-50
-20
10
40
70
100
130
160
Ambient Temperature, TA (°C)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
APS12450–0SxA
BOP(0S_A) vs. VCC
40
35
35
Magnetic Flux Density, BOP (G)
Magnetic Flux Density, BOP (G)
BOP(0S_A) vs. TA
40
30
25
20
15
V CC (V)
3
10
5
30
-50
-20
10
40
70
100
130
30
25
20
-40
25
10
5
160
TA (°C)
15
150
0
5
10
15
Ambient Temperature, TA (°C)
-10
-10
-15
-20
-25
-40
V CC (V)
3
30
-50
-20
10
40
70
100
130
25
150
-20
-25
-30
-35
-40
160
-40
-15
0
5
10
70
70
60
50
40
30
V CC (V)
3
20
30
10
40
70
100
130
-40
25
20
10
160
TA (°C)
30
150
0
5
10
Magnetic Flux Density, BSYM (G)
Magnetic Flux Density, BSYM (G)
20
15
10
5
0
-5
-10
V CC (V)
-15
3
-20
25
30
35
100
Ambient Temperature, TA (°C)
130
15
10
5
0
-5
TA (°C)
-10
-40
-15
25
-20
30
70
20
BSYM(0S_A) vs. VCC
20
40
15
Supply Voltage, VCC (V)
25
10
35
40
BSYM(0S_A) vs. TA
-20
30
50
25
-50
25
60
Ambient Temperature, TA (°C)
-25
20
BHYS(0S_A) vs. VCC
80
Magnetic Flux Density, BHYS (G)
Magnetic Flux Density, BHYS (G)
BHYS(0S_A) vs. TA
-20
15
Supply Voltage, VCC (V)
80
-50
35
TA (°C)
Ambient Temperature, TA (°C)
10
30
BRP(0S_A) vs. VCC
-5
Magnetic Flux Density, BRP (G)
Magnetic Flux Density, BRP (G)
BRP(0S_A) vs. TA
-35
25
Supply Voltage, VCC (V)
-5
-30
20
160
-25
150
0
5
10
15
20
25
30
35
Supply Voltage, VCC (V)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
APS12450–1SxA
BOP(1S_A) vs. VCC
90
82.5
82.5
75
Magnetic Flux Density, BOP (G)
Magnetic Flux Density, BOP (G)
BOP(1S_A) vs. TA
90
67.5
60
52.5
45
37.5
V CC (V)
30
3
22.5
15
-20
10
40
70
100
130
60
52.5
45
TA (°C)
37.5
-40
30
25
22.5
30
-50
75
67.5
150
15
160
0
5
10
Ambient Temperature, TA (°C)
-22.5
-22.5
-30
-30
-37.5
-45
-52.5
-60
V CC (V)
-75
-90
3
-20
-40
25
-37.5
150
-45
-52.5
-60
-67.5
-75
10
40
70
100
130
-90
160
0
5
10
155
155
130
105
80
V CC (V)
55
3
30
10
40
70
100
130
-40
55
30
160
25
150
0
5
10
Magnetic Flux Density, BSYM (G)
Magnetic Flux Density, BSYM (G)
20
15
10
5
0
-5
-10
V CC (V)
-15
3
-20
25
30
35
100
Ambient Temperature, TA (°C)
130
15
10
5
0
-5
TA (°C)
-10
-40
-15
25
-20
30
70
20
BSYM(1S_A) vs. VCC
20
40
15
Supply Voltage, VCC (V)
25
10
35
TA (°C)
80
BSYM(1S_A) vs. TA
-20
30
105
25
-50
25
130
Ambient Temperature, TA (°C)
-25
20
BHYS(1S_A) vs. VCC
180
Magnetic Flux Density, BHYS (G)
Magnetic Flux Density, BHYS (G)
BHYS(1S_A) vs. TA
-20
15
Supply Voltage, VCC (V)
180
-50
35
TA (°C)
Ambient Temperature, TA (°C)
30
30
-82.5
30
-50
25
BRP(1S_A) vs. VCC
-15
Magnetic Flux Density, BRP (G)
Magnetic Flux Density, BRP (G)
BRP(1S_A) vs. TA
-82.5
20
Supply Voltage, VCC (V)
-15
-67.5
15
160
-25
150
0
5
10
15
20
25
30
35
Supply Voltage, VCC (V)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
10
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
APS12450–3SxA
BOP(3S_A) vs. VCC
180
170
170
Magnetic Flux Density, BOP (G)
Magnetic Flux Density, BOP (G)
BOP(3S_A) vs. TA
180
160
150
140
130
V CC (V)
120
3
110
100
30
-50
-20
10
40
70
100
130
160
150
140
130
TA (°C)
120
-40
100
160
25
110
150
0
5
10
15
Ambient Temperature, TA (°C)
-110
-110
-40
-120
25
-120
-130
-140
-150
V CC (V)
-160
-180
3
-20
TA (°C)
150
-130
-140
-150
-160
-170
30
-50
10
40
70
100
130
-180
160
0
5
10
Ambient Temperature, TA (°C)
BHYS(3S_A) vs. TA
340
Magnetic Flux Density, BHYS (G)
340
320
300
280
260
V CC (V)
240
3
220
30
-20
10
40
70
100
130
260
-40
25
220
200
160
TA (°C)
240
150
0
5
10
Magnetic Flux Density, BSYM (G)
20
15
10
5
0
-5
-10
V CC (V)
-15
3
-20
25
30
35
100
Ambient Temperature, TA (°C)
130
15
10
5
0
-5
TA (°C)
-10
-40
-15
25
-20
30
70
20
BSYM(3S_A) vs. VCC
20
40
15
Supply Voltage, VCC (V)
25
10
35
280
BSYM(3S_A) vs. TA
-20
30
300
25
-50
25
320
Ambient Temperature, TA (°C)
-25
20
BHYS(3S_A) vs. VCC
360
-50
15
Supply Voltage, VCC (V)
360
200
35
BRP(3S_A) vs. VCC
-100
Magnetic Flux Density, BRP (G)
Magnetic Flux Density, BRP (G)
30
-100
-170
Magnetic Flux Density, BHYS (G)
25
Supply Voltage, VCC (V)
BRP(3S_A) vs. TA
Magnetic Flux Density, BSYM (G)
20
160
-25
150
0
5
10
15
20
25
30
35
Supply Voltage, VCC (V)
Allegro MicroSystems
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11
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
FUNCTIONAL DESCRIPTION
The difference between operate (BOP) and release (BRP) points is
the hysteresis (BHYS). Hysteresis allows clean switching of the
output even in the presence of external mechanical vibration and
electrical noise. The hysteresis is set to double the programmed
operating point.
Standard Polarity
V+
VOUT(HIGH)
Figure 1 shows the potential unipolar and omnipolar options and
output polarity options of the APS12450 that can be configured.
The direction of the applied magnetic field is perpendicular to the
branded face of the APS12450 (see Figure 2).
V+
Inverted Polarity
VOUT(HIGH)
Switch to High
VOUT
Switch to Low
Switch to High
Note that this device latches; that is, a south pole of sufficient
strength towards the branded face of the device turns the device
on, and the device remains on with removal of the south pole.
Switch to Low
The output of these devices switches when a magnetic field perpendicular to the Hall-effect sensor exceeds the operate point threshold
(BOP). When the magnetic field is reduced below the release point
(BRP), the device output switches to the alternate state. The output
state (polarity) and magnetic field polarity depends on the selected
device options. The device is a latch, therefore BOP and BRP will be
in opposite magnetic field polarities.
Figure 1 shows the output switching behavior relative to increasing and decreasing magnetic field. On the horizontal axis, the
B+ direction indicates increasing south polarity magnetic field
strength. Figure 2 shows the sensing orientation of the magnetic
field, relative to the device package.
VOUT
Operation
VOUT(LOW)
BOPS
B–
(north)
BHYS
0
BRPS
B+
(south)
BOPS
VOUT(LOW)
0
BRPS
B(north)
B+
(south)
BHYS
Figure 1: Hall latch magnetic and output polarity options
B- indicates increasing north polarity magnetic field strength, and
B+ indicates increasing south polarity magnetic field strength.
A
Y
X
Z
B
Y
X
Z
C
Y
X
Z
Figure 2: Magnetic Sensing Orientations
APS12450 LH (Panel A), APS12450 UA (Panel B)
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12
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
FUNCTIONAL SAFETY
The APS12450 was developed in accordance with ISO 26262:2011
as a hardware safety element out of context with ASIL B capability
(pending assessment) for use in automotive safety-related systems
when integrated and used in the manner prescribed in the applicable safety manual and datasheet.
Diagnostics Mode Operation
The APS12450 features a proprietary diagnostics routine that
meets ASIL B safety requirements (pending assessment). This
internal diagnostics routine continuously runs in the background,
monitoring all key subsystems of the IC. These subsystems are
shown in Table 1 and Figure 3. The diagnostic scheme runs at
high speed and provides minimal impact on device performance.
Signal path diagnostics are injected and measured in less than
2 μs, while all other diagnostics are running in real time in the
background. The Hall element biasing circuit and voltage regulator are checked for valid operation, and the digital and non‐volatile memory blocks are checked for valid device configuration.
The signal path monitoring system verifies two internal state
transitions (BOP and BRP within limits) under normal operation.
In cases when these output transitions do not occur, or if another
internal fault is detected, the output will go to the fault state (see
“Three-Wire Diagnostic Output” section).
In the event of an internal fault, the device will continuously run
the diagnostics routine every 2 ms (tDIAGF). The periodic recovery attempt sequence allows the device to continually check for
the presence of a fault and return to normal operation if the fault
condition clears.
In the case where the fault is no longer present, the output will
resume normal operation. However, if the fault is persistent, the
device will not exit fault mode and the output voltage will continue to be VOUT(FAULT).
When a system rating higher than ASIL B is required, additional
external safety measures may be employed (e.g., sensor redundancy and rationality checks, etc.). Refer to the device safety
manual for additional details about the diagnostics.
Table 1: Diagnostics Coverage
Feature
Coverage
1
Hall plate
Connectivity and biasing of Hall plate
2
Signal path
Signal path and Schmitt trigger
3
Voltage regulator
Regulator voltage for normal operation
4
Digital subsystem
Digital subsystem and non-volatile memory
5
Entire system
Overtemperature and redundancies for single point failures
6
Output
Output verified through valid regulations states (external monitor)
VCC
3
5
REGULATOR
DYNAMIC OFFSET
CANCELLATION
To All Subcircuits
1
Low-Pass
Filter
2
HALL
AMP.
SAMPLE, HOLD &
AVERAGING
Schmitt Output
(Internal)
4
SYSTEM DIAGNOSTICS
VOUT
6
OUTPUT
CONTROL
CLOCK LOGIC
GND
Figure 3: Diagnostics Coverage Block Diagram
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13
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Power-On Behavior
Temperature Coefficient and Magnet Selection
During Power-on, the output voltage is in the fault state
(VOUT(FAULT)), which is the pull-up voltage (VPU), until the
device is ready to respond appropriately to the input magnetic
field (t > tON). If the device powers-on with the field within the
hysteresis band, the output will switch from VOUT(FAULT) to the
off state (VOUT(HIGH)) with standard output polarity as shown in
Figure 4. For inverted output polarity operation, the output will
switch from VOUT(FAULT) to VOUT(LOW) (not shown).
The APS12450 allows the user to select the magnetic temperature
coefficient to compensate for drifts of SmCo, NdFeB, and ferrite
magnets over temperature, as indicated in the Magnetic Characteristics specifications table. This compensation improves the
magnetic system performance over the entire temperature range.
For example, the magnetic field strength from NdFeB decreases
as the temperature increases from 25°C to 150°C. This lower
magnetic field strength means that a lower switching threshold
is required to maintain switching at the same distance from the
magnet to the sensor. Correspondingly, higher switching thresholds are required at cold temperatures, as low as –40°C, due to
the higher magnetic field strength from the NdFeB magnet. The
APS12450 compensates the switching thresholds over temperature as described above. It is recommended that system designers evaluate their magnetic circuit over the expected operating
temperature range to ensure the magnetic switching requirements
are met.
OUTPUT
V
POS
VOUT(FAULT )
VOUT(HIGH)
B < BRP
BRP < B < BOP
Output Undefined for V CC < VCC(MIN)
VOUT(LOW )
B > BOP
SUPPLY VOLTAGE
t
V
A sample calculation is provided in the “Applications Information” section.
VCC(MIN)
0
tON
t
Figure 4: Power-On Sequence
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14
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Three-Wire Diagnostic Output
Three-wire diagnostic output enables the user to identify various
fault conditions external to the IC, in addition to the internal fault
detection. The output low (VOUT(LOW)) and high (VOUT(HIGH))
states are ratiometric to the pull-up voltage, with low and high
states being 20% and 80% respectively. For example, a VCC and
VPULL-UP of 5 V, the output state levels will be 1.0 V and 4.0 V
±0.5 V. The output RC time constant (τ) must be less than 3 µs
(e.g., RPU = 3 kΩ and COUT = 1 nF), and VPU must be equal to
VCC (recommend pulling up VOUT directly to VCC).
Under normal operation (Figure 5), the output switches between
the VOUT(LOW) (20%) and VOUT(HIGH) (80%) states.
VOUT(FAULT ) (VPU )
CBYPASS
VOUT(HIGH ) (80%)
RPULL-UP
VCC
VOUT
Normal
Operation
VOUT(LOW) (20%)
GND
COUT
GND
Figure 5: The APS12450 diagnostic output under normal operation (no fault detected)
With various opens and shorts on any of the IC pins, the output
will no longer be controlled by the IC. The output itself may
continue to switch, depending on the external connectivity fault;
however, the output level(s) observed will deviate from the 20%
and 80% (of VPU) output levels.
If an internal fault is detected via diagnostics monitoring, the
output will be set to the fault state, VOUT(FAULT), which is equal
to the pull-up voltage, VPU.
+V
VPU = VCC
VOUT(FAULT )
Fault State
VOUT(HIGH) (max)
Range for valid VOUT(HIGH)
VOUT(HIGH) (min)
External Fault
VOUT(LOW) (max)
Range for valid VOUT(LOW)
VOUT(LOW) (min)
0
External Fault
90% VPU
70% VPU
30% VPU
10% VPU
Any output voltage levels outside of the valid VOUT(HIGH) and
VOUT(LOW) ranges indicates a fault as shown in Figure 6. The
observed voltage on VOUT relative to potential fault conditions
are summarized in Table 2.
The output relative to the fault condition is summarized in Table 2
below.
Table 2: Fault Conditions and Resulting Output
Level
Fault
Output Level
No Fault
20% or 80% of VPU,
respectively
Short, VCC-VOUT
VCC
Short, VOUT-GND
GND
Short, VCC-GND
VPU
Open, VCC
VPU
Open, VOUT
VPU
Open, GND
VPU
Internal Fault
VPU
Note: VOUT(FAULT) ≤ VPULL-UP and VPULL-UP = VCC.
Figure 6: APS12450 valid (normal) and
fault condition output levels
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15
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Fault Detection and Retry
DIAG CHECK
OUTPUT
The fault detection diagnostics runs continuously in the background
during normal operation after the device has powered-on. In the
event a fault is detected, the output will immediately change to the
VOUT(FAULT) state. The diagnostics will continue to retry the diagnostics approximately every 2 ms. If the fault recovers, the output
will return to normal operation. See Figure 7.
VOUT(FAULT )
VOUT(HIGH)
Output switches according
to external magne�c field
Output switches according
to external magne�c field
VOUT(LOW )
t
Background
Diagnos�cs*
2 ms
Background
Diagnos�cs*
2 ms
t
Failure Detected
Device Recovers
Diag Retry**
* 4x Diagnos�c Cycles completed every 0.025 ms (nom.)
** Diagnos�c Fault Retry Time interval is 2 ms (nom.)
Figure 7: Fault Detection and Retry
Output Overshoot
When the output switches from VOUT(LOW) to VOUT(HIGH),
depending upon the RC circuit, a small overshoot can occur
(VOUT(H)OVER). VOUT(H)OVER is specified as a percentage of
VPULL-UP (and/or VCC, which need to be the same). Therefore
with an RC Time Constant (τ) of 3 µs (see the “Applications
Information” section), a nominal overshoot of 2% is possible.
With VPULL-UP at 5.0 V, the output may overshoot by 0.1 V, for
less than 5 µs (tVOUT(H)OVER). Figure 7 demonstrates output edge
profile.
For example, with a 5 V pull-up, if VOUT(HIGH) is at the upper limit
(90%), VOUT(HIGH) will be 4.5 V. With a τ of 3 µs at room temperature, the output can briefly reach 4.6 V until it settles to 4.5 V.
Since VOUT(HIGH) is valid between 70% and 90%, or 3.5 and 4.5 V,
this condition is not out of specification. The Output Off Voltage
Overshoot specification pertains only to conditions where the overshoot is greater than the VOUT(HIGH)MAX specification.
Figure 8: Output Overshoot
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16
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APPLICATIONS INFORMATION
Typical Applications
Temperature Compensation
For the LH and UA packages, an external bypass capacitor,
CBYP, should be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both
external noise and noise generated by the chopper stabilization
technique. As is shown in Figure 9, a 0.1 µF bypass capacitor is
typical, with an optional output capacitor, COUT (recommended
1 nF).
To calculate the typical effect of the TCSENS on BOP (or BRP),
simply multiply the BOP at the starting temperature by TCSENS
and the change in temperature.
The time constant of the RC circuit (τ) on output must be less
than 3 µs, where:
= 3 kΩ × 1 nF
= 3 µs
ΔTA = 150°C – 25°C = 125°C
BOP(150C) = BOP(25C) + (BOP(25C) × TC × ΔTA )
τ = RPULLUP × COUT
Sample BOP calculation for TCSENS compensation from 25°C to
150°C, for TCSENS = –0.12%/°C, and BOP(25C) = 180 G:
= 180 G + (180 G × –0.12%/°C × 125°C)
= 180 G + (–27 G)
= 153 G
The resistor, RPULLUP, must be between 2 and 30 kΩ.
VPULL-UP
VCC
Diagnostic Output*
RSERIES
(optional)
VCC
RPULL-UP
VCC
ECU
VOUT
CBYPASS
0.1 µF
ADC
VPU
VCC
CBYP
0.1 µF
COUT
τRC < 3 µs
RPU
IOUT < 12 mA
τRC < 3 µs
2 kΩ < R < 30 kΩ
RS
100 Ω*
GPIO
GND
COUT
(optional)
IC Output: Diagnostic Output
switching between VOUT(LOW) and VOUT(HIGH )
Figure 9: Typical Applications Circuits
Diagnostic Output
3 to 30 V
* The following application circuit conditions are required
• The τ of the RC on output must be < 3 µs.
• 2 kΩ < RPU < 30 kΩ.
• VPU = VCC (recommend pulling VOUT up
to VCC).
Allegro MicroSystems
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17
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701
• Guidelines For Designing Subassemblies Using Hall-Effect
Devices, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and ThroughHole, AN26009
• Functional Safety Challenges to the Automotive Supply Chain
(https://www.allegromicro.com/en/Design-Center/TechnicalDocuments/General-Semiconductor-Information/FunctionalSafety-Challenges-Automotive-Supply-Chain.aspx)
All are provided on the Allegro website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
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18
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Chopper Stabilization Technique
A limiting factor for switchpoint accuracy when using Halleffect technology is the small-signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize
Hall offset.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and
package stress. This offset reduction technique is based on a
signal modulation-demodulation process. “Figure 10: Model of
Chopper Stabilization Circuit (Dynamic Offset Cancellation)”
illustrates how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset causing the magnetically induced signal to recover its original spectrum at baseband while the DC offset becomes a highfrequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative
chopper-stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate that
produces higher accuracy, reduced jitter, and faster signal processing. Additionally, filtering is more effective and results in a
lower noise analog signal at the sensor output. Devices such as the
APS12450 that use this approach have an extremely stable quiescent Hall output voltage, are immune to thermal stress, and have
precise recoverability after temperature cycling. This technique is
made possible through the use of a BiCMOS process which allows
the use of low offset and low noise amplifiers in combination with
high-density logic and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Sample and
Hold
APS12450
Low-Pass
Filter
Figure 10: Model of Chopper Stabilization Circuit
(Dynamic Offset Cancellation)
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19
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
POWER DERATING
The device must be operated below the maximum junction
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties
of the application.
Thermal Resistance (junction to ambient), RθJA, is a figure of
merit summarizing the ability of the application and the device to
dissipate heat from the junction (die), through all paths to ambient air. RθJA is dominated by the Effective Thermal Conductivity,
K, of the printed circuit board which includes adjacent devices
and board layout. Thermal resistance from the die junction to
case, RθJC, is a relatively small component of RθJA. Ambient air
temperature, TA, and air motion are significant external factors in
determining a reliable thermal operating point.
The following three equations can be used to determine operation
points for given power and thermal conditions.
Finally, using equation 1, solve for maximum allowable VCC for
the given conditions:
VCC (est) = PD (max) ÷ ICC (max) = 91 mW ÷ 4 mA = 22.8 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VCC (est).
If the application requires VCC > VCC(est) then RθJA must by
improved. This can be accomplished by adjusting the layout,
PCB materials, or by controlling the ambient temperature.
Determining Maximum TA
In cases where the VCC (max) level is known, and the system
designer would like to determine the maximum allowable ambient temperature TA (max), for example, in a worst-case scenario
with conditions VCC (max) = 40 V, ICC (max) = 4 mA, and RθJA
= 228°C/W for the LH package using equation 1, the largest possible amount of dissipated power is:
PD = VIN × IIN
(1)
∆T = PD × RθJA
(2)
PD = VIN × IIN
TJ = TA + ∆T
(3)
PD = 40 V × 4 mA = 160 mW
For example, given common conditions: TA = 25°C, VCC = 12 V,
ICC = 4 mA, and RθJA = 110°C/W for the LH package, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
∆T = PD × RθJA = 48 mW × 110°C/W = 5.28°C
TJ = TA + ∆T = 25°C + 5.28°C = 31.28°C
Determining Maximum VCC
For a given ambient temperature, TA, the maximum allowable power dissipation as a function of VCC can be calculated.
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA.
Then, by rearranging equation 3 and substituting with equation 2:
TA (max) = TJ (max) – ΔT
TA (max) = 165°C – (160 mW × 228°C/W)
TA (max) = 165°C – 36.5°C = 128.5°C
In another example, the maximum supply voltage is equal to
VCC (min). Therefore, VCC (max) = 3 V and ICC (max) = 4 mA.
By using equation 1 the largest possible amount of dissipated
power is:
PD = VIN × IIN
PD = 3 V × 4 mA = 12 mW
Example: VCC at TA = 150°C, package UA, using low-K PCB.
Using the worst-case ratings for the device, specifically: RθJA =
165°C/W, TJ (max) = 165°C, VCC (max) = 24 V, and ICC (max) =
4 mA, calculate the maximum allowable power level, PD (max).
First, using equation 3:
Then, by rearranging equation 3 and substituting with equation 2:
∆T (max) = TJ (max) – TA = 165°C – 150°C = 15°C
TA (max) = 165°C – 11.6°C = 162.3°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, from equation 2:
PD (max) = ∆T (max) ÷ RθJA = 15°C ÷ 165°C/W = 91 mW
TA (max) = TJ (max) – ΔT
TA (max) = 165°C – (12 mW × 228°C/W)
The example above indicates that at VCC = 3 V and ICC = 4 mA,
the TA (max) can be as high as 162.3°C without exceeding
TJ (max). However the TA (max) rating of the device is 150°C;
the device performance is not guaranteed above TA = 150°C.
Allegro MicroSystems
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20
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Package LH, 3-Pin SOT23W
+0.125
2.975 –0.75
1.49 D
4°±4°
3
A
+0.020
0.180–0.053
0.96 D
+0.10
2.90 –0.20
+0.19
1.91 –0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Gauge Plane
8× 10° ±5°
B
PCB Layout Reference View
Branded Face
1.00 ±0.13
0.95 BSC
+0.10
0.05 –0.05
0.40 ±0.10
XXX
1
C
Standard Branding Reference View
Line 1 = Three digit assigned brand number
For reference only; not for tooling use (reference DWG-0000628, Rev. 1).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
A
Active Area Depth, 0.28 ±0.04 mm
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
Allegro MicroSystems
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21
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Package UA, 3-Pin SIP, Matrix HD Style
+0.08
4.09 –0.05
45°
B
C
E
+0.08
3.02 –0.05
2.04 NOM
1.52 ±0.05
1.44 NOM
E
10°
Mold Ejector
Pin Indent
E
Branded
Face
A
1.02
MAX
45°
XXX
0.79 REF
1
D Standard Branding Reference View
1
2
Line 1: Logo A
Line 2: Three digit assigned brand number
3
+0.03
0.41 –0.06
14.99 ±0.25
+0.05
0.43 –0.07
For reference only; not for tooling use (reference DWG-0000404, Rev. 1).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
A
Dambar removal protrusion (6×)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 ±0.08 mm
D
Branding scale and appearance at supplier discretion
E
Hall element (not to scale)
1.27 NOM
Allegro MicroSystems
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22
APS12450
Three-Wire Hall-Effect Latch with Advanced Diagnostics
REVISION HISTORY
Number
Date
Description
–
January 31, 2019
Initial release
1
April 23, 2019
Updated ASIL status
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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