ARG81800KESJSR-1

ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD FEATURES AND BENEFITS DESCRIPTION • Automotive AEC-Q100 qualified • Input operating voltage range: 3.5 to 36 V □□ Withstands surge voltages to 40 V for load dump • Low-Power (LP) mode—draws just 8 µA from VIN while maintaining 3.3 or 5.0 VOUT • AUTO mode allows automatic transition between PWM and LP mode based on load current • Programmable PWM frequency (fSW): 250 kHz to 2.4 MHz • PWM frequency dithering and controlled switch node slew rate reduce EMI/EMC signature • CLKOUT allows interleaving and dithering of “downstream” regulators using their synchronization inputs • Interleaving minimizes input filter capacitor requirement and improves EMI/EMC performance • Synchronization of PWM frequency to external clock on SYNCIN pin • Adjustable output voltage: ±1.5% accuracy over operating temperature range (‒40°C to 150°C) • Maximized duty cycle at low VIN improves dropout • Soft recovery from dropout condition • Adjustable soft-start time controls inrush current to accommodate a wide range of output capacitances • External compensation provides flexibility to tune the system for maximum stability or fast transient response The ARG81800 includes all the control and protection circuitry to produce a PWM regulator with ±1.5% output voltage accuracy, with ultralow quiescent current to enable “keepalive” supply operation with minimal current draw from the supply during very light load regulation. There are two versions of the ARG81800 available, 500 mA and 1 A, so the physical size of the power components can be optimized for lower current systems, thus reducing PCB area and saving cost. PWM switching frequency can be programmed over a wide range to balance efficiency, component sizing, and EMC performance. If VIN decays and the duty cycle reaches its maximum, the ARG81800 will automatically fold back its PWM frequency to extend the duty cycle and maintain VOUT. Continued on next page... Infotainment Navigation Systems Instrument Clusters Audio Systems ADAS Applications If the SYNCIN pin is driven by an external clock, the ARG81800 will be forced into PWM mode and synchronize to the incoming clock. The ARG81800 adds frequency dithering to the SYNCIN clock to reduce EMI/EMC. The ARG81800 provides a CLKOUT pin so “downstream” regulators can be easily interleaved and dithered via their synchronization inputs. Continued on next page... APPLICATIONS • • • • • The ARG81800 employs Low-Power (LP) mode to maintain the output voltage at no load or very light load conditions while drawing only micro-amps from VIN. The ARG81800 includes a PWM/AUTO control pin so the system can dynamically force either PWM or AUTO mode by setting this pin high or low, respectively. • • • • • Battery Powered Systems Industrial Systems Network and Telecom Home Audio HVAC Systems 3.5 to 36 V VIN GND 1 µF PGND PWM/AUTO PACKAGE: 20-pin, 4 mm × 4 mm, QFN (ES) with wettable flank Not to scale BIAS BOOT 0.1 µF SW FB EN FSET SS 22 nF 3.3 V, 1 A 20 µF 95.3 kΩ SYNCIN 14.3 kΩ fSW = 2.15 MHz 3.3 µH 301 kΩ 4.7 pF PGOOD CLKOUT COMP VREG 2.2 nF 4.7 µF 10 kΩ 68 pF 40.2 kΩ Typical Application Diagram ARG81800-DS MCO-0000676 June 11, 2019 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 FEATURES AND BENEFITS • • • • Enable input can command ultralow 1 µA shutdown current Open-drain PGOOD output with rising delay Pre-bias startup allows quick restart and avoids reset Overvoltage, pulse-by-pulse current limit, hiccup mode short circuit, and thermal protections • Robust FMEA: pin open/short and component faults DESCRIPTION The ARG81800 has external compensation, so it can be tuned to satisfy a wide range of system goals with many different external components over a wide range of PWM frequencies. The ARG81800 includes adjustable soft start to minimize inrush current. The ARG81800 monitors the feedback voltage to provide an open-drain power good signal. The Enable input can command an ultra-low current shutdown mode with VOUT = 0 V. Extensive protection features of the ARG81800 include pulse-bypulse current limit, hiccup mode short circuit protection, BOOT open/short voltage protection, VIN undervoltage lockout, VOUT overvoltage protection, and thermal shutdown. The ARG81800 is supplied in a low profile 20-pin wettable flank QFN package (suffix “ES”) with exposed power pad. SELECTION GUIDE Part Number DC Current Package Packing Lead Frame ARG81800KESJSR 1 A ARG81800KESJSR-1 0.5 A 20-pin wettable flank QFN package with thermal pad 6000 pieces per 13-inch reel 100% matte tin *Contact Allegro for additional packing options Table of Contents Features and Benefits............................................................ 1 Description........................................................................... 1 Package.............................................................................. 1 Typical Application Diagram.................................................... 1 Selection Guide.................................................................... 2 Absolute Maximum Ratings.................................................... 3 Thermal Characteristics......................................................... 3 Functional Block Diagram...................................................... 4 Pinout Diagram and Terminal List............................................ 5 Electrical Characteristics........................................................ 6 Typical Performance Characteristics.......................................11 Functional Description......................................................... 16 Overview........................................................................ 16 Reference Voltage........................................................... 16 Internal VREG Regulator.................................................. 16 Oscillator/Switching Frequency.......................................... 16 Synchronization (SYNCIN) and Clock Output (CLKOUT)......... 16 Frequency Dither............................................................. 16 Transconductance Error Amplifier...................................... 17 Compensation Components.............................................. 18 Power MOSFETs............................................................. 18 BOOT Regulator.............................................................. 18 Soft Start (Startup) and Inrush Current Control.................... 18 Slope Compensation........................................................ 18 Pre-Biased Startup........................................................... 19 Dropout.......................................................................... 19 PGOOD Output............................................................... 19 Current Sense Amplifier.................................................... 19 Pulse-Width Modulation (PWM)......................................... 19 Low-Power (LP) Mode...................................................... 20 Protection Features.......................................................... 21 Undervoltage Lockout (UVLO)....................................... 21 Pulse-by-Pulse Peak Current Protection (PCP)................ 21 Overcurrent Protection (OCP) and Hiccup Mode.............. 21 BOOT Capacitor Protection........................................... 22 Asynchronous Diode Protection..................................... 22 Overvoltage Protection (OVP)........................................ 22 SW Pin Protection........................................................ 22 Pin-to-Ground and Pin-to-Short Protections..................... 22 Thermal Shutdown (TSD).............................................. 23 Application Information........................................................ 25 Design and Component Selection...................................... 25 PWM Switching Frequency (RFSET)................................ 25 Output Voltage Setting.................................................. 25 Output Inductor (LO)..................................................... 26 Output Capacitors (CO)................................................. 27 Output Voltage Ripple – Ultralow-IQ LP Mode.................. 28 Input Capacitors........................................................... 29 Bootstrap Capacitor...................................................... 29 Soft Start and Hiccup Mode Timing (CSS)........................ 29 Compensation Components (RZ, CZ, and CP).................. 30 Power Stage................................................................ 30 Error Amplifier.............................................................. 31 A Generalized Tuning Procedure.................................... 32 Power Dissipation and Thermal Calculations.......................... 34 EMI/EMC Aware PCB Design............................................... 36 Typical Reference Designs................................................... 39 Package Outline Drawing..................................................... 41 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS [1] Characteristic Symbol Notes VIN, EN, SS, BIAS Pin Voltage SW Pin Voltage BOOT Pin Voltage VSW VBOOT Continuous VIN ≤ 36 V, t < 50 ns Storage Temperature Unit –0.3 to 40 V –0.3 [2] to VIN + 0.3 V –1.0 to VIN + 2 V Continuous VSW – 0.3 to VSW + 5.5 V t < 1 ms VSW – 0.3 to VSW + 7.0 V All Other Pin Voltages Operating Junction Temperature Rating –0.3 to 5.5 V TJ(max) –40 to 150 °C Tstg –55 to 150 °C Stresses beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. [2] This voltage is a function of temperature. [1] THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Package Thermal Resistance [3] Additional Symbol RqJA Test Conditions [3] On 4-layer PCB based on JEDEC standard Value Unit 37 °C/W thermal information available on the Allegro website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 VIN Bias LDO Bias VREG MODE Slope Compensation Ramp Offset Current Sense Amp Gcs FBOV FBUV VINLXSC 500mΩ HD SW PWM/LP Control Logic PWM COMP VREG GND PGND 0.74 V FBUV OCL PGOOD Delay SS LP Comparator FB SLEEP Overcurrent Clamp Hiccup, Dropout, Stop-Start Recovery, Fault, Startup 0.804 V 210 mΩ LD MODE PWM/ AUTO T/2 FAULT CLK CLKOUT Protection & Fault TSD SYNCIN BOOT LXGNDSC toff PLL+ Dither OSC UVLO FB ENd Div 2 or 4 Start up or Hiccup or Drop out OOV ENd tDIS REGOK REGOK 2.5V EN BOOT FAULT OOV 21.6 V 5.4 V FSET EN BOOT REG 0.8 V BG VREG LD OCL Bias >3.15V REGOK BIAS UVLO 3.55 V 3.3 V SLEEP VIN FBOV 0.88 V Error Amp 0.8 V MODE LP Clamp MODE FB SS SS Offset COMP Functional Block Diagram Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 SW 2 SW 3 SS EN PGND Terminal List Table Number 16 NC PGND 17 18 VIN 1 15 VREG 14 FB 13 BIAS 4 12 PGOOD 5 11 COMP 7 8 9 SYNCIN GND FSET PWM/AUTO 10 6 PAD CLKOUT BOOT 19 20 VIN PINOUT DIAGRAM AND TERMINAL LIST Package ES, 20-Pin QFN Pinout Diagram Name Function 1 BOOT This pin supplies the drive for the high-side N-channel MOSFET. Connect a 100 nF ceramic capacitor from BOOT to SW. Do not add any external resistor in series with the boot capacitor. 2, 3 SW Regulator switch node output pins. Connect these pins to power inductor with a short and wide PCB trace. 4 SS Soft start pin. Connect a capacitor, CSS, from this pin to GND to set the start-up time. This capacitor also determines the hiccup period during overcurrent. EN This pin must be set high to enable the ARG81800. If this pin is low, the ARG81800 will enter a very low current shutdown or “SLEEP” state where VOUT = 0 V. If the application does not require a logic level controlled enable, then this pin can be tied directly to VIN. Also, if this pin is floated, it will be pulled low by an internal pull-down resistor, disabling the ARG81800. CLKOUT Dual function pin: Clock output pin for “Master” operation. Frequency dithering is added to this pin when the ARG81800 is operating as a Master. For “Follower” operation, this pin must be connected to VREG so dithering will not be internally added to SYNCIN; see Figure 1. The exact functionality of this pin is dependent on the status of the SYNCIN pin; see Table 1 and the description for SYNCIN for additional details. 7 SYNCIN Triple function pin: High/Low/ExtClock. Setting this pin high sets CLKOUT to the internal oscillator frequency (fSW) but with 180 degree phase shift. Setting this pin low disables the CLKOUT pin. Applying an external clock (at fSYNC) forces PWM mode, synchronizes the PWM switching frequency to the external clock plus dithering, and sets CLKOUT to the same dithered frequency but with 180 degree phase shift. See Table 1 for details. 8 GND Analog ground pin. 9 FSET Frequency setting pin. A resistor, RFSET, from this pin to GND sets the oscillator frequency, fSW. 10 PWM/ AUTO Mode selection pin. High/Low. Setting this pin high forces PWM mode. Setting this pin low allows AUTO changeover between PWM and LP mode based on the load current. 11 COMP Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from this pin to GND for loop compensation. 12 PGOOD Power good output signal. PGOOD is an open-drain output that remains low until the output has achieved regulation for tdPG(SU). The PGOOD pull-up resistor can be connected to VREG, VOUT, or any external supply voltage less than 5.5 V. PGOOD will pull low if the output voltage (VOUT) is out of range. 13 BIAS Connect this pin to the output of the regulator. This pin supplies the internal circuitry when the voltage level is high enough. 14 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulators output, VOUT, to this pin to program the output voltage. 15 VREG Internal voltage regulator bypass capacitor pin. Connect a 4.7 µF capacitor from this pin to PGND and place it very close to the ARG81800. 16, 17 PGND Power ground pins for the lower MOSFET, gate driver, and BOOT charge circuit. 18 NC No connection. 19, 20 VIN Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. Bypass VIN to PGND with an X7R or X8R ceramic capacitor. Place the capacitor as close to the VIN and PGND pins as possible. Additional capacitors may be required depending on the application to comply with EMC requirements. ‒ PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane of the PCB with at least 6 vias directly in the pad. 5 6 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS: Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT VOLTAGE Input Voltage Range VIN VIN must first rise above VINUV(ON) (max) 3.5 – 36 V VINUV(ON) VIN rising 3.35 3.55 3.8 V VIN UVLO Stop VINUV(OFF) VIN falling 3.1 3.3 3.5 V VIN UVLO Hysteresis VINUV(HYS) − 250 − mV VIN UVLO Start INPUT SUPPLY CURRENT Input Shutdown Current [2] IIN(SD) Input Current, PWM Mode [2] IIN(PWM) 3.3 VOUT LP Input Current [3][4] ILP(3.3V) 5.0 VOUT LP Input Current [3][4] ILP(5.0V) VIN = 12 V, VEN = 0, VSW = VIN, TJ = 25°C − 1 2 µA VIN = 12 V, VEN = 2 V, no load, no switching − 5 6.5 mA VIN = 12 V, IOUT = 0 µA, TJ = 25°C − 8 − µA VIN = 12 V, IOUT = 50 µA, TJ = 25°C − 33 − µA VIN = 12 V, IOUT = 0 µA, TJ = 25°C − 8 − µA VIN = 12 V, IOUT = 50 µA, TJ = 25°C − 44 − µA 788 800 812 mV REGULATION ACCURACY (FB PIN) Feedback Voltage Accuracy VFB –40°C < TJ < 150°C, VIN ≥ 3.5 V, VFB = VCOMP SWITCHING FREQUENCY AND DITHERING (FSET PIN) PWM Switching Frequency Dropout Switching Frequency fSW RFSET = 14.3 kΩ 1.93 2.15 2.37 MHz RFSET = 34 kΩ 0.90 1.00 1.10 MHz RFSET = 71.5 kΩ 450 500 550 kHz RFSET = 86.6 kΩ 360 410 460 kHz − fSW/4 − − CLKOUT left open − ±5 ±6.5 % of fSW CLKOUT connected to VREG − 0 − % of fSW − ±0.5 − % of fSW − 60 85 ns fDROP PWM Frequency Dither Range fDITH(RNG) PWM Dither Modulation Frequency fDITH(MAG) PULSE WIDTH MODULATION (PWM) TIMING AND CONTROL Minimum Controllable SW On-Time Minimum SW Off-Time COMP to SW Current Gain Slope Compensation PWM Ramp Offset tON(MIN) VIN = 12 V, IOUT = 0.7 A, VBOOT – VSW = 4.5 V tOFF(MIN) VIN =12 V, IOUT = 0.7 A − 85 110 ns gmPOWER1 ARG81800 − 2.0 − A/V gmPOWER2 ARG81800-1 − 1.0 − A/V SE1 fSW = 2.15 MHz, ARG81800 650 900 1100 mA/µs SE2 fSW = 2.15 MHz, ARG81800-1 325 450 550 mA/µs SE3 fSW = 252 kHz, ARG81800 75 100 125 mA/µs SE4 fSW = 252 kHz, ARG81800-1 35 50 65 mA/µs − 650 − mV VPWM(OFFS) Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit LOW-POWER (LP) MODE LP Output Voltage Ripple [3][4] Low IQ Peak Current Threshold ΔVOUT(LP) LP Mode, 8 V < VIN < 12 V − 65 − mV IPEAK(LP1) ARG81800, No Load, VIN = 12 V 320 400 500 mA IPEAK(LP2) ARG81800-1, No Load, VIN = 12 V 160 212 270 mA TJ =25°C [3], VBOOT – VSW = 4.5 V, IDS = 800 mA − 500 600 mΩ TJ = 150°C, VBOOT – VSW = 4.5 V, IDS = 800 mA − − 1075 mΩ TJ =25°C [3], VIN ≥ 4.5 V, IDS = 1 A − 210 250 mΩ INTERNAL POWER SWITCHES High-Side MOSFET On-Resistance Low-Side MOSFET On-Resistance RDS(on)HS RDS(on)LS TJ =150°C, VIN ≥ 4.5 V, IDS = 1 A − − 450 mΩ High-Side Leakage Current [5] ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 0 V −1.5 − 1.5 µA Low-Side Leakage Current ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 12 V −1.5 − 1.5 µA − 10 25 ns − 5 − V/ns Gate Drive Non-Overlap Time [3] Switch Node Rising Slew Rate tNO SRHS 12 V < VIN < 16 V [3] MOSFET CURRENT PROTECTION THRESHOLDS High-Side Current Limit Low-Side Current Limit ILIMHS1 tON = tON(MIN), ARG81800 1.7 2.0 2.3 A ILIMHS2 tON = tON(MIN), ARG81800-1 0.85 1.0 1.15 A − 50 − % of ILIMHSx ILIMLSx SYNCHRONIZATION INPUT (SYNC IN PIN) Synchronization Frequency Range fSW(SYNC) 0.25 − 2.5 MHz SYNCIN Duty Cycle DCSYNC 20 50 70 % SYNCIN Pulse Width SYNCIN Voltage Thresholds 80 − − ns VSYNC(HI) tPWSYNC VSYNC(IN) rising − 1.35 1.5 V VSYNC(LO) VSYNC(IN) falling 0.8 1.2 − V SYNCIN Hysteresis VSYNC(HYS) VSYNC(HI) ‒ VSYNC(LO) − 150 − mV SYNCIN Pin Current ISYNC VSYNC(IN) = 5 V − ±1 − µA CLOCK OUTPUT (CLK OUT PIN) SYNCIN to CLKOUT Delay ФSYNC(CLK) RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V, Dither disabled − 1/(2×fSW) ± 70 − ns SWMASTER to SWFOLLOWER Delay [3] ФSWM(SWF) RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V − 1/(2×fSW) ± 30 − ns VCLK(OUT)H VVREG = 4.8 V 2.2 − − V VCLK(OUT)L VVREG = 4.8 V − − 0.6 V CLKOUT Output Voltages Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit –40 – –15 nA − 65 − dB VFB > 400 mV 550 750 950 μA/V 0 V < VFB < 400 mV 275 375 550 μA/V − ±75 − μA − 1 − kΩ ERROR AMPLIFIER Feedback Input Bias Current [2] Open-Loop Voltage Gain IFB Transconductance gm Output Current IEA COMP Pull-Down Resistance VFB = 800 mV AVOL RCOMP FAULT = 1 or HICCUP = 1 SOFT START Startup (Source) Current ISS HICCUP = FAULT = 0 −30 −20 −10 µA Hiccup/Dropout (Sink) Current IHIC HICCUP = 1 or Dropout Mode 1 2.2 5 µA Soft Start Delay Time [3] tdSS CSS = 22 nF − 440 − µs Soft Start Ramp Time [3] tSS CSS = 22 nF − 880 − µs VSS falling due to HICCUP or FAULT − 200 275 mV VSS rising − 2.3 − V 0 V < VFB < 200 mV – fSW / 4 – – 200 mV < VFB < 400 mV – fSW / 2 – – FAULT/HICCUP Reset Voltage Hiccup OCP (and LP) Counter Enable Threshold Soft Start Frequency Foldback VSSRST VHIC/LP(EN) fSW(SS) Maximum Voltage VSS(MAX) Pull-Down Resistance RSS(FLT) 400 mV < VFB – fSW – – VEN = 0 V or FAULT without HICCUP − VVREG − − 2 kΩ HICCUP MODE COUNTS High-Side Overcurrent Count HICOC After VSS > VHIC/LP(EN) − 120 − fSW counts SW Short-to-Ground Count HICSW(GND) − 2 − fSW counts BOOT Short Circuit Count HICBOOT(SC) − 120 − fSW counts BOOT Open Circuit Count [3] HICBOOT(OC) − 7 − fSW counts Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit 850 880 900 mV OUTPUT VOLTAGE PROTECTION THRESHOLDS (VFB, OV, UV) VFB OV PWM Threshold VFB(OV) VFB OV PWM Hysteresis VFB(OV,HYS) VFB UV PWM Threshold VFB(UV) VFB UV PWM Hysteresis VFB(UV,HYS) VFB UV LP Mode Threshold [3] VFB(UV,LP) VFB rising VFB falling, relative to VFB(OV) VFB falling VFB rising, relative to VFB(UV) VFB falling – −15 – mV 716 740 764 mV – +15 – mV 665 700 735 mV µs POWER GOOD OUTPUT (PGOOD PIN) PGOOD Startup (SU) Delay tdPG(SU) Increasing VFB due to startup − 30 − PGOOD Undervoltage (UV) Delay tdPG(UV) Decreasing VFB − 30 − µs PGOOD Overvoltage (OV) Delay tdPG(OV) After an overvoltage event − 240 − fSW cycles PGOOD Low Voltage VPG(L) IPGOOD = 5 mA − 200 400 mV PGOOD Leakage [1] IPG(LKG) VPGOOD = 5.5 V − − 2 µA VHI(PWM) VPWM/AUTO rising 1.8 2.0 2.5 V PWM/AUTO INPUT PWM/AUTO High Threshold PWM/AUTO Float Voltage VFLOAT(PWM) VPWM/AUTO floating 1.1 1.4 1.7 V PWM/AUTO Low Threshold VLO(PWM) VPWM/AUTO falling 0.6 0.8 1.0 V PWM to LP Transition Delay [3] tdPWM(LP) VPWM/AUTO = 0 V, VSS > VHIC/LP(EN), PGOOD high − 7.5 − ms ENABLE INPUT (EN PIN) Enable High Threshold VENHI VEN rising − 1.6 2.0 V Enable Low Threshold VENLO VEN falling 0.8 1.4 − V Enable Input Hysteresis VENHYS VENHI ‒ VENLO − 200 − mV tDISDLY VEN transitions low to when SW stops switching − 120 − fSW cycles VEN = VPWM/AUTO = 5 V − 12 − µA Disable Delay Enable Pin Input Current IEN Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit − fSW − − − 4.8 5.3 V BOOT REGULATOR (BOOT PIN) BOOT Charging Frequency fBOOT BOOT Voltage VBOOT VIN = 12 V, VBOOT – VSW VVREG1 6 V < VVIN < 36 V, VBIAS = 0 V 4.5 4.8 5.1 V VBIAS = 3.3V 2.85 3.2 3.29 V 6 V < VBIAS < 20 V 4.5 4.8 5.1 V 3.3 − 36 V 155 170 − °C − 20 − °C INTERNAL REGULATOR (VREG PIN) BIAS Disconnected BIAS Connected BIAS Input Voltage Range VVREG2 VBIAS THERMAL SHUTDOWN PROTECTION (TSD) TSD Rising Threshold [3] TSD Hysteresis [3] TTSD TSDHYS TJ rising, PWM stops immediately and COMP and SS are pulled low TJ falling, relative to TTSD [1] Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airflow. [3] Ensured by design and characterization, not production tested. [4] Using recommended external components specified in Table 3. [5] At V = 36 V, I IN OUT = 0 A, and TJ = 150°C, VOUT rises to overvoltage threshold due to leakage. [2] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C. ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values. ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values. 4 3.8 Current (mA) 3.6 3.5 3.4 3.3 3.2 3.1 3 5 4.8 4.6 4.6 4.4 4.4 4.2 4 3.8 3.6 3.4 3.2 -40 -20 0 20 40 60 80 100 120 140 3 160 Temperature (°C) UVLO Stop 5 4 7 3.5 Current (µA) 6 5 4 3 2 18.5 23.5 28.5 33.5 23.5 28.5 33.5 2 1.5 1.5 1.4 1.3 1.1 1 -40 -20 0 20 40 60 80 100 120 140 -40 20 600 Voltage (mV) 3.5 Resistance (mΩ) 700 803 3.7 802 801 800 799 3.3 15.5 18.5 Bias Voltage (V) Bias Pin Current, PWM Mode Bias Pin Current vs. Output Voltage 21.5 798 -20 0 20 40 60 80 100 120 80 100 120 140 160 EN Low Threshold 500 400 300 200 100 -40 60 EN High and Low Thresholds vs. Temperature 800 3.9 40 EN High Threshold 804 12.5 0 Temperature (°C) 805 9.5 -20 160 Input Shutdown Current vs. Temperature 4.1 160 1.6 Input Shutdown Current 4.3 140 1.2 No Load Input Current, HLP Mode 4.5 120 1.7 Temperature (°C) 4.7 100 80 2 2.5 0 60 1.8 4.9 6.5 40 20 No-Load Input Current (PWM Mode) vs. Temperature 5.1 3.5 0 1.9 Input Current vs. Input Voltage 3.1 -20 No Load Input Current, PWM Mode 3 Input Voltage (V) Input Shutdown Current -40 Temperature (°C) 0.5 18.5 3 38.5 1 1 Current (mA) 13.5 No-Load Input Current (PWM Mode) vs. Input Voltage 4.5 13.5 3.4 No Load Input Current, PWM Mode 8 Current (µA) 8.5 UVLO Start 9 8.5 3.6 3.2 3.5 10 3.5 4 3.8 Input Voltage (V) UVLO Start and Stop Thresholds vs. Temperature 0 4.2 Voltage (V) Voltage (V) 3.7 5 4.8 Current (mA) 3.9 140 Temperature (°C) Feedback Voltage Feedback Voltage vs. Temperature 160 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) High-Side On Resistance Low-Side On Resistance On Resistance (High-Side and Low-Side) vs. Temperature Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C. ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values. ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values. 70 2.1 1.1 2.05 1.05 Current (A) Time (ns) 60 55 50 45 Current (A) 65 2 1 0.95 1.95 40 35 -40 -20 0 20 40 60 80 100 120 140 1.9 160 Temperature (°C) Minimum On Time 0 Minimum Off Time 20 60 80 100 120 140 0.9 160 -25 -26 -27 25 20 40 60 80 100 120 140 5 160 0.05 0.04 0.03 0 20 40 60 80 100 120 140 160 Feedback Input Bias Current vs. Temperature 2.17 Switching Frequency (MHz) 2.18 880 860 840 Voltage (mV) 80 60 820 800 780 760 740 720 0 20 40 60 80 20 100 Temperature (°C) PGOOD Low Voltage PGOOD Low Voltage vs. Temperature 120 140 160 700 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FB OV Threshold, PWM Mode 40 60 80 100 120 140 160 PGOOD Leakage Current vs. Temperature PGOOD Delay (UV and SU) vs. Temperature 900 -20 0 PGOOD Leakage Current 180 -40 -20 Temperature (°C) 200 40 -40 PGOOD UV/SU Delay 100 160 0.06 0 -20 Feedback Input Bias Current 120 140 0.07 Temperature (°C) 140 120 0.01 -40 Temperature (°C) 160 100 80 0.02 10 -29 60 0.1 15 -28 40 0.08 Current (nA) Time (µs) -24 20 20 0.09 30 -23 0 0 High-Side Current Limit vs. Temperature – ARG81800-1 35 -20 -20 High-Side Current Limit - ARG81800-1 40 -22 -40 -40 Temperature (°C) High-Side Current Limit vs. Temperature – ARG81800 -21 Voltage (mV) 40 High-Side Current Limit - ARG81800 -20 Current (nA) -20 Temperature (°C) Minimum On and Off Time vs. Temperature -30 -40 FB UV Threshold, PWM Mode Feedback OV and UV Threshold vs. Temperature 160 2.16 2.15 2.14 2.13 2.12 2.11 2.1 2.09 2.08 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) RFSET = 14.3 kΩ Switching Frequency vs. Temperature Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C. ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values. ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values. 60 50 40 60 50 40 30 30 20 20 10 10 0 0.001 0.01 0.1 0 0.001 1 0.01 Load Current (A) VIN = 8 V, HLP Mode VIN = 12 V, HLP Mode VIN = 16 V, HLP Mode VIN = 8 V, HLP Mode VIN = 12 V, HLP Mode VIN = 16 V, HLP Mode VIN = 8 V, PWM Mode VIN = 12 V, PWM Mode VIN = 16 V, PWM Mode VIN = 8 V, PWM Mode VIN = 12 V, PWM Mode VIN = 16 V, PWM Mode Efficency vs. Load Current VOUT = 5.0 V, fSW = 400 kHz 1 0.1 0.8 0.08 0.6 0.06 0.4 0.04 Regulation (%) Regulation (%) Efficency vs. Load Current VOUT = 3.3 V, fSW = 2.15 MHz 0.2 0 -0.2 0.02 0 -0.02 -0.4 -0.04 -0.6 -0.06 -0.8 -0.08 -1 0.05 0.5 0.1 Load Current (A) 0.1 0.15 0.2 0.25 -0.1 0.05 0.3 0.1 0.15 0.2 VIN = 8 V VIN = 12 V 0.25 0.3 0.35 0.4 0.45 0.5 Load Current (A) Load Current (A) VIN = 8 V VIN = 16 V Load Regulation VOUT = 3.3 V, fSW = 2.15 MHz, LP Mode VIN = 12 V VIN = 16 V Load Regulation VOUT = 5.0 V, fSW = 400 kHz, PWM Mode 1 0.06 0.8 0.04 0.6 Regulation (%) Regulation (%) 0.4 0.2 0 -0.2 -0.4 -0.6 0 -0.02 -0.04 -0.8 -1 0.02 5.5 10.5 15.5 20.5 25.5 30.5 Input Voltage (V) IOUT = 0 A IOUT = 0.15 A Line Regulation VOUT = 3.3 V, fSW = 2.15 MHz, LP Mode 35.5 -0.06 7 12 17 22 27 32 36 Input Voltage (V) IOUT = 0 A IOUT = 0.25 A IOUT = 0.5 A Line Regulation VOUT = 5.0 V, fSW = 400 kHz, PWM Mode Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD TYPICAL PERFORMANCE CHARACTERISTICS VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C. ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values. ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values. VEN: 5 V/DIV VEN: 5 V/DIV VEN: 5 V/DIV VOUT: 1 V/DIV VSS: 2 V/DIV VSS: 2 V/DIV VOUT: 2 V/DIV VSS: 2 V/DIV VOUT: 1 V/DIV VPGOOD: 5 V/DIV 1 ms/DIV Start-up with EN rising VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode VPGOOD: 5 V/DIV ILO: 1 A/DIV 100 µs/DIV Shut-down with EN falling VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode 1 ms/DIV Pre-bias Start-up with EN rising VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode VSW: 10 V/DIV VEN: 5 V/DIV VSS: 2 V/DIV VSW: 10 V/DIV VOUT (AC): 20 mV/DIV VOUT: 2 V/DIV VOUT (AC): 100 mV/DIV IL: 500 mA/DIV IL: 500 mA/DIV VPGOOD: 5 V/DIV 200 µs/DIV Pre-bias Shut-down with EN falling VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode VPGOOD: 2 V/DIV 500 ns/DIV Steady-State Performance VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode VPGOOD: 2 V/DIV 10 µs/DIV Steady-State Performance VOUT = 3.3 V, IOUT = 10 mA, LP Mode VSW: 10 V/DIV VOUT (AC): 200 mV/DIV VOUT (AC): 100 mV/DIV VOUT (AC): 50 mV/DIV 40 mA/µs IL: 500 mA/DIV IOUT: 500 mA/DIV 40 mA/µs VPGOOD: 2 V/DIV VPGOOD: 2 V/DIV VPGOOD: 2 V/DIV 5 µs/DIV Steady-State Performance VOUT = 3.3 V, IOUT = 100 mA, LP Mode IOUT: 500 mA/DIV 200 µs/DIV Load Transient Performance VOUT = 3.3 V, PWM Mode 200 µs/DIV Load Transient Performance VOUT = 3.3 V, LP Mode Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C. ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values. ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values. VSW: 10 V/DIV VOUT (AC): 100 mV/DIV VOUT (AC): 100 mV/DIV 20 mA/µs 20 mA/µs IOUT: 500 mA/DIV IOUT: 500 mA/DIV VPGOOD: 5 V/DIV VPGOOD: 5 V/DIV 200 µs/DIV 200 µs/DIV Load Transient Performance VOUT = 5.0 V, PWM Mode VOUT (AC): 100 mV/DIV Load Transient Performance VOUT = 5.0 V, LP Mode VSYNCIN: 5 V/DIV 5 µs/DIV External Clock Synchronization VOUT = 3.3 V, fSW = 2.15 MHz, fEXT = 1 MHz VSW (MASTER): 5 V/DIV VSW: 10 V/DIV VIN: 10 V/DIV VOUT: 2 V/DIV VSS: 2 V/DIV VSW (follower): 5 V/DIV VPGOOD: 2 V/DIV VOUT: 2 V/DIV VPGOOD: 5 V/DIV Interleaved Clock Generation VOUT = 5.0 V, fSW = 500 kHz, PWM Mode Output Short Protection VOUT = 3.3 V, PWM Mode VIN: 5 V/DIV 500 ns/DIV 5 ms/DIV 10 s/DIV VOUT: 2 V/DIV IOUT: 1 A/DIV 100 ms/DIV ISO 16750-2: Load Dump Pulse VOUT = 3.3 V, IOUT = 1.0A, PWM Mode 50 s/DIV VIN: 5 V/DIV VIN: 5 V/DIV VOUT: 2 V/DIV VOUT: 2 V/DIV VPGOOD: 2 V/DIV IOUT: 1 A/DIV VIN Slow Ramp Up and Ramp Down VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode VPGOOD: 2 V/DIV IOUT: 1 A/DIV 200 ms/DIV ISO 16750-2: Level 1 Starting Profile VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode VPGOOD: 2 V/DIV ISO 16750-2: Reset Voltage Profile VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD FUNCTIONAL DESCRIPTION Overview The ARG81800 is a wide input voltage (3.5 to 36 V) synchronous PWM buck regulator that integrates low RDS(on) high-side and low-side N-channel MOSFETs. The ARG81800 employs peak current mode control to provide superior line and load regulation, cycle-by-cycle current limit, fast transient response, and simple compensation. The features of the ARG81800 include ultralow IQ LP mode, extremely low minimum on-time, maximized duty cycle for low dropout operation, soft recovery from dropout condition, and pre-bias startup capability. Protection features of the ARG81800 include VIN undervoltage lockout, cycle-by-cycle overcurrent protection, BOOT overvoltage and undervoltage protection, hiccup mode short circuit protection, overvoltage protection, and thermal shutdown. In addition, the ARG81800 provides open circuit, adjacent pin short circuit, and pin-to-ground short circuit protection. Reference Voltage The ARG81800 incorporates an internal precision reference that allows output voltages as low as 0.8 V. The accuracy of the internal reference is ±1.5% across –40°C to 150°C. The output voltage of the regulator is programmed with a resistor divider between VOUT and the FB pin of the ARG81800. Internal VREG Regulator VREG is used as the power supply for internal control circuitry and a low-side MOSFET driver. The ARG81800 consists of two internal low dropout regulators, VIN LDO and Bias LDO, to generate VREG voltage. VIN LDO is powered from input voltage to generate 4.8 V for VREG supply. Bias LDO uses the BIAS pin as a supply to generate VREG voltage. When voltage at the BIAS pin exceeds 3.0 V, VIN LDO is deactivated and Bias LDO generates the VREG voltage. Bias LDO can be made more efficient than VIN LDO by providing an external voltage at the BIAS pin that is less than the input voltage. If the output voltage of the ARG81800 is programmed to be greater than 3.1 V, it is recommended to supply the output voltage to the BIAS pin to improve the efficiency of the regulator. Oscillator/Switching Frequency The PWM switching frequency of the ARG81800 is adjustable from 250 kHz to 2.4 MHz by programming the internal clock fre- quency of the oscillator by connecting an FSET resistor from the FSET pin to GND. The internal clock has an accuracy of about ±10% over the operating temperature range. Usually, an FSET resistor with ±1% tolerance is recommended. A graph of switching frequency versus FSET resistor value is shown in the Design and Component Selection section. The ARG81800 will suspend operation if the FSET pin is shorted to GND or left open. Synchronization (SYNCIN) and Clock Output (CLKOUT) The Phase-Locked Loop (PLL) in the ARG81800 allows its internal oscillator to be synchronized to an external clock applied on the SYNCIN pin. If the SYNCIN pin is driven by an external clock, the ARG81800 will be forced to operate in PWM mode, with synchronized switching frequency, overriding the mode selection on the PWM/AUTO pin. The external clock must also satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the Electrical Characteristics table. If the SYNCIN pin is continuously pulled high, the ARG81800 outputs a 180-degree phase-shifted internal oscillator clock on the CLKOUT pin, so “downstream” ARG81800 devices can be easily interleaved via their synchronization inputs. Figure 1 shows the usage of multiple ARG81800 devices in master-follower configuration. If the SYNCIN pin is continuously pulled low, the device disables the CLKOUT pin. Frequency Dither In addition to EMI-aware PCB layout, extensive filtering, controlled switch node transitions, and shielding, switching frequency dithering is an effective way to mitigate EMI concerns in switching power supplies. Frequency dither helps to minimize peak emissions by spreading the emissions across a wide range of frequencies. The ARG81800 provides frequency dither by spreading the switching frequency ±5% using a triangular modulated wave of 0.5% switching frequency. The ARG81800 is capable of adding dither to the external clock applied on the SYNCIN pin. This unique feature allows the minimizing of electromagnetic emissions even when the device is using external clock. Frequency dither scheme can be disabled by connecting the CLKOUT pin to VREG pin. In master-follower configuration, the CLKOUT pin of the follower device should be connected to VREG to avoid double-dithering. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 fSYNC ± fDITHER + 180° VO2 SW2 VREG fSYNC ± fDITHER VO1 SW1 ARG81800 Master fSYNC ARG81800 Follower SYNC IN CLKOUT fSYNC ± fDITHER + 180° fSYNC ± fDITHER + 180° VO3 SW3 VREG SYNC IN CLKOUT ARG81800 Follower SYNC IN CLKOUT Figure 1: Master-Follower Configuration Table 1: PWM Frequency, CLKOUT, and Dithering Settings PWM Frequency and Dithering Device SYNCIN ARG81800/ ARG81800-1 Low fSW High fSW fSYNC fSYNC SW Frequency CLKOUT Frequency and Dithering Magnitude of Dithering Dither Modulation Frequency ±0.05 × fSW 0.005 × fSW ±0.05 × fSW 0.005 × fSW Transconductance Error Amplifier The transconductance error amplifier’s primary function is to control the regulator’s output voltage. The error amplifier is a three-terminal input device with two positive inputs and one negative input, as shown in Figure 2. The negative input is simply connected to the FB pin and is used to sense the feedback voltage for regulation. The error amplifier performs an “analog OR” selection between its positive inputs and operates according to the positive input with the lowest potential. The two positive inputs are used for soft-start and steady-state regulation. The error amplifier regulates to the soft-start pin voltage minus 400 mV during startup and to the internal reference (VREF) during normal operation. Frequency Magnitude of Dithering Dither Modulation Frequency Disabled/Off None None fSW + 180° ±0.05 × fSW 0.005 × fSW fSYNC + 180° ±0.05 × fSYNC 0.005 × fSYNC 400 mV Error Amplifier SS Pin COMP Pin VREF 800 mv FB Pin Figure 2: ARG81800 Error Amplifier Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD Compensation Components To stabilize the regulator, a series RC compensation network (RZ and CZ) must be connected from the output of the error amplifier (COMP pin) to GND as shown in the applications schematic. In most instances, an additional low-value capacitor (CP) should be connected in parallel with the RZ-CZ compensation network to reduce the loop gain at very high frequencies. However, if the CP capacitor is too large, the phase margin of the converter may be reduced. Calculation of RZ, CZ, and CP is covered in the Component Selection section of this datasheet. If a fault occurs or the regulator is disabled, the COMP pin is pulled to GND via the approximately 1 kΩ internal resistor and PWM switching is inhibited. Power MOSFETs The ARG81800 includes a 500 mΩ, high-side N-channel MOSFET and a 210 mΩ, low-side N-channel MOSFET to provide synchronous rectification. When the ARG81800 is disabled via the EN input being low or a fault condition, its output stage is tristated by turning off both the upper and lower MOSFETs. BOOT Regulator The ARG81800 includes a BOOT regulator to supply the power for a high-side MOSFET gate driver. The voltage across the BOOT capacitor is typically 4.8 V. If the BOOT capacitor is missing, the device will detect a BOOT overvoltage. Similarly, if the BOOT capacitor is shorted, the ARG81800 will detect a BOOT undervoltage. Also, the BOOT regulator has a current limit to protect itself during a short-circuit condition. Soft Start (Startup) and Inrush Current Control start, the voltage at the SS pin will rise from 400 mV to 1.2 V (a difference of 800 mV), the voltage at the FB pin will rise from 0 V to 800 mV, and the regulator output voltage will rise from 0 V to the set voltage determined by the feedback resistor divider. During startup, PWM switching frequency is reduced to 25% of fSW while FB is below 200 mV. If FB voltage is above 200 mV but below 400 mV, the switching frequency is 50% of fSW. At the same time, the transconductance of the error amplifier, gm, is reduced to half of nominal value when FB is below 400 mV. When FB is above 400 mV, the switching frequency will be fSW and the error amplifier gain will be the nominal value. The reduced switching frequency and error amplifier gain are necessary to help improve output regulation and stability when VOUT is very low. During low VOUT, the PWM control loop requires ontime near the minimum controllable on-time and very low duty cycles that are not possible at the nominal switching frequency. When the voltage at the soft start pin reaches approximately 1.2 V, the error amplifier will switch over and begin regulating the voltage at the FB pin to the fixed internal bandgap reference voltage of 800 mV. The voltage at the soft start pin will continue to rise to the internal LDO regulator output voltage. If the ARG81800 is disabled or a fault occurs, the internal fault latch is set and the capacitor at the SS pin is discharged to ground very quickly through a 2 kΩ pull-down resistor. The device will clear the internal fault latch when the voltage at the SS pin decays to approximately 200 mV. However, if the device enters hiccup mode, the capacitor at the SS pin is slowly discharged through a current sink, IHIC. Therefore, the soft start capacitor CSS not only controls the startup time but also the time between soft start attempts in hiccup mode. The soft start function controls the inrush current at startup. The soft start pin (SS) is connected to GND via a capacitor. When the ARG81800 is enabled and all faults are cleared, the SS pin sources the charging current ISS and the voltage on the soft start capacitor CSS starts ramping upward from 0 V. When the voltage at the soft start pin exceeds the soft start offset voltage (SS Offset), typically 400 mV, the error amplifier will ramp up its output voltage above the PWM Ramp Offset. At this instant, the top and bottom MOSFETs will begin switching. There is a small delay (tdSS) from the moment EN pin transitioning high to the moment soft start voltage reaching 400 mV to initiate PWM switching. Slope Compensation Immediately after the start of PWM switching, the error amplifier will regulate the voltage at the FB pin to the soft start pin voltage minus approximately 400 mV. During the active portion of soft where fSW is switching frequency in MHz and SE is slope compensation in A/µs. Internal slope compensation in ARG81800-1 is half of that (Equation 1) in ARG81800. The ARG81800 incorporates internal slope compensation that ensures stable operation at PWM duty cycles above 50% for a wide range of input/output voltages, switching frequencies, and inductor values. As shown in the functional block diagram, the slope compensation signal is added to the sum of the current sense and PWM Ramp Offset. The relationship between slope compensation and adjustable switching frequency is given by Equation 1: SE = 12.84 / (37.037 / fSW – 3) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD Pre-Biased Startup If the output of the buck regulator is pre-biased at a certain output voltage level, the ARG81800 will modify the normal startup routine to prevent discharging the output capacitors. As described in the Soft Start (Startup) and Inrush Current Control section, the error amplifier usually becomes active when the voltage at the soft start pin exceeds 400 mV. If the output is pre-biased, the voltage at the FB pin will be non-zero. The device will not start switching until the voltage at SS pin rises to approximately VFB + 400 mV. From then on, the error amplifier becomes active, the voltage at the COMP pin rises, PWM switching starts, and VOUT will ramp upward from the pre-bias level. Dropout The ARG81800 is designed to operate at extremely wide duty cycles to minimize any reduction in output voltage during dropout conditions (difference between input and output voltage drops to a minimum value) such as cold crank. During dropout, if the minimum off-time (85 ns typical) is reached for more than 5 consecutive switching cycles, the programmed switching frequency fSW is reduced by a factor of 4 and the off-time is extended to 115 ns (typical). While operating with reduced frequency, if the device further reaches minimum off-time (115 ns typical) for more than 35 consecutive switching cycles, it continues to operate with reduced frequency. Otherwise, the device toggles back to the programmed switching frequency fSW. In addition, during dropout operation, the soft start capacitor CSS will discharge so that if the input voltage increases, the output voltage recovers with a slew rate set by the soft start ramp. PGOOD Output The ARG81800 provides a Power Good (PGOOD) status signal to indicate if the output voltage is within the regulation limits. Since the PGOOD output is an open-drain output, an external pull-up resistor must be used as shown in the applications schematic. PGOOD transitions high when the output voltage, sensed at the FB pin, is within regulation. During start-up, PGOOD signal exhibits an additional delay of tdPG(SU) after FB pin voltage reaches the regulation voltage. This delay helps to filter out any glitches on the FB pin voltage. The PGOOD output is pulled low if either an undervoltage or overvoltage condition occurs or the ARG81800 junction temperature exceeds thermal shutdown threshold (TSD). The PGOOD overvoltage and undervoltage comparators incorporate a small amount of hysteresis (VFB(OV,HYS), VFB(UV,HYS)) to prevent chattering and deglitch filtering (tdPG(UV), tdPG(OV)) to eliminate false triggering. For other faults, PGOOD depends on the output voltage. It is important that the correct status of PGOOD is reported during either the input supply ramp up or ramp down. During a supply ramp up, the PGOOD is designed to operate in the correct state from a very low input voltage. Also, during supply ramp down, the PGOOD is designed to operate in the correct state down to a very low input voltage. Current Sense Amplifier The ARG81800 incorporates a high-bandwidth current sense amplifier to monitor the current through the top MOSFET. This current signal is used to regulate the peak current when the top MOSFET is turned on. The current signal is also used by the protection circuitry for the cycle-by-cycle current limit and hiccup mode short circuit protection Pulse-Width Modulation (PWM) The ARG81800 employs fixed-frequency, peak current mode control to provide excellent load and line regulation, fast transient response, and simple compensation. A high-speed comparator and control logic is included in the ARG81800. The inverting input of the PWM comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation signal, and a DC PWM Ramp offset voltage (Ramp Offset). At the beginning of each PWM cycle, the CLK signal sets the PWM flip flop, the bottom MOSFET is turned off, the top MOSFET is turned on, and the inductor current increases. When the voltage at the non-inverting of PWM comparator rises above the error amplifier output COMP, the PWM flip flop is reset, the top MOSFET is turned off, the bottom MOSFET is turned on, and the inductor current decreases. Since the PWM flip flop is reset, the dominant error amplifier may override the CLK signal in certain situations. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD Low-Power (LP) Mode The ARG81800 operates in ultralow IQ LP mode when PWM/ AUTO pin is pulled to logic low. If the PWM/AUTO pin transitions from logic high to logic low while output is in regulation, the device waits for 7 clock cycles before entering the LP mode. This delay provides adequate filtering to ensure no noise transients forces the device to erroneously enter LP mode. When LP mode is selected, the ARG81800 operates in continuous conduction PWM Mode until peak inductor current decreases to IPEAK(LP). When peak inductor current falls below IPEAK(LP), the LP comparator monitors FB node and regulates the output voltage in hysteretic manner. The reference for the LP comparator is calibrated approximately 0.5% above the PWM regulation point. The transition point from PWM to LP mode is defined by the input voltage, output voltage, and inductor value. The exact operation of the ARG81800 in LP mode is described below. When voltage on the COMP pin falls to the voltage corresponding to the ultralow IQ peak current threshold value, an internal clamp prevents the COMP voltage from falling further. This results in a momentary rise in the FB voltage beyond LP comparator upper threshold which causes the LP comparator to trip. Once the LP comparator trips, the device enters coast period during which MOSFET switching is terminated and the associated control circuitry is also shut down. This ensures a very low quiescent current is drawn from the input. The coast period terminates once the FB voltage falls below the LP comparator lower threshold. The device will fully power-up approximately after a 2.5 μs delay and the high-side MOSFET is repeatedly turned on, operating at the PWM switching frequency until the voltage at the FB pin rises again above the LP comparator threshold. The rate of rise of output voltage is determined by the input voltage, output voltage, inductor value, output capacitance, and load. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 20 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD Protection Features UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout (UVLO) comparator in the ARG81800 monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the start threshold (VINUV(ON), VIN rising) or the stop threshold (VINUV(OFF), VIN falling). The UVLO comparator incorporates some hysteresis (VINUV(HYS)) to help prevent on-off cycling of the regulator due to resistive or inductive drops in the VIN path during heavy loading or during startup. PULSE-BY-PULSE PEAK CURRENT PROTECTION (PCP) The ARG81800 monitors the current in the high-side MOSFET, and if the peak MOSFET current exceeds the pulse-by-pulse overcurrent limit ILIMHSx, the upper MOSFET is turned off and the bottom MOSFET is turned on until the start of the next clock pulse from the oscillator. The device includes leading edge blanking to prevent false triggering of pulse-by-pulse current protection when the upper MOSFET is turned on. Because of the addition of the slope compensation ramp to the sensed inductor current, the ARG81800 can deliver more current at minimum duty cycle and less current at maximum duty cycle. Figure 3 illustrates the relationship between the high-side MOSFET peak current limit and duty cycle. As shown, the peak current limit at minimum and maximum duty cycle remains fixed, but the relationship versus duty cycle is skewed with frequency due to the fixed minimum off-time. Given the relationship, it is best to use the IHSPKMIND and IHSPKMAXD current limits to calculate the current limit at any given duty cycle. During synchronization, slope compensation scales in a similar fashion as with RFSET although with slightly less accuracy. The exact current the buck regulators can support is heavily dependent on duty cycle (VIN, VOUT), ambient temperature, thermal resistance of the PCB, airflow, component selection, and nearby heat sources. 2.3 Peak Current Limit (A) The ARG81800 was designed to satisfy the most demanding automotive and non-automotive applications. In this section, a description of each protection feature is described and Table 2 summarizes the protections and their operation. 2.5 2.1 1.9 ARG81800 Max ARG81800 Min 1.7 ARG81800-1 Max ARG81800-1 Min 1.5 1.3 1.1 0.9 0.7 0.5 0 10 20 30 40 50 60 70 80 90 Duty Cycle (%) Figure 3: Peak Current Limit vs. Duty Cycle OVERCURRENT PROTECTION (OCP) AND HICCUP MODE An OCP counter and hiccup mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when the load is too high. When the soft-start ramp is active (t < tss), the OCP hiccup counter is disabled. The following two conditions must be met for the OCP counter to be enabled and begin counting: • SS pin voltage, VSS > VHIC/LP(EN) (2.3 V), and • Comp pin voltage, VCOMP clamped at its maximum voltage (OCP = 1) As long as these two conditions are met, the OCP counter remains enabled and will count pulses from the overcurrent comparator. If the COMP voltage decreases (OCP = 0), the OCP counter is cleared. Otherwise, if the OCP counter reaches HICOCP clock counts (120), PWM switching ceases, a hiccup latch is set, and the COMP pin is quickly pulled down by a relatively low resistance (1 kΩ). The hiccup latch also enables a small current sink connected to the SS pin (IHIC). This causes the voltage at the soft start pin to slowly ramp downward. When the voltage at the soft start pin decays to a low enough level (VSSRST, 200 mV), the hiccup latch is cleared, and the current sink is turned off. At Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 21 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD this instant, the SS pin will begin to source current (ISS) and the voltage at the SS pin will ramp upward. This marks the beginning of a new, normal soft start cycle as described earlier. When the voltage at the soft start pin exceeds the error amp voltage by approximately 400 mV, the error amplifier will force the voltage at the COMP pin to quickly slew upward and PWM switching will resume. If the short circuit/overload at the regulator output persists, another hiccup cycle will occur. Hiccups will repeat until the short circuit/overload is removed or the converter is disabled. If the short circuit/overload is removed, the device will soft start normally and the output voltage will automatically recover to the desired level. Thus, hiccup mode is a very effective protection for the short-circuit/overload condition. It avoids false trigger during short duration short-circuit/overload. On the other hand, for the extended short-circuit/overload duration, the reduced average power dissipation with hiccup mode of operation helps in lowering the temperature rise of the device and enhancing the system reliability. Note that OCP is the only fault that results in hiccup mode being ignored while VSS < 2.3 V. BOOT CAPACITOR PROTECTION The ARG81800 monitors the voltage across the BOOT capacitor to detect if the BOOT capacitor is missing or short-circuited. If the BOOT capacitor is missing, the regulator enters hiccup mode after 7 clock counts. If the BOOT capacitor is shorted, the device enters hiccup mode after 120 clock counts. Also, the boot regulator has a current limit to protect itself during a short-circuit condition. For a boot fault, hiccup mode operates virtually the same as described previously for overcurrent protection (OCP), with soft start ramping up and down for repeated hiccups. Boot faults are non-latched faults, so the device will automatically recover when the fault is removed. OVERVOLTAGE PROTECTION (OVP) The ARG8100 consists of an always-on overvoltage protection circuit that monitors output overvoltage on the BIAS pin, perhaps caused by the FB pin pulled to ground, high-side MOSFET leakage current, or line/load transients. During an overvoltage fault caused by any of the above events, the controller tries to reduce the output overvoltage by terminating the high-side MOSFET switching and pulsing the low side MOSFET with minimum off-time (tOFFmin) until FB returns to regulation. The ARG81800 waits for tdPG(OV) (120) clock counts before pulling the PGOOD low. If the overvoltage fault is not cleared even beyond tdPG(OV), PGOOD is pulled low and the device continuously attempts to reduce the output overvoltage. The output overvoltage protection threshold, at any given time, varies with the voltage on the feedback node as shown in Figure 4. If the BIAS pin is connected to VOUT, the maximum settable output voltage is limited to 20 V. Output Overvoltage Threshold (V) ARG81800 25 20 15 10 5 0 0 100 200 300 400 500 600 700 800 900 FB Voltage (mV) Figure 4: Output Overvoltage Threshold Variation with Increasing Feedback Voltage SW PIN PROTECTION Unlike most regulators, the ARG81800 protects itself when the SW pin is shorted to ground. If the SW pin is shorted to ground, there will be a very high current in the high-side MOSFET when it is turned on. The ARG81800 incorporates an internal secondary current protection to detect this unusually high current and turns off the high-side MOSFET if the high current persists for more than two consecutive switching cycles. After turning off the highside MOSFET, the device enables the hiccup latch and attempts to restart after hiccup latch is cleared. If the short to ground is removed, the regulator will automatically recover; otherwise, the device continues hiccupping. Unlike other hiccup mode protections, the SW pin protection is not delayed until soft start is completed, i.e., VSS > 2.3 V. PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS The ARG81800 is designed to satisfy the most demanding automotive applications. For example, the device has been carefully designed to withstand a short circuit to ground at each pin without causing any damage to the IC. In addition, care was taken when defining the device pinouts to optimize protection against pin-to-pin adjacent short circuits. For Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 22 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD example, logic pins and high-voltage pins are separated as much as possible. Inevitably, some low-voltage pins are located adjacent to high voltage pins, but in these instances, the low voltage pins are designed to withstand increased voltages, with clamps and/or series input resistance, to prevent damage to the device. THERMAL SHUTDOWN (TSD) The ARG81800 monitors internal junction temperature and shuts down the IC by disabling the switching pulses of high- and lowside MOSFETs if the junction temperature exceeds the Thermal Shutdown Threshold TTSD. Also, to prepare for a restart, the internal soft-start voltage (VSS) and the voltage at the COMP pin are pulled low until VSS < VSSRST. TSD is a non-latched fault, so the device automatically recovers if the junction temperature decreases by approximately 20°C. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 23 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD Table 2: Summary of ARG81800 Fault Modes and Operation During Fault Counting, before Hiccup Mode BOOT Charging PGOOD State Latched Fault Reset Condition Forced Turn-off Disabled Depends on VREG NO Automatic, VIN above UVLO start threshold fSW / 4 due to VOUT < 25%, responds to VCOMP Turned on if BOOT voltage is too low Not affected Depends on VOUT NO Automatic, Short removed Clamped to ILIMHS, then pulled low for Hiccup fSW responds to VCOMP Turned on if BOOT voltage is too low Not affected Depends on VOUT NO Automatic, Load current decreased Hiccup, after 2 clock count Pulled low via 1 kΩ resistor for hiccup Forced Turn-off Forced Turn-off Not affected Depends on VOUT NO Automatic, Short removed Boot capacitor open/missing Hiccup, after 7 clock counts Pulled low via 1 kΩ resistor for hiccup Forced Turn-off Turned off when fault occurs Disabled when fault occurs Depends on VOUT NO Automatic, Boot capacitor replaced Boot capacitor shorted (BOOTUV) Hiccup, after 120 clock counts Pulled low via 1 kΩ resistor for hiccup Forced Turn-off Turned off only during hiccup Disabled only during hiccup Depends on VOUT NO Automatic, Short removed Output overvoltage Not affected Transitions low via loop response Turned-off by low VCOMP Pulsed with Minimum off-time Disabled when VFB is too high Pulled low when VFB is too high NO Automatic, After VFB returns to normal range Output undervoltage Not affected Transitions high via loop response Active, Responds to VCOMP Turned on if BOOT voltage is too low Not affected Pulled low when VFB is too low NO Automatic, After VFB returns to normal range FSET shorted to GND or above 1.0 V Pulled Low Pulled Low Forced Turn-off Forced Turn-off Disabled Depends on VOUT NO Automatic FB open Not affected Transitions low via loop response Turned-off by low VCOMP Pulsed with Minimum off-time Disabled when VFB is too high Pulled low when VFB is too high NO Automatic, After VFB returns to normal range Thermal shutdown (TSD) Pulled low until VSS < VSSRST and TSD = 0 Pulled low until VSS < VSSRST and TSD = 0 Forced Turn-off Forced Turn-off Disabled Pulled low NO Automatic, Part cools down Fault Mode Internal Soft Start VIN undervoltage VCOMP High-Side MOFSET Low-Side MOFSET Pulled low via 2 kΩ resistor, No Hiccup Pulled low via 1 kΩ resistor, No Hiccup Forced Turn-off Output shorted to ground Hiccup, after 120 OCP clock counts Clamped to ILIMHS, then pulled low for Hiccup Output overcurrent, VOUT > 50% Hiccup, after 120 OCP clock counts High-side MOSFET overcurrent (SW short to GND) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 24 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 APPLICATION INFORMATION Design and Component Selection PWM SWITCHING FREQUENCY (R FSET) The PWM switching frequency is set by connecting a resistor from the FSET pin to signal ground. Figure 5 shows the relationship between the typical switching frequency (y-axis) and the FSET resistor (x-axis). For a required switching frequency (fSW), the FSET resistor value can be calculated as follows: Equation 2: = 37037 − 2.96 where fSW is in kHz and RFSET is in kΩ. Switching Frequency, fSW (kHz) 3000 2500 2000 1500 not occur at the maximum synchronized switching frequency (i.e., 1.5 × fSYNC should be less than the frequency fSW in Equation 3). OUTPUT VOLTAGE SETTING The output voltage of the ARG81800 is determined by connecting a resistive feedback divider (RFB1, RFB2) from the output node (VOUT) to the FB pin as shown in Figure 6. The feedback resistors must satisfy the ratio shown in Equation 4 below to produce the desired output voltage (VOUT). Equation 4: 1 2 = 0.8 − 1.0 1% resistors are recommended to maintain the output voltage accuracy. There are tradeoffs while choosing the value of the feedback resistors. If the series combination (RFB1 + RFB2) is too low, the light load efficiency of the regulator will be reduced. So to maximize the efficiency, it is best to choose large values for feedback resistors. On the other hand, large values of feedback resistors increases the parallel combination (RFB1//RFB2) and makes the regulator more susceptible to noise coupling onto the FB pin. VOUT 1000 RFB1 500 CFF FB 0 0 10 20 30 40 50 60 70 80 IFB RFB2 90 100 110 120 130 140 FSET Resistor, RFSET (kΩ) Figure 5: PWM Switching Frequency vs. RFSET While choosing the PWM switching frequency, the designer should be aware of the minimum controllable on-time, tON(MIN), of the ARG81800. If the required on-time of the system is less than the minimum controllable on-time, pulse skipping will occur and the output voltage will have increased ripple. The PWM switching frequency should be calculated using Equation 3, where VOUT is the output voltage, tON(MIN) is the minimum controllable on-time of the device (see EC table), and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). Equation 3: fSW VOUT < tON(MIN) × VIN(MAX) If an external clock fSYNC is used for synchronization, the base switching frequency should be chosen such that pulse skipping will Figure 6: Feedback Divider with Feedforward Capacitor Large values of RFB1 also impact the output voltage accuracy of the regulator. A small amount of leakage current IFB flowing into the FB pin increases the output voltage beyond the set regulation voltage. The output voltage of the regulator considering the FB pin leakage current is given by: Equation 5: = 0.8 × ( 1 + 1 2 )+ × 1 FB pin leakage current increases the output voltage beyond the set regulation voltage by an amount of IFBRFB1. The larger the value of RFB1, the larger is the inaccuracy in the output voltage. A feedforward capacitor (CFF) can be connected in parallel with Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 25 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 RFB1 to increase phase margin and loop crossover frequency for improving transient response of the regulator. Addition of CFF results in an additional zero and pole in the compensation network and boosts the loop phase at the crossover frequency. In general, CFF should be less than 25 pF. While large value of CFF increases the loop crossover frequency and reduces the phase margin, very small value of CFF will not have any effect. Optimal value of CFF can be calculated from the below equation. Equation 6: = 2× OUTPUT INDUCTOR (L O) 1 × 1× The ARG81800 incorporates a peak current mode control technique for closed-loop regulation of the output voltage. It is common knowledge that, without adequate slope compensation, a peak current mode controlled regulator will become unstable when duty cycle is near or above 50%. Hence, to stabilize the regulator over the complete range of its operating duty cycle, the ARG81800 employs a fixed internal slope compensation (SE). Many factors determine the selection of output inductor, such as switching frequency, output/input voltage ratio, transient response, and ripple current. A larger value inductor will result in less ripple current, which also results in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule of thumb for determining the output inductor is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum output current (IOUT(MAX)). The inductance value can be calculated from the following equation: Equation 7: = ×∆ ×(1− ) where ∆ILO is the peak-to-peak inductor ripple current, which is 0.3 × IOUT(MAX). Equation 8: ≥ × ( 1 − 0.18 × ( ) ) where LO is output inductance in µH and SE is external slope compensation provided in the Electrical Characteristics table. To avoid dropout, VIN(MIN) must be approximately 1 to 1.5 V above VOUT. Choose output inductor such that its inductance is greater than the maximum of inductance values calculated in Equation 7 and Equation 8. However, absolute maximum inductance should not exceed 1.1 × VOUT / SE(min). The saturation current of the inductor should be higher than the peak current capability of the ARG81800. Ideally, for output short-circuit conditions, inductor should not saturate, given the highest peak current limit (ILIMHSx) at minimum duty cycle. At the very least, the output inductor should not saturate with the peak operating current according to the following equation: Equation 9: ISAT_Lo > ILIMHSx(MAX) − ( 1.15 × × × ( ) ) where tON(MIN) is the minimum on-time provided in the Electrical Characteristics table. The typical DC output current capability of the regulator at any given duty cycle (D) is: Equation 10: IOUT(TYP) = ILIMHSx(TYP) − × − 2× × (1 − ) × After an inductor is chosen, it should be tested during output short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. A second constraint on inductor value arises from the loop stability at duty cycles greater than 50%. Although slope compensation is primarily required to avoid subharmonic oscillations, the inductor value calculated from the formula derived by Dr. Ridley, given below in Equation 8, can critically damp the pole pair at half the switching frequency. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 26 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 OUTPUT CAPACITORS (C O) The output capacitor of switching regulators filter the output voltage to provide an acceptable level of ripple on the output voltage, and they also store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (ΔVOUT ) is a function of the output capacitor parameters: CO, ESRCO, and ESLCO: Equation 11: ∆ =∆ × + 8× + ∆ − × × The type of output capacitors determine which terms of Equation 11 are dominant. For ceramic output capacitors, ESRCO and ESLCO are virtually zero, so the output voltage ripple will be dominated by the third term of Equation 11. The value of CO can be calculated as: Equation 12: ≥ 8× ∆ ×∆ Voltage ripple of a regulator using ceramic output capacitors can be reduced by increasing the total capacitance, reducing the inductor current ripple, or increasing the switching frequency. For electrolytic output capacitors, the value of capacitance will be relatively high, so the third term in Equation 11 will be very small and the output voltage ripple will be determined primarily by the first two terms: Equation 13: ∆ =∆ × + − × Voltage ripple of a regulator using electrolytic output capacitors can be reduced by: decreasing the equivalent ESRCO and ESLCO by using a high quality capacitor, adding more capacitors in parallel, or reducing the inductor current ripple. As the ESR of some electrolytic capacitors can be quite high, Allegro recommends choosing a quality capacitor for which the ESR or the total impedance is clearly documented in the capacitor datasheet. Also, ESR of electrolytic capacitors usually increases significantly at cold ambient temperatures, as much as 10 times, which increases the output voltage ripple and in most cases reduces the stability of the system. The transient response of the regulator depends on the quantity and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (high diO/dt), the change in the output voltage, using electrolytic output capacitors, is: Equation 14: ∆ =∆ × + × When ceramic capacitors are used in the output, the output voltage deviation during load transients depends on the bulk output capacitance along with various other factors. To calculate the bulk ceramic capacitance required, the entire load transient duration can be divided into two stages: large signal and small signal. During large signal load transients, immediately after the transient event, the output voltage deviates from the nominal value due to large mismatch in the load current requirement and the inductor current. The output voltage deviation during this interval is maximum and depends on output inductor, bulk output capacitance, and closed-loop crossover frequency. For designs with higher crossover frequency, the controller typically saturates the duty cycle, i.e., either minimum or maximum. For a chosen output inductor and crossover frequency values, the output voltage deviation can be minimized by increasing the output bulk capacitance. In the case of a buck converter, operating with a low duty cycle, the step-down load transient is more severe and hence the output capacitance should be determined for this scenario. The bulk ceramic output capacitance required is given by: Equation 15: , = 2× ∆ 2 × ×∆ , where ∆IO is the magnitude of the change in the load current, ∆VOUT,spec is the maximum allowed output voltage deviation during load transient event. Gradually, as the mismatch between the load current and the inductor current becomes small, the output voltage deviation also reduces, resembling a small signal transient event. Eventually, during small signal transient interval, the error amplifier brings the output voltage back to its nominal value. The speed with which the error amplifier brings the output voltage back into regulation depends mainly on the loop crossover frequency. A higher crossover frequency usually results in a shorter time to return to the nominal set voltage. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 27 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 Equation 18: OUTPUT VOLTAGE RIPPLE – ULTRALOW-I Q LP MODE After choosing output inductor and output capacitor(s), it is important to calculate the output voltage ripple (VPP(LP)) during ultralow-IQ LP mode. With ceramic output capacitors, the output voltage ripple in PWM mode is usually negligible, but this is not the case during LP mode. In LP mode, the peak inductor current during on-time of the highside switch is limited to IPEAK(LP). Also, in LP mode, the low-side switch is constantly turned off thereby forcing the regulator to operate in Discontinuous Conduction Mode (DCM) in order to reduce switching losses. A LP comparator monitors the output voltage on the FB pin and allows the regulator to switch until the FB pin voltage is greater than 0.5% of its nominal value (0.8 V). When FB voltage is greater than 0.804 V, the ARG81800 coasts by terminating the switching pulses. During coasting, the device shuts down most of its internal control circuitry to ensure very low quiescent current is drawn from the input. The number of switching pulses, in LP mode, required to coast the device depend on various factors including: input voltage, output voltage, load current, output inductor, and output capacitor. If ARG81800 starts coasting after a single switching pulse, then the output voltage ripple would be dictated by this single pulse. The peak inductor current without slope compensation (IPEAK_LO) is given by: Equation 16: IPEAK_LO = − − ×( × VOUT VPP(LP) ILo IPEAK_Lo IOUT t1 t2 tOFF tON Figure 7: Output Voltage Ripple in LP Mode During on-time interval, the length of time for the inductor current to rise from 0 A to IOUT is: Equation 19: 1 = − − _ × ×( ( ) + ( )) Equation 20: Equation 17: _ × During off-time interval, the length of time for the inductor current to fall from IOUT to 0 A is: IPEAK(LP) × 1+ − where IPEAK(LP) is the peak inductor current, specified in the Electrical Characteristics table, at which device enters into LP mode. Referring to Figure 7, on-time and off-time calculations are given as: = _ = 2 = × Given the peak inductor current (IPEAK_L) and the rise and fall times (tON and tOFF) for the inductor current, the output voltage ripple for a single switching pulse can be calculated as follows: Equation 21: ( ) + ( )) ( ) = _ 2× − ×( + − 1 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com − 2) 28 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 Three factors should be considered when choosing the input capacitors. First, the capacitors must be chosen to support the maximum expected input surge voltage with adequate design margin. Second, the capacitor RMS current rating must be higher than the expected RMS input current to the regulator. Third, the capacitors must have enough capacitance and a low enough ESR to limit the input voltage dV/dt to much less than the hysteresis of the UVLO circuitry (250 mV nominal) at maximum loading and minimum input voltage. The input capacitors must deliver an RMS current (IRMS) given by: Equation 22: = ×√ IRMS/IOUT INPUT CAPACITORS 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle, D(%) × (1 − ) where the duty cycle (D) is defined as: Figure 8: Normalized Input Capacitor Ripple versus Duty Cycle Equation 23: ≈ Figure 8 shows the normalized input capacitor RMS current versus duty cycle. To use this graph, simply find the operational duty cycle (D) on the x-axis and determine the input/output current multiplier on the y-axis. For example, at a 20% duty cycle, the input/output current multiplier is 0.40. Therefore, if the regulator is delivering 1.0 A of steady-state load current, the input capacitor(s) must support 0.40 × 1.0 A or 0.4 A RMS. A good design should consider the DC bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. This effect is very pronounced with the Y5V and Z5U temperature characteristic devices (as much as 90% reduction), so these types should be avoided. The X5R, X7R, and X8R type capacitors should be the primary choices due to their stability versus both DC bias and temperature. The input capacitor(s) must limit the voltage deviations at the VIN pin to significantly less than the device UVLO hysteresis during maximum load and minimum input voltage condition. The following equation allows to calculate the minimum input capacitance required: For all ceramic capacitors, the DC bias effect is even more pronounced on smaller sizes of device case, so a good design uses the largest affordable case size (such as 1206 or 1210). Also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst case transient input voltage (such as a load dump as high as 40 V for automotive applications). Equation 24: BOOTSTRAP CAPACITOR ≥ × 0.85 × × (1 − ) ×∆ ( ) where ΔVIN(MIN) is chosen to be much less than the hysteresis of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recommended), and fSW is the nominal PWM frequency. The D × (1–D) term in Equation 22 has an absolute maximum value of 0.25 at 50% duty cycle. So, for example, a very conservative design based on IOUT = 1.0 A, fSW = 0.5 MHz, D × (1–D) = 0.25, and ΔVIN =150 mV yields: ≥ 1.0 × 0.25 = 1.95 µ 0.85 × 0.5 × 106 × 150 × 10−3 A bootstrap capacitor must be connected between the BOOT and SW pins to provide floating gate drive to the high-side MOSFET. Usually, 47 nF is an adequate value. This capacitor should be a high-quality ceramic capacitor, such as an X5R or X7R, with a voltage rating of at least 16 V. SOFT START AND HICCUP MODE TIMING (C SS) The soft start time of the ARG81800 is determined by the value of the capacitance (CSS) at the soft start pin. When the ARG81800 is enabled, the SS pin sources the charging current ISS and the voltage across the soft start capacitor CSS starts ramping upward from 0 V. However, PWM switching will begin only after the voltage across the CSS rises above 400 mV. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 29 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 The soft start delay (tdSS) can be calculated using the equation below: Equation 25: d = × ( 0.4 ) If the device is starting with a very heavy load, a very fast soft start time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. This occurs because the sum of the full load current, the inductor ripple current, and the additional current required to charge the output capacitors COMPENSATION COMPONENTS (R Z, C Z, AND C P) The objective of the selection of the compensation components is to ensure adequate stability margins to avoid instability issues, to maintain a high loop gain at DC to achieve excellent output voltage regulation and to obtain a high loop bandwidth for superior transient response. To a first order, the closed-loop model of a peak current mode controlled regulator can be broken into two blocks as shown below in Figure 9. Power Stage Equation 26: VC = × A/V is higher than the pulse-by-pulse current threshold. This phenomenon is more pronounced when using high value electrolytic type output capacitors. To avoid prematurely triggering hiccup mode, the soft start capacitor (CSS) should be calculated according to equation below: Equation 27: ≥ × × 0.8 × where VOUT is the output voltage, CO is the output capacitance, ICO is the amount of current allowed to charge the output capacitance during soft start (0.1 A < ICO < 0.3 A is recommended). The soft start time (tSS) can be calculated as below: Equation 28: = 0.8 × gmPOWER ( ) Higher values of ICO result in faster soft start times. However, lower values of ICO ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an ICO of 0.1 A and increasing it only if the soft start time is too slow. If a non-standard capacitor value for CSS is calculated, the next larger value should be used. When the device is in hiccup mode, the soft start capacitor is used as a timing capacitor and sets the hiccup period. The soft start pin charges the soft start capacitor with ISS during a startup attempt and discharges the same capacitor with IHIC between startup attempts. Because the ratio of ISS:IHIC is approximately 4:1, the time between hiccups will be about four times as long as the startup time. Therefore, the effective duty cycle will be very low and the junction temperature will be kept low. RZ CZ VOUT CO RL RFB1 FB Pin COMP Pin CP IOUT gm = 750 µA/V RO RFB2 VFB 0.8 V Reference Error Amplifier Figure 9: Closed-Loop Model of Peak Current Mode Controlled Regulator POWER STAGE The power stage includes the output filter capacitor, CO, the equivalent load, RL, and the inner current loop which consists of the PWM modulator and the output inductor, LO. The inner current loop, with a first-order approximation, can be effectively modeled as a transconductance amplifier that converts the control voltage (VC) from the error amplifier to a peak output inductor current with an equivalent gain gmPower. Although, the peak current through the inductor is being controlled—neglecting the inductor ripple current—it is acceptable to replace it with output current IOUT. From a small-signal point of view, the current mode control loop behaves like a current source and therefore the power inductor can be ignored. The output capacitor integrates the ripple current through the inductor, effectively forming a single pole with the output load. A control-to-output transfer function between the control voltage (VC), output of the error amplifier in the feed- Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 30 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 back loop, and the regulator output voltage (VOUT) describes the dynamics of the power stage. The DC gain of the power stage, i.e., control-to-output transfer function, is given by: Equation 29: ( ) = × where gmPOWER is the equivalent gain of the inner current loop (specified in the Electrical Characteristics table) and RL is the load resistance. The control-to-output transfer function has a pole fP(CO), formed by the output capacitance (CO) and load resistance (RL), located at: Equation 30: ( ) = 2 × 1 × The control-to-output transfer function has a zero fZ(CO), formed by the output capacitance (CO) and its associated ESR, located at: Equation 31: ( ) = 2 × 1 × For a design with very low-ESR type output capacitors (such as ceramic or OSCON output capacitors), the ESR zero, fZ(CO), is usually at a very high frequency so it can be ignored. On the other hand, with high-ESR electrolytic output capacitors, the ESR zero falls below or near the 0 dB crossover frequency of the closed-loop; hence, it should be cancelled by the pole formed by the CP capacitor and the RZ resistor discussed and identified later as fP2(EA). ERROR AMPLIFIER where AVOL is the open-loop DC gain of the error amplifier (specified in the Electrical Characteristics table). The DC gain of the error amplifier is 65 dB (equivalent to 1778) and with a gm value of 750 μA/V, the effective output impedance, RO, of the amplifier is: Equation 33: = 1778 = 2.37 750 × 10−6 Ω Typically, RO ≫ RZ and CZ ≫ CP, which simplifies the derivation of the transfer function of the Type-II compensated error amplifier. The transfer function has a (very) low frequency pole fP1(EA) dominated by the error amplifier output impedance RO and the compensation capacitor CZ: Equation 34: 1( ) = ( ) = 2 × 1 × The transfer function of the Type-II compensated error amplifier also has a zero at frequency fZ(EA) caused by the resistor RZ and the capacitor CZ: Equation 35: 2 × 1 × Lastly, the transfer function of the Type-II compensated error amplifier has a (very) high frequency pole fP2(EA) dominated by the resistor RZ resistor and the capacitor CP: Equation 36: The error amplifier, as a part of the output voltage feedback loop, comprises a transconductance amplifier with an external Type-II compensation formed by RZ-CZ-CP network. A Type-II compensated error amplifier introduces two poles and a zero. The placement of these poles and zero should be such that the closed-loop system has sufficient stability margins and high bandwidth (loop crossover frequency) and provides optimal transient response. The DC gain of the feedback loop, including the error amplifier and the feedback resistor divider is given by: 2( ) = 2 × 1 × Although there are many different approaches for designing the feedback loop, a good design approach attempts to maximize the closed-loop system stability, while providing a high bandwidth and optimized transient response. A generalized tuning procedure is presented below to systematically determine the values of compensation components (RZ, CZ, and CP) in the feedback loop. Equation 32: ( ) = = × × 1 + 2 2 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 31 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 A GENERALIZED TUNING PROCEDURE 1. Choose the system bandwidth (fC). This is the frequency at which the magnitude of the gain crosses 0 dB. Recommended values for fC, based on the PWM switching frequency, are in the range fSW / 20 < fC < fSW / 10. A higher value of fC generally provides a better transient response, while a lower value of fC generally makes it easier to obtain higher gain and phase margins. 2. Calculate the RZ resistor value. This sets the system bandwidth (fC): Equation 37: = × × 2 × × 3. Calculate the range of values for the CZ capacitor. Use the following: Equation 38: 4 × 2 × < < 2 × 1 × 1.5 × ( ) To maximize system stability, i.e., high gain and phase margins, use a higher value of CZ. To optimize transient recovery time, although at the expense of low stability margins, use a lower value of CZ. 4. Calculate the frequency of the ESR zero fZ(CO) formed by the output capacitor(s) by using Equation 31 (repeated here): ( ) = 2 × 1 × If fZ(CO) is at least one decade higher than the target crossover frequency fC, then fZ(CO) can be ignored. This is usually the case for a design using ceramic output capacitors. Use Equation 36 to calculate the value of CP by setting fP2(EA) to either 5 × fC or fSW / 2, whichever is higher. Alternatively, if fZ(CO) is near or below the target crossover frequency fC, then use Equation 36 to calculate the value of CP by setting fP2(EA) equal to fZ(CO). This is usually the case for a design using high ESR electrolytic output capacitors. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 32 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 CIN VIN BIAS GND BOOT PGND FSET RFSET 0.1 μF SW LO VOUT RFB1 FB CO RFB2 VREG 4.7 μF 10 kΩ CFF PGOOD COMP RZ CP CZ Figure 10: Applications Schematic Showing Component Locations Table 3: Recommended External Components (for load transient slew rate < 50 mA/µs) ARG81800 VOUT fSW RFSET LO CO COMP Components (BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components RZ CZ CP RFB1 CIN(MIN) RFB2 CFF 5.0 V 2.15 MHz 14.3 kΩ 4.7 µH 20 µF 51.1 kΩ 1.2 nF 82 pF 732 kΩ 137 kΩ 4.7 pF 1.0 µF 3.3 V 2.15 MHz 14.3 kΩ 3.3 µH 20 µF 40.2 kΩ 2.2 nF 68 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF 5.0 V 400 kHz 90.9 kΩ 22 µH 33 µF 24.9 kΩ 2.2 nF 100 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF 3.3 V 400 kHz 90.9 kΩ 15 µH 47 µF 29.4 kΩ 2.2 nF 47 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF ARG81800-1 VOUT fSW RFSET LO CO COMP Components (BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components RZ CZ CP RFB1 CIN(MIN) RFB2 CFF 5.0 V 2.15 MHz 14.3 kΩ 9.1 µH 20 µF 150 kΩ 1.0 nF 47 pF 732 kΩ 137 kΩ 4.7 pF 1.0 µF 3.3 V 2.15 MHz 14.3 kΩ 7.5 µH 20 µF 60.4 kΩ 1.0 nF 33 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF 5.0 V 400 kHz 90.9 kΩ 43 µH 33 µF 51.1 kΩ 2.2 nF 47 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF 3.3 V 400 kHz 90.9 kΩ 33 µH 47 µF 49.9 kΩ 2.2 nF 47 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF Note 1: Components were chosen to maintain LP ripple voltage and minimize voltage droop during LP to PWM changeover. Note 2: CFF is chosen to offset 15 to 25 pF of stray capacitance at the FB pin. Table 4: Recommended External Components (for load transient slew rate > 50 mA/µs) ARG81800 VOUT fSW 5.0 V 2.15 MHz 3.3 V 5.0 V 3.3 V RFSET LO CO COMP Components (BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components CIN(MIN) RZ CZ CP RFB1 RFB2 CFF 42 µF 10.0 kΩ 5.6 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 14.3 kΩ 4.7 µH 1.0 µF 2.15 MHz 14.3 kΩ 3.3 µH 42 µF 8.06 kΩ 9.1 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF 400 kHz 90.9 kΩ 22 µH 55 µF 5.11 kΩ 9.1 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF 400 kHz 90.0 kΩ 15 µH 69 µF 5.23 kΩ 9.1 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF ARG81800-1 VOUT fSW RFSET LO CO COMP Components (BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components RZ CZ CP RFB1 CIN(MIN) RFB2 CFF 5.0 V 2.15 MHz 14.3 kΩ 9.1 µH 42 µF 30.1 kΩ 5.6 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 3.3 V 2.15 MHz 14.3 kΩ 7.5 µH 42 µF 12.1 kΩ 5.6 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF 1.0 µF 5.0 V 400 kHz 90.9 kΩ 43 µH 55 µF 10.0 kΩ 9.1 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF 3.3 V 400 kHz 90.9 kΩ 33 µH 69 µF 10.0 kΩ 9.1 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF Note 1: Components were chosen to maintain LP ripple voltage and minimize voltage droop during LP to PWM changeover. Note 2: CFF is chosen to offset 15 to 25 pF of stray capacitance at the FB pin. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 33 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 POWER DISSIPATION AND THERMAL CALCULATIONS The total power dissipated in the ARG81800 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due to the switching of the high-side power MOSFET (PSWH), the power dissipated due to the conduction of rms current in the high-side MOSFET (PCH) and low-side MOSFET (PCL), power dissipated due to the low-side MOSFET body diode conduction during the non-overlap time (PNO) and the power dissipated by both high-side and low-side gate drivers (PDRIVER). The power dissipated from the VIN supply current (with BIAS pin open) can be calculated using Equation 39: Equation 39: = +( × − , )×( H L) + × where VIN is the input voltage, IIN,PWM is the input quiescent current drawn by the ARG81800 in PWM mode (see EC table), VGS is the MOSFET gate drive voltage (typically 4.8 V), QGH and QGL are the internal high-side and low-side MOSFET gate charges (approximately 0.3 nC and 0.6 nC, respectively), and fSW is the PWM switching frequency. The power dissipated by the high-side MOSFET during PWM switching can be calculated using Equation 40: Equation 40: ×( + 2 × = The exact rise and fall times at the SW node will depend on the external components and PCB layout, so each design should be measured at full load. Approximate values for both tr and tf range from 10 to 20 ns. The power dissipated in the high-side MOSFET while it is conducting can be calculated using Equation 41: Equation 41: 2 = ( , × ( ) ( × ) 2 + ∆ 2 12 )× = 2 ( , × ( = 1− ) )×( 2 + ∆ 2 12 )× ( ) where IOUT is the regulator output current, ΔILO is the peakto-peak inductor ripple current, RDS(ON)H is the on-resistance of the high-side MOSFET, RDS(ON)L is the on-resistance of the low-side MOSFET. The RDS(ON) of both MOSFETs have some initial tolerance plus an increase from self-heating and elevated ambient temperatures. A conservative design should accommodate an RDS(ON) with at least 15% initial tolerance plus 0.39%/°C increase due to temperature. The power dissipated in the low-side MOSFET body diode during the non-overlap time can be calculated as follows: Equation 43: = × ×2× × where VSD is the source-to-drain voltage of the low-side MOSFET (typically 0.60 V), and tNO is the non-overlap time (15 ns typical). The power dissipated in the internal gate drivers can be calculated using Equation 44: Equation 44: )× where VIN is the input voltage, IOUT is the regulator output current, fSW is the PWM switching frequency, tr and tf are the rise and fall times measured at the switch node. = Equation 42: ( ) Similarly, the conduction losses dissipated in the low-side MOSFET while it is conducting can be calculated by the following equation: =( )× + × where VGS is the gate drive voltage (typically 4.8 V). Finally, the total power dissipated in the ARG81800 is given by: Equation 45: = + + + + + The average junction temperature (TJ) can be calculated as follows: Equation 46: = × + where PTOTAL is the total power dissipated from Equation 45, RθJA is the junction-to-ambient thermal resistance (37°C/W on a 4-layer PCB), and TA is the ambient temperature. RθJA includes the thermal impedance from junction to case, RθJC and the thermal impedance from case to ambient, RθCA. RθCA is generally determined by the amount of copper that is used underneath and around the device on the printed circuit board. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 34 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD The maximum allowed power dissipation depends on how efficiently heat can be transferred from the junction to the ambient air, i.e., minimizing the RθJA. As with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. There are tradeoffs between ambient operating temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and other nearby heat sources. Even a small amount of airflow will reduce the junction temperature considerably. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 35 ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD EMI/EMC AWARE PCB DESIGN The ARG81800 is designed to minimize electromagnetic (EM) emissions when proper PCB layout techniques are adopted. A good PCB layout is also critical for the ARG81800 to provide clean and stable output voltages. Design guidelines for EMI/EMC-aware PCB layout are presented below. Figure 10 shows a typical application schematic of a synchronous buck regulator IC with critical power paths/loops. 1. Place the ceramic input capacitors as close as possible to the VIN pin and PGND pins to make the loop area minimal, and the traces of the input capacitors to VIN pin should be short and wide to minimize the inductance. This critical loop is shown as trace 1 in Figure 11. The bulk/electrolytic input capacitor can be located further away from VIN pin. The input capacitors and ARG81800 IC should be on the same side of the board with traces on the same layer. 2. The loop from the input supply and capacitors, through the highside MOSFET, into the load via the output inductor, and back to ground should be minimized with relatively wide traces. 3. When the high-side MOSFET is off, free-wheeling current flows from ground, through the synchronous low-side MOSFET, into the load via the output inductor, and back to ground. This loop should be minimized and have relatively wide traces. This loop is shown as trace 2 in Figure 11. 4. Place the output capacitors relatively close to the output inductor (LO) and the ARG81800. Ideally, the output capacitors, output inductor and the ARG81800 should be on the same layer. Connect the output inductor and the output capacitors with a fairly wide trace. The output capacitors must use a ground plane to make a very low-inductance connection to the GND. These critical connections are shown as trace 3 in Figure 11. 5. Place the output inductor (LO) as close as possible to the SW pin with short and wide traces. This critical trace is shown as trace 4 in Figure 11. The voltage at SW node transitions from 0 V to VIN with a high dv/dt rate. This node is the root cause of many noise issues. It is suggested to minimize the SW copper area to minimize the coupling capacitance between SW node and other noise-sensitive nodes; however, the SW node area cannot be too small in order to conduct high current. A ground copper area can be placed underneath the SW node to provide additional shielding. Also, noise sensitive analog signals (like FB, COMP) should not be routed near the SW polygon. 6. Place the feedback resistor divider (RFB1 and RFB2) very close to the FB pin. Route the ground side of RFB2 as close as possible to the ARG81800. 7. Place the compensation components (RZ, CZ, and CP) as close as possible to the COMP pin. Also route the ground side of CZ and CP as close as possible to the ARG81800. 8. Place the FSET resistor as close as possible to the FSET pin; Place the soft start capacitor CSS as close as possible to the SS pin. 9. The output voltage sense trace (from VOUT to RFB1) should be routed as close as possible to the load to obtain the best load regulation. 10. Place the bootstrap capacitor (CBOOT) near the BOOT pin and keep the routing from this capacitor to the SW polygon as short as possible. This critical trace is shown as trace 5 in Figure 11. 11. A two-layer (TOP and BOT) PCB is sufficient for better thermal performance. 12. When connecting the input and output ceramic capacitors, use multiple vias to GND planes and place the vias as close as possible to the pads of the components. Do not use thermal reliefs around the pads for the input and output ceramic capacitors. 13. Place all the components on the TOP layer and limit the routing only to the top layer. Use BOT layer as GND plane. 14. To minimize thermal resistance, extend ground planes on TOP layer as much as possible and use thermal vias to connect them to GND plane in BOT layer. 15. To minimize PCB losses and improve system efficiency, the power traces should be as wide as possible. 16. EMI/EMC issues are always a concern. Allegro recommends having placeholder for an RC snubber from SW to ground. The resistor should be 0805 or 1206 size. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 36 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 CREG 1 RPullup EN VIN VREG RFB 1 CLK OUT Internal Regulator BOOT CBoot Boot Regulator CIN PGOOD BIAS 5 FB SW COMP CZ CP 2 SYNC IN RFSET CSS RZ SS VOUT VREG FSET RFB 2 LO 4 GND RL CO PGND 1 3 Figure 11: PCB Layout for Minimizing EM Emissions 6.8 μH, 2.5 A VBAT: 3.5 V to 36 V 0.1 μF 50 V, X7R 4.7 μF 50 V, X7R 10 μF 50 V, X7R 10 μF 50 V, X7R 4.7 μF 50 V, X7R VIN GND PGND 0.1 μF 50 V, X7R BIAS BOOT 0.1 μF 16 V, X7R SW SS 22 nF 16 V, X7R 4.7 μF 16 V, X7R VREG 2 × 10 μF 16 V, X7R 0.25 W 0.1 μF 16 V, X7R 680 pF 50 V, COG SYNC IN 14.3 kΩ fSW = 2.15 MHz 3.3 V / 1 A 10 Ω PWM/AUTO EN FSET 3.3 μH, 2.5 A 301 kΩ FB 10 kΩ 95.3 kΩ PGOOD CLK OUT COMP 4.7 pF 50 V, COG 2.2 nF 50 V, COG 10 pF 50 V, COG 30.1 kΩ Figure 12: 3.3 V, 1 A Buck Regulator with Input EMI Filter Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 37 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 45 45 Horizontal Polarization 40 35 35 EN 55025 (2008) Automotive Components PK EN 55025 (2008) Automotive Components PK 30 25 20 EN 55025 (2008) Automotive Components AV 15 Level in dBµV/m Level in dBµV/m 30 25 20 10 5 5 0 0 50 60 70 80 90 100M 200 30M 330M EN 55025 (2008) Automotive Components AV 15 10 30M Vertical Polarization 40 50 60 70 80 90 100M 200 330M Frequency in Hz Frequency in Hz Figure 13: Radiated EMI – Biconical Antenna VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz Figure 14: Radiated EMI – Biconical Antenna VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz 50 80 45 70 EN 55025 (2008) Automotive Radiated Class 5 PK 40 60 35 50 25 EN 55025 (2008) Automotive Radiated Class 5 AV 20 15 10 Level in dBµV Level in dBµV/m 30 EN 55025 (2008) Automotive Voltage PK 40 30 EN 55025 (2008) Automotive Voltage AV 20 10 5 0 0 -10 -5 150k 300 400 500 800 1M 2M 3M 4M 5M 6 8 10M 20M 30M Frequency in Hz Figure 15: Radiated EMI – Monopole Antenna VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz 150k 300 400500 8001M 2M 3M 4M5M 6 8 10M 20M 30M 40 50 60 80 108M Frequency in Hz Figure 16: Conducted EMI VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz EMI test results are obtained using standard evaluation board with Input EMI filter and Snubber (see Figure 12 above). Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 38 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 TYPICAL REFERENCE DESIGNS U1 VBAT: 3.5 V to 36 V C2 VIN GND PGND C3 R1 BIAS BOOT SW FB PWM/AUTO EN ARG81800 SYNCIN C8 L1 VOUT R2 C4 R3 PGOOD FSET CLKOUT COMP C10 C9 C5 C6 R6 C7 VREG SS R4 C1 C11 R5 Figure 17: Reference Design 1 – AUTO Mode with CLKOUT enabled VIN = 3.5 to 36 V, VOUT = 3.3 V, IOUT = 0 to 1.0 A, fSW = 2.15 MHz Table 5: Reference Design 1 – Recommended Bill of Materials Designator Description Value Footprint Manufacturer Manufacturer P/N C1 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D C2 Capacitor, X7R 4.7 µF, 50 V 1206 Murata GRJ31CR71H475KE11L C3 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D C4 Capacitor, X7R 0.1 µF, 50 V 1206 Murata GCM319R71H104KA37J C5 Capacitor, X7R 10 µF, 16 V 1210 Murata GRM32DR71C106KA01L C6 Capacitor, X7R 10 µF, 16 V 1210 Murata GRM32DR71C106KA01L C7 Capacitor, C0G (NP0) 4.7 pF, 50 V 0603 Murata GCM1885C1H4R7BA16D C8 Capacitor, X7R 4.7 µF, 16 V 0805 Murata GCJ21BR71C475KA01L C9 Capacitor, X7R 22 nF, 50 V 0603 Murata GRM188R71H223KA01D C10 Capacitor, X7R 2.2 nF, 50 V 0603 Murata GCM188R71H222KA37D C11 Capacitor, C0G (NP0) 10 pF, 50 V 0603 Kemet C0603C100J5GACTU L1 Inductor 3.3 µH, 2 A 5.2 mm × 5.2 mm Wurth Electronics 74437334033 R1 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V R2 Resistor, 1%, 1/10 W 301 kΩ 0603 Panasonic ERJ-3EKF3013V R3 Resistor, 1%, 1/10 W 95.3 kΩ 0603 Panasonic ERJ-3EKF9532V R4 Resistor, 1%, 1/10 W 14.3 kΩ 0603 Panasonic ERJ-3EKF1432V R5 Resistor, 1%, 1/10 W 30.1 kΩ 0603 Panasonic ERJ-3EKF3012V R6 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V U1 Allegro IC ARG81800 QFN20_4x4 Allegro ARG81800KESJSR Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 39 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 U1 VBAT: 3.5 V to 36 V C2 VIN GND PGND C3 R1 BIAS BOOT SYNCIN EN C1 SW FB ARG81800-1 C4 PGOOD FSET CLKOUT C5 C6 R6 C7 VREG SS R4 VOUT R3 PWM/AUTO C8 L1 R2 COMP C10 C9 C11 R5 Figure 18: Reference Design 2 – Forced PWM Mode with CLKOUT disabled VIN = 3.5 to 36 V, VOUT = 5.0 V, IOUT = 0 to 0.5 A, fSW = 400 kHz Table 6: Reference Design 2 – Recommended Bill of Materials Designator Description Value Footprint Manufacturer Manufacturer P/N C1 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D C2 Capacitor, X7R 4.7 µF, 50 V 1206 Murata GRJ31CR71H475KE11L GCM188R71H104KA57D C3 Capacitor, X7R 0.1 µF, 50 V 0603 Murata C4 Capacitor, X7R 0.1 µF, 50 V 1206 Murata GCM319R71H104KA37J C5 Capacitor, X7R 22 µF, 16 V 1210 Murata GRM32ER71C226MEA8L C6 Capacitor, X7R 10 µF, 16 V 1210 Murata GRM32DR71C106KA01L C7 Capacitor, C0G (NP0) 4.7 pF, 50 V 0603 Murata GCM1885C1H4R7BA16D C8 Capacitor, X7R 4.7 µF, 16 V 0805 Murata GCJ21BR71C475KA01L C9 Capacitor, X7R 22 nF, 50 V 0603 Murata GRM188R71H223KA01D C10 Capacitor, X7R 2.2 nF, 50 V 0603 Murata GCM188R71H222KA37D C11 Capacitor, C0G (NP0) 10 pF, 50 V 0603 Kemet C0603C100J5GACTU L1 Inductor 47 µH, 2.2A 10 mm × 10 mm Wurth Electronics 7447714470 R1 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V R2 Resistor, 1%, 1/10 W 732 kΩ 0603 Panasonic ERJ-3EKF7323V R3 Resistor, 1%, 1/10 W 140 kΩ 0603 Panasonic ERJ-3EKF1403V R4 Resistor, 1%, 1/10 W 90.9 kΩ 0603 Panasonic ERJ-3EKF7152V R5 Resistor, 1%, 1/10 W 34 kΩ 0603 Panasonic ERJ-3EKF3402V R6 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V U1 Allegro IC ARG81800-1 QFN20_4x4 Allegro ARG81800KESJSR-1 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 40 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use (Reference JEDEC MO-220WGGD) Dimensions in millimeters NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown 0.30 4.00 ±0.10 0.50 0.08 REF 20 20 1 2 0.95 A 1 2 4.00 ±0.10 2.60 4.10 DETAIL A 21X 2.60 D C 0.75 ±0.05 0.08 C 4.10 SEATING PLANE C PCB Layout Reference View 0.22 ±0.05 0.50 BSC 0.20 0.40 ±0.10 B 0.05 REF Detail A 2.45 ±0.10 20 2.45 ±0.10 0.203 REF 0.05 REF 2 1 0.25 0.40 ±0.10 0.08 REF 0.10 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Figure 19: Package ES, 20-pin wettable flank QFN with exposed thermal pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 41 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ARG81800 Revision History Number Date – June 11, 2019 Description Initial release Copyright 2019, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 42