ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC
With I2C Digital Output and Low-Resistance Current Conductor
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: December 5, 2016
Recommended Substitutions: no direct replacement
For existing customer transition, and for new customers or new applications, contact Allegro Marketing.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC
With I2C Digital Output and Low-Resistance Current Conductor
Description
Features and Benefits
The Allegro™ ACS764 fully integrated Hall-effect current
sensor IC is designed for applications that require digital
current sensing and reporting through an I2C™ bus. Allegro
factory programming of the offset and gain, including the
temperature coefficients, stabilizes the offset and gain over
the operating temperature range. This programming greatly
reduces the device total error, typically less than 2% over the
operating temperature range. A fast response digital fault output
is also provided. Both coarse sensitivity and fault level can be
programmed via an I2C control register, and can be used for
enhanced diagnostic functions.
• Fully integrated current sensor IC in a compact QSOP
package eliminates the need for shunt resistors
• Hall effect sensing technology eliminates the error
associated with shunt resistor variation due to temperature
• High accuracy: typical error < 2% over operating
temperature range
• Fast response digital fault output with programmable level
through I2C bus interface
• Digital output through I2C interface with 9-bit A-to-D
conversion for high resolution current measurement
• User-selectable decimation averaging of current output; up
to 256 samples
• Freeze pin for holding current measurement value while
reading many sensors serially
• User-selectable (via I2C) coarse sensitivity and
OC fault levels, for exceptional flexibility to meet
application requirements
The integrated low resistance conductor eliminates the
requirement for external shunt resistors and, by employing
Hall-effect sensing technology, eliminates the error associated
with changing sense resistance due to temperature. The device
allows 16 unique I2C bus addresses, selectable via external pins.
The sensor IC gain can be selected by the user through the I2C
bus. The device uses a BiCMOS process that allows a highly
stable chopper-stabilized small signal amplifier design.
Continued on the next page…
Package: 24-pin QSOP (suffix LF)
The ACS764 is provided in a compact 24-pin QSOP package
(suffix LF). The leadframe is plated with 100% matte tin, which
is compatible with standard lead (Pb) free printed circuit board
assembly processes. Internally, the device is Pb-free, except
for flip-chip high-temperature Pb-based solder balls, currently
exempt from RoHS.
Not to scale
Typical Application Diagrams
IP
1
2
3
4
5
6
+3.3 V
CBYP
0.1 μF
7
8
9
10
11
12
ACS764-DS
IP+
IP–
IP+
IP–
IP+
IP+
IP+
IP–
ACS764
(I2C
Slave)
IP–
IP–
IP+
IP–
IP+
IP–
VCC
A1
SDA
A0
SCL
FAULT
GND
FREEZE
NC
NC
24
23
22
21
VCC
20
VA1
19
VCC
18
17
16
15
14
13
VCC
RPU
VA0
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Features and Benefits (continued)
• Less than 0.5 mΩ series resistance greatly reduces power
dissipation and heat generation
• Factory programmed temperature compensation stabilizes
sensitivity and offset voltage throughout the operating
temperature range
• 16 programmable I2C addresses
• Unidirectional DC current sensing and reporting
• Immunity to stray magnetic fields simplifies PCB layout
Selection Guide
Part Number
Packing*
ACS764XLFTR-32AU-T
Tape and reel, 2500 pieces/reel
ACS764XLFTR-16AU-T
Tape and reel, 2500 pieces/reel
*Contact Allegro™ for additional packing options.
Operating Ambient
Temperature,TA
(°C)
Optimized
Current Sensing
Range
(A)
Optimized
Nominal Resolution
(mA/LSB)
–20 to 125
–20 to 125
32
16
62.62
31.31
Absolute Maximum Ratings
Characteristic
Forward Supply Voltage
Symbol
Notes
Rating
Unit
VCC
7
V
¯¯A¯¯U¯¯
¯¯T
¯ Pin Voltage
Forward ¯F
L
VFAULT
24
V
DC Forward Voltage (A0, A1, FREEZE
pins)
VFDCx
7
V
DC Reverse Voltage (VCC, A0, A1,
¯F
¯¯A¯¯U¯¯
¯¯T
¯, FREEZE pins)
L
VRDCx
–0.5
V
–20 to 125
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 165
ºC
Storage Temperature
X temperature range
Thermal Characteristics
Characteristic
Steady State Package Thermal Resistance
Symbol
RθJA
Test Conditions
Value
Unit
Tested with 30 A DC current and based on ACS764
demo board in 1 cu. ft. of still air. Please refer to product
FAQs page on Allegro website for detailed information on
ACS764 demo board.
27
ºC/W
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
Functional Block Diagram
VCC
To all subcircuits
Master Current
Supply
POR and
Reset
Hall Drive
Fault Logic
Dynamic Offset
Cancellation
IP+
CBYPASS
Tuned
Filter
Sensitivity
Control
IP–
FAULT
ADC
Offset
Control
Data
Averaging
FREEZE
I2C
Interface
SDA
SCL
EEPROM
Digital
Controller
Temperature
Sensor
A0
A1
GND
Terminal List Table
Pin-out Diagram
IP+ 1
24 IP–
IP+ 2
23 IP–
IP+ 3
22 IP–
IP+ 4
21 IP–
IP+ 5
20 IP–
IP+ 6
19 IP–
IP+ 7
18 IP–
VCC 8
17 A1
SDA 9
16 A0
SCL 10
15 FAULT
GND 11
NC 12
14 FREEZE
13 NC
Number
Name
1 to 7
IP+
Primary current path input terminals
Function
8
VCC
Device power supply
9
SDA
I2C control: interface data signal input/output
10
SCL
I2C control: clock signal input/output
11
GND
Device ground
12,13
NC
14
FREEZE
No internal connection; connect to GND for optimal ESD performance
Digital output register freezing control input; pull-up to stop Data
register updating
15
¯F
¯¯A¯¯U¯¯L¯¯T¯
16
A0
I2C control: address input 0
17
A1
I2C control: address input 1
18 to 24
IP–
Primary current path output terminals
IP fault flag output; active low
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
OPERATING CHARACTERISTICS1 Valid throughout an ambient temperature range of –20°C to 125°C, CBYPASS = 0.1 μF,
VCC = 3.3 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
3.0
–
3.6
V
Electrical Characteristics
Supply Voltage
VCC
Supply Current
ICC
No load on SDA and SCL
–
9
14
mA
Power-On Time
tPO
TA = 25°C; CBYPASS = open
–
64
–
μs
Internal Bandwidth
BWi
Small signal –3 dB; TA = 25°C
–
2
–
kHz
Leadframe Resistance
RP
IP+ to IP– through primary current path
–
0.5
–
mΩ
[GAIN_RANGE] = 10b
–
8
–
A
Current Sensing Range Selection
Current Sensing Range2,3
Nominal Resolution3
[GAIN_RANGE] = 11b
–
16
–
A
[GAIN_RANGE] = 00b
–
32
–
A
[GAIN_RANGE] = 01b
–
64
–
A
[GAIN_RANGE] = 10b
–
15.66
–
mA/LSB
[GAIN_RANGE] = 11b
–
31.31
–
mA/LSB
[GAIN_RANGE] = 00b
–
62.62
–
mA/LSB
[GAIN_RANGE] = 01b
–
125.24
–
mA/LSB
ResADC
–
9
–
bit
tADC
–
375 × N
–
μs
1
–
256
data point
CSR
RES
Output Signal Characteristics
A-to-D Conversion Resolution
A-to-D Conversion Time
Average Quantity of Data Points
Included in Moving Average
Calculation4
N
[N7:N0]=[0000 0000] through [1111 1111]
represents 1 data point through 256 data points
Analog Noise
INOISE(rms)(A) TA = 25°C
–
15
–
mA
Analog Noise Density
INOISE(den)(A) TA = 25°C
–
0.27
–
mA/Hz1/2
15
–
496
ADC
Code
–
INOISE(rms)(A)
/ N1/2
–
mA
GAIN_RANGE set for optimized CSR, ADC
code is within ADCLIN; measured at 2 A;
TA = 25°C to 125°C
–8
±5
+8
LSB
GAIN_RANGE set for optimized CSR; ADC
code is within ADCLIN; measured at 2 A;
TA = –20°C to 25°C
–15
±7
+15
LSB
A-to-D Linear Range5
Digital Noise
ADCLIN
INOISE(rms)(D) TA = 25°C
Accuracy Performance
Offset Error
ErrOS
Continued on the next page…
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
OPERATING CHARACTERISTICS1 (continued) Valid throughout an ambient temperature range of –20°C to 125°C,
CBYPASS = 0.1 μF, VCC = 3.3 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GAIN_RANGE set for optimized CSR,
ADC code is within ADCLIN ; TA = 25°C to 125°C;
measured at 0.94 × CSR
–2.5
±1
+2.5
%
GAIN_RANGE set for optimized CSR,
ADC code is within ADCLIN ; TA = –20°C to 25°C;
measured at 0.94 × CSR
–3.5
±1.5
+3.5
%
GAIN_RANGE set for optimized CSR,
ADC code is within ADCLIN
–
±0.75
–
%
GAIN_RANGE set for optimized CSR;
ADC code is within ADCLIN; Current =
0.94 × CSR; TA = 25°C to 125°C
–2.5
±1
+2.5
%
GAIN_RANGE set for optimized CSR;
ADC code is within ADCLIN; Current =
0.94 × CSR; TA = –20°C to 25°C
–3.5
±2
+3.5
%
Accuracy Performance (continued)
Resolution Accuracy
Nonlinearity Error
Total Error
ResACC
ErrLIN
ErrTOT
Lifetime Drift Characteristics
Resolution Lifetime Drift
ResDRIFT
–
±3.0
–
%
Total Error Lifetime Drift
ErrTOT_DRIFT
–
±3
–
%
–
A
Overcurrent Fault Detection Resolution/Timing
Fault Current Maximum Setpoint
IFAULT(MAX) FAULT_LEVEL = 0000b
–
1.46 × CSR
Fault Current Minimum Setpoint
IFAULT(MIN) FAULT_LEVEL = 1111b
–
0.5 × CSR
–
A
Digital Fault Level Resolution
ResFAULT
–
4
–
bit
EFAULT(MIN)
GAIN_RANGE set for optimized CSR;
measured at FAULT_LEVEL = 0000b
–4
±2.5
+4
%
EFAULT(MAX)
GAIN_RANGE set for optimized CSR;
measured at FAULT_LEVEL = 1111b
–
±7
–
%
10
–
–
kΩ
Fault Level Error6
¯¯T¯ Pin
Pull up Resistance at ¯F¯¯A¯¯U¯¯L
¯F
¯¯A¯¯U¯¯
¯¯T
¯ Output Voltage
L
RPU
VFAULT
RPU = 10 kΩ, under fault condition
–
–
0.4
V
tFAULT
Delay from IP rising above IFAULT until
VFAULT < 0.4 V
–
100
–
μs
VFREEZE(IL)
–
–
0.2 × VCC
V
FREEZE Pin Input Level (High)
VFREEZE(IH)
0.8 × VCC
–
–
V
FREEZE Pin Input Impedance
RFREEZE(IN)
–
10
–
kΩ
Fault Response Time
FREEZE Pin Characteristics
FREEZE Pin Input Level (Low)
Continued on the next page…
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
OPERATING CHARACTERISTICS1 (continued) Valid throughout an ambient temperature range of –20°C to 125°C,
CBYPASS = 0.1 μF, VCC = 3.3 V, unless otherwise noted
Characteristics
Address Pin
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Characteristics7
Address Value 0 Voltage
VADDR0
A0, A1 pins
–
0
0.08 ×
VCC
V
Address Value 1 Voltage
VADDR1
A0, A1 pins
0.28 ×
VCC
0.31 ×
VCC
0.34 ×
VCC
V
Address Value 2 Voltage
VADDR2
A0, A1 pins
0.53 ×
VCC
0.56 ×
VCC
0.59 ×
VCC
V
Address Value 3 Voltage
VADDR3
A0, A1 pins
0.8 ×
VCC
VCC
–
V
Input Bias Current
IA0
A0 pin
–
100
–
nA
IA1
A1 pin
–
100
–
nA
1All
current measurement accuracy specifications listed in this datasheet apply only for the optimized current sensing range.
will be most accurate in its optimized gain range.
3The GAIN_RANGE setting of 11b selects the Optimized Nominal Resolution for the 16AU variant, and the GAIN_RANGE setting of 00b selects the
Optimized Nominal Resolution for the 32AU variant.
4Programmable by user through the I2C interface.
5The ADC is most linear within ADC
LIN, so code readings outside ADCLIN should not be used for precise measurement.
6Percentage of CSR. See table 3 and Definitions of Accuracy Characteristics section.
7Address pin characteristics are ensured by designed but are not factory tested.
2The ACS764
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
6
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
I2C INTERFACE CHARACTERISTICS* Valid at an ambient temperature range of –20°C to 125°C and VCC = 3.3 V; unless otherwise noted
Characteristics
Symbol
Min.
Typ.
Max.
Unit
tBUF
1.3
–
–
μs
Hold Time Start Condition
thdSTA
0.6
–
–
μs
Setup Time for Repeated Start Condition
tsuSTA
0.6
–
–
μs
SCL Low Time
tLOW
1.3
–
–
μs
SCL High Time
tHIGH
0.6
–
–
μs
ns
Bus Free Time Between Stop and Start
Test Conditions
Data Setup Time
tsuDAT
100
–
–
Data Hold Time
thdDAT
0
–
900
ns
Setup Time for Stop Condition
tsuSTO
0.6
–
–
μs
Logic Input Low Level (SDA, SCL pins)
VIL
−
−
0.3×VCC
V
Logic Input High Level (SDA, SCL pins)
VIH
0.7×VCC
−
−
V
Logic Input Current
IIN
Output Voltage (SDA pin)
VOL
VIN = 0 V to VCC
−1
−
1
μA
RPU = 1 kΩ, CB = 100 pF
−
−
0.2 ×VCC
V
Logic Input Rise Time (SDA, SCL pins)
tr
−
−
300
ns
Logic Input Fall time (SDA, SCL pins)
tf
−
−
300
ns
SDA Output Rise Time
tr
RPU = 1 kΩ, CB = 100 pF
−
−
300
ns
SDA Output Fall Time
tf
RPU = 1 kΩ, CB = 100 pF
−
−
300
ns
Clock Frequency (SCL pin)
fCLK
−
−
400
kHz
SDA and SCL Bus Pull-up Resistor
RPU
−
1
−
kΩ
Total Capacitive Load for Each of SDA
and SCL Buses
CB
−
−
100
pF
*I2C interface characteristics are ensured by designed but are not factory tested.
I2C Interface Timing Diagram
tsuSTA thdSTA
tsuDAT
thdDAT
tsuSTO
tBUF
SDA
tr
tf
SCL
tLOW
tHIGH
tr
tf
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115 Northeast Cutoff
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7
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Application Information
The ACS764 is a fully integrated Hall-effect based current sensor
IC with a digital current output and an overcurrent fault output
for current monitoring and reporting applications. The digital output can be read from the ACS764 by a master controller through
the I2C interface. The I2C interface can also be used to control
some features of the ACS764. Sixteen device addresses are available through two input pins (A0, A1), allowing multiple devices
to be connected to the same I2C bus in the application.
The output data that can be read from the ACS764 through the
I2C interface includes the following:
• Current amplitude (9 bits)
• Unlatched overcurrent fault flag (1 bit)
• Latched overcurrent fault flag (1 bit)
• Unread new current data flag (1 bit)
The control data that can be written to the ACS764 through I2C
interface includes the following:
• Current range selection (2 bits)
• Overcurrent fault level selection (4 bits)
• Digital averaging filter data point selection (8 bits)
• Latched overcurrent fault flag reset (1 bit)
I2 C
Interface
I2C is a serial interface that uses two bus lines, SCL and SDA, to
access the internal device registers. Data is exchanged between
a master controller (for example, a microcontroller) and the
ACS764 (slave). The clock input to SCL is generated by the
master, while the SDA line functions as either an input or an open
drain output, depending on the direction of the data transfer. The
I2C input thresholds depend on the VCC voltage of the ACS764.
Timing Considerations
I2C communication is composed of several steps in the following
sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
while SCL is high.
2. Address Cycle. 7 device (slave) address bits, plus 1 bit
to indicate write (0) or read (1), followed by an acknowledge bit.
3. Data Cycles. Reading or writing 8 data bits, followed by an
acknowledge bit. This cycle can be repeated for multiple
bytes of data transfer. If there are multiple registers in a
device (for example, EEPROM), the first data byte could be
the register address. See the following sections for further
information.
4. Stop Condition. Defined by a positive edge on the SDA line,
while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable
while the clock is high. SDA can only be changed while SCL is
low.
It is possible for the Start or Stop condition to occur at any time
during a data transfer. The ACS764 always responds by resetting
the data transfer sequence.
The state of the Read/Write bit is set low to indicate a write cycle
and set high to indicate a read cycle.
The master monitors for an acknowledge pulse to determine if
the slave device is responding to the address byte sent to the
ACS764. When the ACS764 decodes the 7-bit address field as a
valid address, it responds by pulling SDA low during the ninth
clock cycle.
During a data write from the master, the ACS764 pulls SDA low
during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received.
After sending either an address byte or a data byte, the master
device must release the SDA line before the ninth clock cycle, in
order to allow the handshaking to occur.
Writing to ACS764 Registers Through the I2C
Interface Bus
The master controls the ACS764 by programming it as a slave.
To do so, the master transmits data bits to the SDA input of the
ACS764 in synchronization with the clocking signal it transmits
simultaneously on the SCL input.
A complete transmission begins with the master pulling SDA low
(Start bit), and completes with the master releasing the SDA line
(Stop bit). Between these points, the master transmits a pattern
of slave device (ACS764) address bits with a write command
(D0 = 0), and then the target register address (within that device),
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8
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
a low to the master on the SDA line. After writing data to a register the master must provide a Stop bit if writing is completed.
If the stop bit is not set, then the next three bytes will be written
to the current register address + 1. Writing will continue in this
fashion until the Stop bit is received. If the total data byte count
(that is, not including the Register Address byte) is not modulo
three, then the write operation that would contain less than three
bytes is not done.
and finally the data for the register. Each register in the ACS764
device is three bytes, or 24 bits, long. The address consists of
two bytes, comprising: the ACS764 (device) address (7 bits) and
the read/write bit, followed by the address byte of the individual
register. The data stream of writing data to an individual register
is shown in figure 1.
After each byte, the slave ACS764 acknowledges by transmitting
ACS764 (Slave) Acknowledge
Operation Bit (Write)
ACS764 Bus Address
Master
Start
ACS764 (Slave) Acknowledge
Register Address
SDA
A6 A5 A4 A3 A2 A1 A0 RW AK R7 R6 R5 R4 R3 R2 R1 R0 AK
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
ACS764 (Slave) Acknowledge
7
8
ACS764 (Slave) Acknowledge
Data Byte 2
...
...
SDA
SCL
9
...
...
ACS764 (Slave) Acknowledge
Data Byte 1
Master
Stop
Data Byte 0
D23 D22 D21 D20 D19 D18 D17 D16 AK D15 D14 D13 D12 D11 D10 D9 D8 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
MSB Byte
8
9 1
2
3
4
5
6
7
8
9
LSB Byte
Figure 1. I2C interface typical data write to an individual register in the ACS764
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9
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
data from an individual register is shown in figure 2.
Reading from ACS764 Registers Through the I2C
Interface Bus
After each byte of data received, the master acknowledges by
transmitting a low to the slave on the SDA line. After receiving three bytes of data from a register, the master must provide
a Stop bit if reading is completed. If the Stop bit is not set,
then the next three bytes will be read from the initial register
address + 1. Reading will continue in this fashion until the Stop
bit is received. Please note that the acknowledge bit immediately
before the Stop bit should be a non-acknowledge (AK = 1).
When the master controller performs a data read from an ACS764
internal register, a so-called combined data transmission format
is used. The I2C master provides the Start bit, the ACS764 device
(slave) address, the read/write bit set to write (0), and then the initial source register address. The master then issues another Start
bit (referred to as restart) followed by the same slave address and
the read/write bit set to read (1). The ACS764 then provides three
bytes of read data, one byte at a time. The data stream of reading
Master Restart
ACS764 (Slave) Acknowledge
ACS764 (Slave) Acknowledge
Operation Bit (Write)
ACS764 Bus Address
Master
Start
ACS764 (Slave) Acknowledge
Operation Bit (Read)
ACS764 Bus Address
Register Address
SDA
A6 A5 A4 A3 A2 A1 A0 RW AK R7 R6 R5 R4 R3 R2 R1 R0 AK
A6 A5 A4 A3 A2 A1 A0 RW AK
SCL
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
Master Acknowledge
SDA
SCL
2
3
4
5
Master Acknowledge
Data Byte 2
...
...
9
6
7
8
9
...
...
Master Non-Acknowledge
Data Byte 1
Master
Stop
Data Byte 0
D23 D22 D21 D20 D19 D18 D17 D16 AK D15 D14 D13 D12 D11 D10 D9 D8 AK D7 D6 D5 D4 D3 D2 D1 D0 NAK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
MSB Byte
8
9 1
2
3
4
5
6
7
8
9
LSB Byte
Figure 2. I2C interface typical data read from an individual register in the ACS764
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115 Northeast Cutoff
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10
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
I2C Device (Slave) Address Coding
The four LSBs of the device (slave) address (A3, A2, A1, and A0)
can be set by applying different voltages to pins A0 and A1 as
show in figure 3 and defined in table 1.
Note: Different values for the three MSBs of the address (A6, A5,
and A4) are available for factory programming if a conflict with
other units occurs in the application design.
ACS764 Bus Address Byte Definitions
Address Bit
A6
A5
1
1
A4
A3
A2
A1
A0
0/1
0/1
Binary Device Address Value
0
0/1
0/1
Table 1. I2C Device Address Coding (Refer to figure 3)
Device Address #
Voltage on A1 Pin, VA1
Voltage on A0 Pin, VA0
Decimal
Binary
(A3, A2, A1,A0)
0V
0V
0
0000
0V
0.31 × VCC
1
0001
0V
0.56 × VCC
2
0010
0V
VCC
3
0011
0.31 × VCC
0V
4
0100
0.31 × VCC
0.31 × VCC
5
0101
0.31 × VCC
0.56 × VCC
6
0110
0.31 × VCC
VCC
7
0111
0.56 × VCC
0V
8
1000
0.56 × VCC
0.31 × VCC
9
1001
0.56 × VCC
0.56 × VCC
10
1010
0.56 × VCC
VCC
11
1011
VCC
0V
12
1100
VCC
0.31 × VCC
13
1101
VCC
0.56 × VCC
14
1110
VCC
VCC
15
1111
VCC
VCC
VA0, VA1
ACS764
A0, A1
43 kΩ
Figure 3. External equivalent circuit for
I2C device address selection
0.56 × VCC
24 kΩ
I2C
Interface
0.31 × VCC
30 kΩ
0V
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11
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Table 2. User-Accessible Volatile Memory Registers
Data Register
I2C Register
Address
Bits
Parameter Name
0x00
23:12
Reserved
0x00
11
NON-LATCHED_FAULT_STATUS
0x00
10
LATCHED_FAULT_STATUS
0x00
9
SYNC
0x00
8:0
CURRENT
Description
Read as all 0s
Non-Latched Fault bit (Read only)
Latched Fault bit; resets with 1 written to this bit (Read/Write)
Sync (new data) bit; resets when this register is read (Read only)
Current Sensor output value (digital filter output) (Read only)
Control Registers
I2C Register
Address
Bits
Parameter Name
0x02
7:0
AVG_POINTS
Number of averaging points (Read/Write)
0x04
1:0
GAIN_RANGE
Current sensing range selection (Read/Write)
0x06
3:0
FAULT_LEVEL
Fault threshold selection (Read/Write)
Description
Default
0
0 (32AU version)
3 (16AU version)
0
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12
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
User-Accessible Register Bit Descriptions
Volatile Register Bits (Address: 0x00)
X
X
X
X
X
X
X
X
X
X
X
X 0/1 0/1 0/1 D8 D7 D6 D5 D4 D3 D2 D1 D0
Reserved
CURRENT
NON-LATCHED_FAULT_STATUS
LATCHED_FAULT_STATUS
SYNC
Volatile Register Bits (Address: 0x02)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X N7 N6 N5 N4 N3 N2 N1 N0
Reserved
AVG_POINTS
Volatile Register Bits (Address: 0x04)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X G1 G0
Reserved
GAIN_RANGE
Volatile Register Bits (Address: 0x06)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X F3 F2 F1 F0
Reserved
FAULT_LEVEL
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13
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Working with Internal Device Registers Through I2C
Control Registers
On power-up the control registers will be loaded to their default
values from the EEPROM. The settings can be changed after
powering on the device by overwriting the control registers
through the I2C interface. However, the control registers will
revert to their previous levels if the sensor IC is power cycled.
Contact your local sales representative if you need the default
control register values to be factory-programmed differently.
Data Registers
The volatile register at 0x00 holds all the output data of the
device. It includes nine bits of current measurement data and
three flag bits: one bit for current output update (SYNC), one bit
for latched overcurrent fault (LATCHED_FAULT_STATUS),
and one bit for non-latched overcurrent fault (NON-LATCHED_
FAULT_STATUS), in that order.
After the current measurement data has been updated, SYNC is
set. It will be reset when the data is read by a master controller
through the I2C interface.
When an overcurrent fault condition is detected, both the
LATCHED_FAULT_STATUS and the NON-LATCHED_
FAULT_STATUS bits will be set. The NON-LATCHED_
FAULT_STATUS bit will be reset after the overcurrent condition
is removed. However, the LATCHED_FAULT_STATUS bit will
remain set until a 24-bit word in the format:
XXXX XXXX XXXX X1XX XXXX XXXX
is written to the register.
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14
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Setting the Overcurrent Fault Threshold
The Overcurrent Fault threshold, IFAULT , is determined by setting
the four FAULT_LEVEL bits. The combined settings determine
the threshold as a percentage of current sensing range, CSR. The
¯F¯A
¯¯U¯¯L¯¯T¯ pin will be pulled low when the current is above the
¯ pin will be released
programmed I_FAULT level. The ¯F¯A¯¯U¯¯L¯¯T
when the current drops below the programmed I_FAULT level.
The digital NON-LATCHED FAULT STATUS bit will be 1 when
the current is above I_FAULT and 0 when the current is below
I_FAULT. The LATCHED FAULT STATUS bit will be 1 when
the current is above I_FAULT and will only return to being 0
when the current is below I_FAULT and the bit is reset by writing
a 1 to it.
Table 3. I2C Control: Settings for Overcurrrent Fault Threshold
FAULT_LEVEL Bits
IFAULT
F3
F2
F1
F0
Level
Setting
( %CSR )
0
0
0
0
0
50
0
0
0
1
1
56
0
0
1
0
2
63
0
0
1
1
3
69
0
1
0
0
4
76
0
1
0
1
5
82
0
1
1
0
6
88
0
1
1
1
7
95
1
0
0
0
8
101
1
0
0
1
9
108
1
0
1
0
10
114
1
0
1
1
11
120
1
1
0
0
12
127
1
1
0
1
13
133
1
1
1
0
14
140
1
1
1
1
15
146
Example: If the required overcurrent fault threshold is 88% of the CSR ,
then the required FAULT_LEVEL values are: 0110 (Level 6).
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15
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
Characteristic Performance Data
Data taken using the ACS764-32AU
Accuracy Data
Offset Error versus Ambient Temperature
Resolution versus Ambient Temperature
20.00
15.00
Sens (mV/A)
ErrOS (LSB)
10.00
5.00
0
-5.00
-10.00
-15.00
-20.00
-40
-20
0
20
40
60
80
100
120
65.50
65.00
64.50
64.00
63.50
63.00
62.50
62.00
61.50
61.00
60.50
60.00
140
-40
-20
0
20
40
TA (°C)
100
120
140
Fault Minimum Error versus Ambient Temperature
4.00
5.00
3.00
4.00
3.00
EFAULT(MIN) (%)
2.00
ErrTOT (%)
80
TA (°C)
Total Error versus Ambient Temperature
1.00
0
-1.00
-2.00
2.00
1.00
0
-1.00
-2.00
-3.00
-3.00
-4.00
-4.00
-40
-20
0
20
40
60
80
100
120
-5.00
-40
140
-20
0
20
40
Fault Maximum Error versus Ambient Temperature
8.00
80
100
120
140
Total Error versus Current
TA = 25°C
8.00
6.00
6.00
4.00
ErrTOT (%)
2.00
0
-2.00
-4.00
-6.00
4.00
2.00
0
-2.00
-8.00
-4.00
-10.00
-12.00
-40
60
TA (°C)
TA (°C)
EFAULT(MAX) (%)
60
-6.00
-20
0
20
40
60
80
100
120
140
0
2
4
6
8
10
TA (°C)
12
14
16
18
20
22
24
26
28
30
32
Current (A)
+3 sigma
Maximum Limit
Mean
-3 sigma
Minimum Limit
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16
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
Characteristic Performance Data
Data taken using the ACS764-16AU
Accuracy Data
Offset Error versus Ambient Temperature
Resolution versus Ambient Temperature
20.00
33.00
15.00
32.50
Sens (mV/A)
ErrOS (LSB)
10.00
5.00
0
-5.00
32.00
31.50
31.00
-10.00
30.50
-15.00
-20.00
-40
30.00
-20
0
20
40
60
80
100
120
140
-20
0
20
40
80
100
120
140
Total Error versus Ambient Temperature
Fault Minimum Error versus Ambient Temperature
4.00
5.00
3.00
4.00
3.00
EFAULT(MIN) (%)
1.00
0
-1.00
-2.00
2.00
1.00
0
-1.00
-2.00
-3.00
-3.00
-4.00
-4.00
-40
-20
0
20
40
60
80
100
120
-5.00
-40
140
-20
0
20
40
TA (°C)
6.00
8.00
5.00
6.00
4.00
4.00
3.00
ErrTOT (%)
10.00
2.00
0
-2.00
80
100
120
140
14
16
Total Error versus Current
TA = 25°C
2.00
1.00
0
-4.00
-1.00
-6.00
-2.00
-8.00
-3.00
-10.00
-40
60
TA (°C)
Fault Maximum Error versus Ambient Temperature
EFAULT(MAX) (%)
60
TA (°C)
2.00
ErrTOT (%)
-40
TA (°C)
-4.00
-20
0
20
40
60
80
100
120
0
140
2
4
TA (°C)
6
8
10
12
Current (A)
+3 sigma
Maximum Limit
Mean
-3 sigma
Minimum Limit
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17
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
Definitions of Accuracy Characteristics
A-to-D Linear Range (ADCLIN)
The range of the ADC over which the ADC code is proportional
to the current being sensed. One should consider the ADC saturated outside this range. See figure 4.
Offset Error (ErrOS)
The offset of the ADC code versus the measured current from the
ideal of zero. See figure 4. This parameter is measured at 2 A,
as the ADC is below ADCLIN at zero current. The offset error is
calculated as:
1
ErrOS = ADCCODE at 2 A – 2000 (mA) ×
RES
Resolution Accuracy (ResACC)
The resolution of the sensor is given in mA/LSB, which is the
inverse of the slope of the ADC code versus the measured current
(see figure 4). Multiplying the ADC code by the resolution yields
the measured current. The Resolution Accuracy (ResACC) is how
511
Ignore (consider saturated)
ADC Code (LSB)
ADCLIN(max)
{
Ideal ADC Behavior
Offset Error
0
Nonlinearity Error (ErrLIN)
The Nonlinearity Error is a measure of how linear the ADC code
versus measured current curve is. The nonlinearity is calculated as:
0.5 ADCCODE (0.94 × CSR) – ErrOS
ErrLIN = 1–
× 100 (%)
0.94 ADCCODE (0.5 × CSR) – ErrOS
Total Error (ErrTOT)
The percentage difference between the current measurement from
the sensor IC and the actual current being measured (IP), relative
to the actual current. This is equivalent to the percentage difference between the ideal ADC code and the actual ADC code,
relative to the ideal ADC code:
ADCIDEAL(IP) – ADC(IP)
× 100 (%)
ADCIDEAL(IP)
2
CSR
Measured Current (IP) (A)
Fault Level Error (EFAULT(MIN), EFAULT(MAX))
The Fault Level Error is a measure of the accuracy of the
overcurrent fault function. EFAULT(MIN) is EFAULT measured at
FAULT_LEVEL = 0000b, and EFAULT(MAX) is EFAULT measured
at FAULT_LEVEL = 1111b. The Fault Level Error is calculated as:
EFAULT(FAULT_LEVEL) =
Ignore (consider saturated)
Figure 4. A-to-D Linear Range
Measured Resolution – RES
× 100 (%)
RES
The Total Error incorporates all sources of error and is a function
of the measured current ( IP ). At relatively high currents, ErrTOT
will be mostly due to the Resolution Accuracy, and at relatively
low currents, ErrTOT will be mostly due to the Offset Error.
Actual ADC Behavior
{
ResACC =
ErrTOT(IP) =
1/Resolu on
ADCLIN(min)
close the actual resolution is to the Nominal Resolution (RES).
The Resolution Accuracy is calculated as:
Fault Trip Current
– IFAULT_Percent
CSR × 100 (%)
where IFAULT_Percent is the ideal percentage of CSR at which the
overcurrent fault should trip, based on the FAULT_LEVEL settings as given in table 3. For example, if FAULT_LEVEL is set
to 0000b, the ideal trip point is at 50% of CSR. An EFAULT(MIN)
specification of ±4% means the actual trip point ia between 46%
and 54% of CSR.
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18
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Dynamic Response Characteristics
Power-On Time (tPO):
When the supply is ramped to its operating voltage, the device
requires a finite time to power its internal components before
responding to a magnetic field due to current flow through the
sensor. Power-On Time, tPO , is defined as the time it takes from
when the supply voltage (VCC) reaches its minimum specified
voltage to when the value from the ADC is valid, as well as the
fault bits and fault output.
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19
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative to
the offset that can be produced at the output of the Hall sensor IC.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges. Chopper stabilization is a unique approach
used to minimize Hall offset on the chip. Allegro employs a patented technique to remove key sources of the output drift induced
by thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent
demodulation acts as a modulation process for the offset, causing
the magnetic field-induced signal to recover its original spectrum
at baseband, while the DC offset becomes a high-frequency signal.
The magnetic-sourced signal then can pass through a low-pass
filter, while the modulated DC offset is suppressed. In addition
to the removal of the thermal and stress related offset, this novel
technique also reduces the amount of thermal noise in the Hall sensor IC while completely removing the modulated residue resulting
from the chopper operation. The chopper stabilization technique
uses a high-frequency sampling clock. For demodulation process, a
sample-and-hold technique is used. This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
and faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall output
voltages and precise recoverability after temperature cycling. This
technique is made possible through the use of a BiCMOS process,
which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold
circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anti-Aliasing
LP Filter
Tuned
Filter
Concept of Chopper Stabilization Technique
Allegro MicroSystems, LLC
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
20
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
ACS764
Package LF, 24-Pin QSOP
8º
0º
8.66 ±0.10
24
0.25
0.15
3.91 ±0.10
2.30
5.00
5.99 ±0.20
A
1.27
0.41
1
1.04 REF
2
0.25 BSC
Branded Face
24X
1.75 MAX
0.20 C
0.30
0.20
0.635 BSC
SEATING
PLANE
C
0.40
0.635
B
SEATING PLANE
GAUGE PLANE
0.25 MAX
PCB Layout Reference View
NNNNNNNNNNNNN
TLF-AAA
For Reference Only, not for tooling use (reference JEDEC MO-137 AE)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
LLLLLLLLLLL
A Terminal #1 mark area
B Reference pad layout (reference IPC7351 SOP63P600X175-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
C
Standard Branding Reference View
N = Device part number
T = Temperature code
LF = (Literal) Package type
A = Amperage
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
21
ACS764
Fully Integrated, Hall-Effect Based Current Sensor IC with I2C
Digital Output and Low-Resistance Current Conductor
Copyright ©2010-2013, Allegro MicroSystems, LLC
I2C™ is a trademark of Philips Semiconductors.
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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