UCN5833EP

5833 UCN5833EP SERIAL DATA OUT POWER GROUND OUTPUT ENABLE SERIAL DATA IN BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER Designed to reduce logic supply current, chip size, and system cost, the UCN5833A/EP integrated circuits offer high-speed operation for thermal printers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak output current rating. The combination of bipolar and MOS technologies gives BiMOS II smart power ICs an interface flexibility beyond the reach of standard buffers and power driver circuits. 39 38 37 36 Data Sheet 26185.16A* STROBE LOGIC SUPPLY CLOCK OUT32 41 OUT1 NC CLK 44 43 OE 42 VDD 1 ST 4 40 5 6 3 2 NC OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT10 OUT11 OUT 12 7 8 9 10 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 11 12 13 14 15 16 17 35 34 33 32 31 30 29 These 32-bit drivers have bipolar open-collector npn Darlington outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS shift register, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems at data input rates above 3.3 MHz. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high. The UCN5833A is supplied in a 40-pin dual in-line plastic package with 0.600" (15.24 mm) row spacing. At an ambient temperature of +75°C, all outputs of the DlP-packaged device will sustain 50 mA continuously. For high-density applications, the UCN5833EP is available. This 44-lead plastic chip carrier (quad pack) is intended for surface-mounting on solder lands with 0.050" (1.27 mm) centers. CMOS serial data outputs permit cascading for applications requiring additional drive lines. REGISTER REGISTER LATCHES SUB OUT13 19 OUT14 20 OUT15 21 OUT16 22 LOGIC GROUND 23 OUT17 24 OUT18 25 OUT19 26 OUT20 27 LATCHES NC 28 NC 18 Dwg. No. A-13,049 FEATURES ABSOLUTE MAXIMUM RATINGS at +25°C Free-Air Temperature Output Voltage, VOUT . . . . . . . . . . . 30 V Logic Supply Voltage, VDD . . . . . . . 7.0 V Input Voltage Range, VIN . . . . . . . . . - 0.3 V to VDD + 0.3 V Continuous Output Current, lOUT (each output) . . . . . . . . . . 125 mA Package Power Dissipation, PD (UCN5833A) . . . . . . . . . . . . . . . 3.5 W* (UCN5833EP) . . . . . . . . . . . . . . 2.5 W* Operating Temperature Range, TA . . . . . . . . . . . . . . - 20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . -55°C to +150°C * Derate linearly to 0 W at +150°C. I To 3.3 MHz Data Input Rate I 30 V Minimum Output Breakdown I Darlington Current-Sink Outputs I Low-Power CMOS Logic and Latches Always order by complete part number: Part Number UCN5833A UCN5833EP Package 40-Pin DIP 44-Lead PLCC Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER UCN5833A FUNCTIONAL BLOCK DIAGRAM LOGIC SUPPLY SERIAL DATA IN POWER GROUND STROBE OUT 1 OUT OUT OUT 2 3 1 2 3 4 5 6 7 8 ST V DD CLK CLOCK 40 LOGIC SUPPLY 39 SERIAL DATA OUT OUTPUT ENABLE OUT 32 V DD CLOCK 32-BIT SHIFT REGISTER SERIAL DATA IN LATCHES STROBE LOGIC GROUND SUB SERIAL DATA OUT OE 38 37 36 35 34 33 OUT 31 OUT 30 OUT 29 OUT 28 OUT 27 OUTPUT ENABLE 4 5 6 7 MOS BIPOLAR REGISTER REGISTER OUT OUT 10 11 12 12 LATCHES LATCHES OUT 9 32 31 OUT 26 30 29 28 27 26 25 24 OUT 25 OUT 24 OUT 23 OUT1 OUT2 OUT3 POWER OUT30 OUT31 OUT32 GROUND OUT 8 OUT 9 OUT Dwg. No. A-13,057 10 14 OUT 22 OUT 21 OUT 20 OUT 19 OUT 11 15 OUT 12 16 TYPICAL INPUT CIRCUIT VDD OUT 13 17 OUT 14 18 23 OUT 18 22 SUB OUT 15 19 OUT 16 20 OUT 17 IN 21 LOGIC GROUND Dwg. No. A-13,048 Dwg. No. A-13,050 SUB TYPICAL OUTPUT DRIVER OUT Dwg. No. A-13,051 115 Northeast Cutoff, Box 15036 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1986, 1995, Allegro MicroSystems, Inc. 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted). Characteristic Output Leakage Current Collector-Emitter Saturation Voltage Input Voltage Symbol ICEX VCE(SAT) VIN(1) VIN(0) Input Current lIN(1) lIN(0) Serial Output Voltage VOUT(1) VOUT(0) Supply Current lDD VIN = 5.0 V VIN = 0 V IOUT = -200 µA IOUT = 200 µA One output ON, lOUT = 100 mA All outputs OFF Output Rise Time Output Fall Time tr tf lOUT = 100 mA, 10% to 90% lOUT = 100 mA, 90% to 10% Test Conditions VOUT = 30 V, TA = 70°C lOUT = 50 mA lOUT = 100 mA Min. — — — 3.5 -0.3 — — 4.5 — — — — — Limits Max. 10 1.2 1.7 5.3 +0.8 1.0 -1.0 — 0.3 1.0 50 500 500 Units µA V V V V µA µA V V mA µA ns ns NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin. TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Input Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X H L P1 P2 P3 ... PN-1 PN H H H ... H H P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER CLOCK DATA IN E STROBE OUTPUT ENABLE G OUTN Dwg. No. A-12,276A A B D F C TIMING CONDITIONS (VDD = 5.0 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) .......................................................................... 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns C. Minimum Data Pulse Width ................................................................ 150 ns D. Minimum Clock Pulse Width ............................................................... 150 ns E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns F. Minimum Strobe Pulse Width ............................................................. 100 ns G. Typical Time Between Strobe Activation and Output Transition ........................................................................... 500 ns Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the OUTPUT ENABLE input high, the outputs are controlled by the state of the latches. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER UCN5833A Dimensions in Inches (controlling dimensions) 40 21 0.015 0.008 0.700 MAX 0.580 0.485 0.600 BSC 1 2 0.070 0.030 3 4 2.095 1.980 20 0.100 BSC 0.005 MIN 0.250 MAX 0.015 MIN 0.200 0.115 0.022 0.014 Dwg. MA-003-40 in Dimensions in Millimeters (for reference only) 40 21 0.381 0.204 17.78 14.73 12.32 MAX 15.24 BSC 1 2 1.77 0.77 3 4 53.2 50.3 2.54 BSC 20 0.13 MIN 6.35 MAX 0.39 MIN 5.08 2.93 0.558 0.356 Dwg. MA-003-40 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER UCN5833EP Dimensions in Inches (controlling dimensions) 28 18 29 0.319 0.291 0.021 0.013 0.695 0.685 0.656 0.650 0.319 0.291 0.050 BSC INDEX AREA 17 0.032 0.026 39 7 40 0.020 MIN 44 1 2 6 0.656 0.650 0.695 0.685 Dwg. MA-005-44A in 0.180 0.165 Dimensions in Millimeters (for reference only) 28 18 29 8.10 7.39 0.533 0.331 17.65 17.40 16.662 16.510 INDEX AREA 17 0.812 0.661 8.10 7.39 1.27 BSC 39 7 40 0.51 MIN 44 1 2 6 4.57 4.20 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 5833 BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER POWER INTERFACE DRIVERS Function 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit (constant-current LED driver) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) 10-Bit (active pull-downs) 12-Bit (active pull-downs) 16-Bit (constant-current LED driver) 20-Bit (active pull-downs) 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) 4-Bit 8-Bit 8-Bit 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) Unipolar Stepper Motor Translator/Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 28-Line Decoder/Driver * † ‡ Output Ratings* SERIAL-INPUT LATCHED DRIVERS -120 mA 350 mA 350 mA 350 mA 350 mA 75 mA 250 mA 350 mA 100 mA -25 mA -25 mA 75 mA -25 mA -25 mA 100 mA 100 mA 350 mA -25 mA 350 mA 100 mA 250 mA 1.25 A 250 mA 350 mA 100 mA 450 mA 50 V‡ 50 V 80 V 50 V‡ 80 V‡ 17 V 50 V 50 V‡ 50 V 60 V 60 V 17 V 60 V 60 V 30 V 40 V 50 V‡ 60 V 50 V‡ 50 V 50 V 50 V‡ 50 V 50 V‡ 50 V 30 V 5895 5821 5822 5841 5842 6275 6595 6A595 6B595 5810-F and 6809/10 5811 and 6811 6276 5812-F and 6812 5818-F and 6818 5833 5832 5800 5815 5801 6B273 6273 5804 6259 6A259 6B259 6817 Part Number† PARALLEL-INPUT LATCHED DRIVERS SPECIAL-PURPOSE DEVICES Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000