UCN5841LW

5841 AND 5842 UCN5841A & UCN5842A VEE CLOCK SERIAL DATA IN LOGIC GROUND LOGIC SUPPLY SERIAL DATA OUT STROBE OUTPUT ENABLE VEE 1 2 3 4 5 6 7 8 9 ST OE VDD 18 SUB CLK SHIFT REGISTER 17 16 LATCHES 15 14 13 12 11 10 SUB Dwg. PP-026-1 BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS The merging of low-power CMOS logic and bipolar output power drivers permit the UCN5841/42A, UCN5841/42LW, and A5841/42SLW integrated circuits to be used in a wide variety of peripheral power driver applications. Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The 500 mA npn Darlington outputs, with integral transient-suppression diodes, are suitable for use with relays, solenoids, and other inductive loads. Except for packaging and the maximum driver output voltage ratings, the UCN5841A, UCN5841LW, A5841SLW, UCN5842A, UCN5842LW, and A5842SLW are identical. All package variations of the 5842 offer premium performance with a minimum output-breakdown voltage rating of 80 V (50 V sustaining). All drivers can be operated with a split supply where the negative supply is up to -20 V. BiMOS II devices have higher data-input rates than the earlier BiMOS circuits. With a 5 V logic supply, they will typically operate at better than 5 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, drivers can be cascaded for interface applications requiring additional drive lines. The UCN584xA devices are furnished in a standard 18-pin plastic DIP; the UCN584xLW devices are in an 18-lead surface-mountable wide-body SOIC package; the A584xSLW devices are provided in a 20lead wide-body SOIC package with improved thermal characteristics. The A5841SLW and UCN5841LW drivers are also available for operation to a temperature of -40°C. To order, change the suffix from ‘SLW’ to ‘ELW’, or change the prefix from ‘UCN’ to ‘UCQ’. Data Sheet 26185.14F OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 K Note that the UCN584xA (dual in-line package) and UCN584xLW (small-outline IC package) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at 25°C Free-Air Temperature Output Voltage, VCE (5841) . . . . . . . . . . . . . . . . . . . . . . 50 V (5842) . . . . . . . . . . . . . . . . . . . . . . 80 V Output Voltage, VCE(sus) (5841) . . . . . . . . . . . . . . . . . . . . . 35 V† (5842) . . . . . . . . . . . . . . . . . . . . . 50 V† Logic Supply Voltage Range, VDD . . . . . . . . . . . . . . . . 4.5 V to 15 V VDD with Reference to VEE . . . . . 25 V Emitter Supply Voltage, VEE . . . . . . . -20 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Output Current, IOUT . . . . . . . . . . . . . . . . . . . . 500 mA Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55°C to +150°C †For inductive load applications. Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. FEATURES I To 3.3 MHz Data-Input Rate I CMOS, NMOS, TTL Compatible Inputs I Internal Pull-Up/Pull-Down Resistors I Low-Power CMOS Logic and Latches, I High-Voltage Current-Sink Outputs I Output Transient-Protection Diodes I Single or Split Supply Operation I DIP or SOIC Packaging I Automotive Capable Always order by complete part number, e.g., A5841SLW . 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS FUNCTIONAL BLOCK DIAGRAM (‘A’ Package Shown) CLOCK SERIAL DATA IN LOGIC GROUND 2 VDD 5 LOGIC SUPPLY SERIAL DATA OUT STROBE OUTPUT ENABLE (ACTIVE LOW) 3 SERIAL-PARALLEL SHIFT REGISTER 6 4 LATCHES 7 8 MOS BIPOLAR 1 18 17 16 15 14 13 12 11 10 9 POWER GROUND OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 K SUB Dwg. FP-013-2 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS A5841SLW & A5842SLW POWER GROUND CLOCK SERIAL DATA IN GROUND LOGIC SUPPLY SERIAL DATA OUT STROBE OUTPUT ENABLE POWER GROUND NO CONNECT. 1 SUB 2 3 4 5 6 7 8 9 SUB 10 NC NC 11 NO CONNECT. ST OE VDD CLK 19 18 LATCHES 2.5 2.0 18-PIN DIP, RθJA = 60°C/W 20-LEAD SOIC, RθJA = 70°C/W 18-LEAD SOIC, RθJA = 80°C/W 20 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 K 1.5 SHIFT REGISTER 17 16 15 14 13 12 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. PP-029-3 Dwg. GP-022-4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 2000 Allegro MicroSystems, Inc. 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, VEE = 0 V (unless otherwise specified). Applicable Characteristic Output Leakage Current Symbol ICEX Devices 5841* Test Conditions VOUT = 50 V VOUT = 50 V, TA = +70°C 5842* VOUT = 80 V VOUT = 80 V, TA = +70°C Collector-Emitter Saturation Voltage VCE(SAT) All IOUT = 100 mA IOUT = 200 mA IOUT = 350 mA, VDD = 7.0 V Collector-Emitter Sustaining Voltage Input Voltage VCE(sus) 5841* 5842* VIN(0) VIN(1) All All VDD = 12 V VDD = 10 V VDD = 5.0 V Input Resistance RIN All VDD = 12 V VDD = 10 V VDD = 5.0 V Supply Current IDD(ON) All All Drivers ON, VDD = 12 V All Drivers ON, VDD = 10 V All Drivers ON, VDD = 5.0 V IDD(OFF) All All Drivers OFF, VDD = 12 V All Drivers OFF, VDD = 10 V All Drivers OFF, VDD = 5.0 V Clamp Diode Leakage Current Clamp Diode Forward Voltage IR 5841* 5842* VF All VR = 50 V VR = 80 V IF = 350 mA IOUT = 350 mA, L = 2 mH IOUT = 350 mA, L = 2 mH Min. — — — — — — — 35 50 — 10.5 8.5 3.5 50 50 50 — — — — — — — — — Limits Max. 50 100 50 100 1.1 1.3 1.6 — — 0.8 — — — — — — 16 14 8.0 2.9 2.5 1.6 50 50 2.0 Unit µA µA µA µA V V V V V V V V V kΩ kΩ kΩ mA mA mA mA mA mA µA µA V * Complete part number includes a prefix (A or UCN) and a suffix (A, LW, or SLW) as follows: UCN5841A, UCN5841LW, or A5841SLW, UCN5842A, UCN5842LW, or A5842SLW. www.allegromicro.com 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS TYPICAL INPUT CIRCUITS V DD CLOCK A B DATA IN E C STROBE F D STROBE IN OUTPUT ENABLE OUTPUT ENABLE OUT N G Dwg. No. A-12,627 Dwg. EP-010-3 VDD TIMING CONDITIONS (TA = +25°C, VDD = 5.0 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns CLOCK SERIAL DATA IN B. Minimum Data Active Time After Clock Pulse (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . . 300 ns F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns Dwg. EP-010-4A G. Typical Time Between Strobe Activation and Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µs TYPICAL OUTPUT DRIVER K Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data entry. When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. OUT V EE SUB Dwg. EP-021-8 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 .............. I8 H L X H L R1 R2 .............. R7 R1 R2 .............. R7 Serial Data Strobe Output Input R7 R7 R8 X P8 L H R1 R2 R3 .............. R8 P1 P2 P3 .............. P8 X L = Low Logic Level H = High Logic Level X = Irrelevant X X .............. X L H P1 P2 P3 .............. P8 Latch Contents I1 I2 I3 .............. I8 Output Enable Output Contents I1 I2 I3 .............. I8 R1 R2 R3 .............. R8 X X X .............. X P1 P2 P3 .............. P8 H H H .............. H P = Present State R = Previous State TYPICAL APPLICATION RELAY/SOLENOID DRIVER Using Split Supply UCN5842A The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Dwg. No. A-12,547 www.allegromicro.com 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5841A and UCN5842A Dimensions in Inches (controlling dimensions) 18 10 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 0.920 0.880 BSC 9 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-18A in Dimensions in Millimeters (for reference only) 18 10 0.355 0.204 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 23.37 22.35 BSC 9 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-18A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5841LW and UCN5842LW Dimensions in Inches (for reference only) 18 10 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.4625 0.4469 0.050 BSC 0° TO 8° 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-18A in Dimensions in Millimeters (controlling dimensions) 18 10 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 11.75 11.35 1.27 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-18A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 5 841 AND 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS A5841SLW and A5842SLW Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.5118 0.4961 0.050 BSC 0° TO 8° 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-20 in Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 13.00 12.60 1.27 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000