UCN5910LW

5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS OUT 8 OUT 7 OUT 6 CLOCK LOGIC GROUND LOGIC SUPPLY STROBE POWER GROUND OUT 5 OUT 4 1 2 3 4 5 6 7 8 9 20 19 OUT 9 OUT 10 Note that the dual in-line package (designator ‘A’) and small-outline IC package (designator ‘LW’) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD ................ 15 V Driver Supply Voltage, VBB UCN5910A/LW ......................... 150 V Suffix “-2” .................................. 140 V Continuous Output Current Range, IOUT ....................... -30 mA to +40 mA Input Voltage Range, VIN .................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD . See Graph Operating Temperature Range, TA ............................... -20°C to +85°C Storage Temperature Range, TS .............................. -55°C to +150°C Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. T C UY DL ON RO PE DC EN UE IN ER TF NE OR CR IS O DF — VBB 18 17 16 LATCHES LOAD SUPPLY (6-10) SERIAL DATA OUT SERIAL DATA IN CLK REGISTER REGISTER LATCHES SUB The UCN5910x combines a 10-bit CMOS shift register and accompanying data latches, control circuitry, high-voltage bipolar sourcing outputs with DMOS active pull-downs. Designed primarily to drive ink-jet and piezoelectric printers, large flat-panel vacuum-fluorescent or ac plasma displays, the 140 V or 150 V and ±50 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The lower-cost (suffix “-2”) devices are identical to the basic devices except for output voltage rating. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, serial-data input rates are typically over 5 MHz, with significantly higher speeds obtainable at 12 V. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices for up to 60-volt operation are available in 10, 12, 20, and 32-bit configurations. The UCN5910A/LW output source drivers are npn Darlingtons capable of sourcing at least 40 mA. The DMOS active pull-downs are capable of sinking at least 30 mA. For inter-digit blanking, all of the output drivers can be disabled and the DMOS sink drivers turned ON by the BLANKING input high. The UCN5910A and UCN5910A-2 are furnished in a 20-pin dual in-line plastic package. The surface-mount UCN5910LW and UCN5910LW-2 are furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and lower output saturation voltages allow all devices to be operated at ±20 mA from all outputs (50% duty cycle), at ambient temperatures up to +30°C, or at ±15 mA to +55°C. Data Sheet 26182.2A VDD ST BLNK 15 VBB 14 13 BLANKING LOAD SUPPLY (1-5) OUT 1 OUT 2 OUT 3 12 10 11 Dwg. PP-029-14 FEATURES s High-Speed Source Drivers s 140 V (suffix “-2”) or 150 V Minimum Output Breakdown s Improved Replacements for TL4810B s s s s Low Output Saturation Voltages Low-Power CMOS Logic and Latches To 3.3 MHz Data Input Rate Active DMOS Pull-Downs PRELIMINARY INFORMATION (Subject to change without notice) January 18, 2000 Always order by complete part number, e.g., UCN5910A-2 . 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER LATCHES BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TYPICAL INPUT CIRCUIT VDD IN ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 2.0 SU FF IX Dwg. EP-010-4A 1.5 SU FF IX 'A ', R θJ A= TYPICAL OUTPUT DRIVER 55 °C /W 'LW ', R V BB 1.0 θJ A= 70 °C /W 0.5 OUT N 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GS-004A Dwg. No. A-14,219 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1984, 1999, Allegro MicroSystems, Inc. 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 150 V (basic devices) or 140 V (suffix “-2”) unless otherwise noted. Limits @ VDD = 5 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) Test Conditions VOUT = 0 V, TA = +70°C Basic, IOUT = -40 mA Suffix “-2”, IOUT = -40 mA VOUT(0) IOUT = 5 mA IOUT = 10 mA IOUT = 30 mA Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB VOUT = 20 V to VBB Input Voltage VIN(1) VIN(0) Input Current IIN(1) IIN(0) Serial Data Output Voltage VOUT(1) VOUT(0) Maximum Clock Frequency Supply Current fclk IDD(1) IDD(0) IBB(1) IBB(0) Blanking to Output Delay tPHL tPLH Output Fall Time Output Rise Time tf tr All Outputs High All Outputs Low Outputs High, No Load Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% CL = 30 pF, 90% to 10% CL = 30 pF, 10% to 90% VIN = VDD VIN = 0.8 V IOUT = -200 µA IOUT = 200 µA Mln. Typ. Max. – 145 135 – – – 10 – 3.5 -0.3 – -0.3 4.5 – 3.3 – – – – – – – – -5.0 148 – 2.5 5.0 – 14 – – – 0.05 – 5.0 200 5.0 320 320 0.6 10 0.7 0.9 1.3 1.2 -15 – – 3.2 – – – – 5.3 +0.8 0.5 -0.8 – 250 – 450 450 1.75 100 0.9 1.3 1.5 1.5 Limits @ VDD = 12 V Min. Typ. Max. – 145 135 – – – – 25 10.5 -0.3 – -0.3 11.7 – 5.0 – – – – – – – – -5.0 148 – 2.0 – 12 – 40 – – 0.05 – 12 200 – 650 650 0.9 10 0.35 0.35 0.6 1.0 -15 – – 3.2 – 25 – – 12.3 +0.8 1.0 -0.8 – 250 – 800 800 1.75 100 0.6 0.6 0.7 1.2 Units µA V V V V V mA mA V V µA µA V mV MHz µA µA mA µA µs µs µs µs Negative current is defined as coming out of (sourcing) the specified device terminal. 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS CLOCK DATA IN C STROBE BLANKING G OUTN Dwg. No. A-12,649A A B D E F Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. (TA = +25°C, VDD = 12 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................... 75 ns C. Minimum Data Pulse Width ............................................................. 150 ns D. Minimum Clock Pulse Width ........................................................... 100 ns E. F. Minimum Time Between Clock Activation and Strobe .................... 300 ns Minimum Strobe Pulse Width .......................................................... 100 ns TIMING CONDITIONS G. Typical Time Between Strobe Activation and Output Transition ............................................................................. 750 ns TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L Latch Contents I1 I2 I3 ... IN-1 IN Blanking Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... P1 P2 P3 ... PN-1 PN P = Present State R = Previous State 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5910A & UCN5910A-2 Dimensions in Inches (controlling dimensions) 20 11 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 BSC 10 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 20 11 0.355 0.204 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-20 mm NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5910LW & UCN5910LW-2 Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.5118 0.4961 0.050 BSC 0° TO 8° 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-20 in Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 13.00 12.60 1.27 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS This page intentionally left blank 5910 HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS BiMOS II (Series 5800), BiMOS III (Series 5900), & DABiC IV (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS Function 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit (constant-current LED driver) 9-Bit 10-Bit (active pull-downs) 10-Bit (active pull-downs) 10-Bit (active pull-downs) 12-Bit (active pull-downs) 16-Bit (constant-current LED driver) 20-Bit (active pull-downs) 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) 4-Bit 8-Bit 8-Bit Unipolar Stepper Motor Translator/Driver Addressable 28-Line Decoder/Driver * † ‡ Output Ratings* SERIAL-INPUT LATCHED DRIVERS -120 mA 350 mA 350 mA 350 mA 350 mA 75 mA 1.6 A -25 mA -40 mA -40 mA -25 mA 75 mA -25 mA -25 mA 100 mA 100 mA 350 mA -25 mA 350 mA 1.25 A 450 mA 50 V‡ 50 V 80 V 50 V‡ 80 V‡ 17 V 50 V 60 V 140 V 150 V 60 V 17 V 60 V 60 V 30 V 40 V 50 V‡ 60 V 50 V‡ 50 V‡ 30 V 5895 5821 5822 5841 5842 6275 5829 5810-F and 6809/10 5910-2 5910 5811 and 6811 6276 5812-F and 6812 5818-F and 6818 5833 5832 5800 5815 5801 5804 6817 Part Number† PARALLEL-INPUT LATCHED DRIVERS SPECIAL-PURPOSE DEVICES Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000