HSACTD003A

3-axis Accelerometer 1 / 84 Rev.1.1 Apr. 2018 HSACTD003A Data Sheet HSACTD003A □Accelerometer function Head office 1-7,Yukigaya-otsukamachi, Ota-ku, Tokyo, 145-8501, JAPAN Phone+81 3-3726-1211 FAX+81 3-3728-1741 Nagaoka Plant 1-3-5, Higashitakamimachi, Nagaoka-city, Niigata-pref.940-0006, JAPAN Phone+81 258-24-4111 FAX+81 258-24-4110 This specification is subject to change without notice. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 2 / 84 Rev.1.1 Apr. 2018 - OVERVIEW This product is an ultra-low power, low-noise, integrated digital output 3-axis accelerometer with a feature set optimized for wearables and consumer product motion sensing. Applications include wearable consumer products, IoT devices, user interface control, gaming motion input, electronic compass tilt compensation for cell phones, game controllers, remote controls and portable media products. Low noise and low power are inherent in the monolithic fabrication approach, where the MEMS accelerometer is integrated in a single-chip with the electronics integrated circuit. The internal sample rate can be set from 14 to 1300 samples / second. Specific tap or sample acquisition conditions can trigger an interrupt to a remote MCU. Alternatively, the device supports the reading of sample and event status via polling. - FEATURES Range, Sampling & Power ・ ±2, 4, 8, 12 or 16g ranges ・ 8, 10 or 12-bit resolution with FIFO o 14-bit single samples ・ Sample rate 14 - 1300 samples/sec o Sample trigger via internal oscillator, clock pin or software command ・ Sniff and Wake modes o 0.4 μA Sniff current @ 6Hz o Separate or combined sniff/wake ・ Ultra-Low Power with 32 sample FIFO o 0.9 μA typical current @ 25Hz o 1.6 μA typical current @ 50Hz o 2.8 μA typical current @ 100Hz o 36 μA typical current @ 1300Hz Simple System Integration ・ I2C interface, up to 1 MHz ・ SPI Interface, up to 8 MHz ・ 1.6 × 1.6 × 0.94 mm 10-pin package ・ Single-chip 3D silicon MEMS ・ Low noise to 2.3mgRMS Confidential 3-axis Accelerometer HSACTD003A 3 / 84 Rev.1.1 Apr. 2018 Table of Contents 1 Order Information ............................................................................................................. 5 5 2 Functional Block Diagram ................................................................................................ 6 6 3 Packaging and Pin Description ........................................................................................ 7 7 3.1 Package Outline ................................................................................................................... 7 7 3.2 Package Orientation ............................................................................................................. 8 8 3.3 Pin Description ..................................................................................................................... 9 9 3.4 Typical Application Circuits ................................................................................................ 10 10 3.5 Tape and Reel ................................................................................................................... 13 13 4 Specifications ................................................................................................................. 15 15 4.1 Absolute Maximum Ratings ................................................................................................ 15 15 4.2 Sensor Characteristics ....................................................................................................... 16 16 4.3 Electrical and Timing Characteristics .................................................................................. 17 17 4.3.1 Electrical Power and Internal Characteristics .................................................................. 17 17 4.3.2 Electrical Characteristics ................................................................................................ 18 18 4.3.3 I2C Timing Characteristics .............................................................................................. 19 19 4.3.4 SPI Timing Characteristics.............................................................................................. 20 20 5 General Operation ......................................................................................................... 21 21 5.1 Sensor Sampling ................................................................................................................ 21 21 5.2 Offset and Gain Calibration ................................................................................................ 21 21 5.3 Reset ................................................................................................................................. 21 21 5.4 Reload ............................................................................................................................... 22 22 5.5 Operational Modes ............................................................................................................. 23 23 5.6 Mode State Machine Flow .................................................................................................. 24 24 6 Interfaces ....................................................................................................................... 25 25 6.1 SPI vs I2C Operation Modes .............................................................................................. 25 25 6.2 I2C Physical Interface ........................................................................................................ 25 25 6.3 I2C Message Format .......................................................................................................... 26 26 6.4 SPI Physical Interface ........................................................................................................ 27 27 6.5 SPI 3-Wire Mode ................................................................................................................ 27 27 6.6 SPI Protocol ....................................................................................................................... 27 27 6.7 SPI Register Write Cycle - Single ....................................................................................... 28 28 6.8 SPI Register Write Cycle - Burst ........................................................................................ 28 28 Confidential 3-axis Accelerometer HSACTD003A 4 / 84 Rev.1.1 Apr. 2018 Table of Contents (Continue) 6.9 SPI Register Read Cycle - Single ....................................................................................... 28 28 6.10 SPI Register Read Cycle - Burst ........................................................................................ 29 29 6.11 SPI Status Option ............................................................................................................... 29 29 6.12 SPI High-Speed Mode........................................................................................................ 30 30 7 Register Interface .......................................................................................................... 31 31 7.1 Register Summary ............................................................................................................. 32 32 7.2 (0x00) Extended Status Register 1 ..................................................................................... 34 34 7.3 (0x01) Extended Status Register 2 ..................................................................................... 35 35 7.4 (0x02 – 0x07) XOUT, YOUT & ZOUT Data Output Registers ............................................. 36 36 7.5 (0x08) Status Register 1 ..................................................................................................... 37 37 7.6 (0x09) Status Register 2 ..................................................................................................... 39 39 7.7 (0x0D) Feature Register 1 .................................................................................................. 41 41 7.8 (0x0E) Feature Register 2 .................................................................................................. 43 43 7.9 (0x0F) Initialization Register 1 ............................................................................................ 46 46 7.10 (0x10) Mode Control Register ............................................................................................ 47 47 7.11 (0x11) Rate Register 1 ....................................................................................................... 49 49 7.12 (0x12) Sniff Control Register .............................................................................................. 51 51 7.13 (0x13) Sniff Threshold Control Register ............................................................................. 54 54 7.14 (0x14) Sniff Configuration Register .................................................................................... 57 57 7.15 (0x15) Range and Resolution Control Register .................................................................. 59 59 7.16 (0x16) FIFO Control Register ............................................................................................. 61 61 7.17 (0x17) Interrupt Control Register ........................................................................................ 62 62 7.18 (0x1A) Initialization Register 3 ............................................................................................ 64 64 7.19 (0x1B) Scratchpad Register ............................................................................................... 65 65 7.20 (0x1C) Power Mode Control Register ................................................................................. 66 66 7.21 (0x20) Drive Motion X Register .......................................................................................... 68 68 7.22 (0x21) Drive Motion Y Register .......................................................................................... 69 69 7.23 (0x22) Drive Motion Z Register ........................................................................................... 70 70 7.24 (0x24) Reset Register ........................................................................................................ 71 71 7.25 (0x28) Initialization Register 2 ............................................................................................ 72 72 7.26 (0x29) Trigger Count Register ............................................................................................ 73 73 7.27 (0x2A – 0x2B) X-Axis Offset Registers ............................................................................... 74 74 7.28 (0x2C – 0x2D) Y-Axis Offset Registers .............................................................................. 75 75 7.29 (0x2E – 0x2F) Z-Axis Offset Registers ............................................................................... 76 76 7.30 (0x2B & 0x30) X-Axis Gain Registers ................................................................................. 77 77 7.31 (0x2D & 0x31) Y-Axis Gain Registers ................................................................................. 78 78 7.32 (0x2F & 0x32) Z-Axis Gain Registers ................................................................................. 79 79 8 Index of Tables .............................................................................................................. 80 80 9 Revision History ............................................................................................................. 82 82 10 Legal .............................................................................................................................. 83 83 11 Asking that use this product ..................................................................................................................... 84 Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 5 / 84 Rev.1.1 Apr. 2018 1 ORDER INFORMATION Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 1 482 5 7 6 3 9 3-axis Accelerometer HSACTD003A 6 / 84 Rev.1.1 Apr. 2018 2 FUNCTIONAL BLOCK DIAGRAM Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 482 5 7 6 3 9 3-axis Accelerometer HSACTD003A 7 / 84 Rev.1.1 Apr. 2018 3 PACKAGING AND PIN DESCRIPTION 3.1 PACKAGE OUTLINE Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 482 5 7 6 3 9 3-axis Accelerometer HSACTD003A 8 / 84 Rev.1.1 Apr. 2018 3.2 PACKAGE ORIENTATION Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 482 5 7 6 3 9 3-axis Accelerometer HSACTD003A 9 / 84 Rev.1.1 Apr. 2018 3.3 PIN DESCRIPTION Notes: 1) When using the I2C interface, this pin requires a pull-up resistor, typically 4.7kΩ to pin VDDIO. Refer to I2C Specification for Fast-Mode devices. Higher resistance values can be used (typically done to reduce current leakage) but such applications are outside the scope of this datasheet. 2) This pin can be configured by software to operate either as an open-drain output or push-pull output. If set to open-drain, then it requires a pull-up resistor, typically 4.7kΩ to pin VDDIO. 3) INTN pin polarity is programmable. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 10 / 84 Rev.1.1 Apr. 2018 3.4 TYPICAL APPLICATION CIRCUITS In typical applications, the interface power supply may contain significant noise from external sources and other circuits which should be kept away from the device. Therefore, for some applications a lower-noise power supply might be desirable to power the device. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 11 / 84 Rev.1.1 Apr. 2018 3.4 TYPICAL APPLICATION CIRCUITS (Continue) (／) (／) Confidential ALPS ELECTRIC CO.,LTD. 11 10 67548293 3-axis Accelerometer HSACTD003A 12 / 84 Rev.1.1 Apr. 2018 3.4 TYPICAL APPLICATION CIRCUITS (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 13 / 84 Rev.1.1 Apr. 2018 3.5 TAPE AND REEL Devices are shipped in reels, in standard cardboard box packaging. See Figure 8. Tape Dimensions and Figure 9. Reel Dimensions. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 14 / 84 Rev.1.1 Apr. 2018 3.5 TAPE AND REEL (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 15 / 84 Rev.1.1 Apr. 2018 4 SPECIFICATIONS 4.1 ABSOLUTE MAXIMUM RATINGS Parameters exceeding the Absolute Maximum Ratings may permanently damage the device. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 16 / 84 Rev.1.1 Apr. 2018 HSACTD003A 4.2 SENSOR CHARACTERISTICS 1 Values are based on device characterization, not tested in production. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 17 / 84 Rev.1.1 Apr. 2018 4.3 ELECTRICAL AND TIMING CHARACTERISTICS 4.3.1 ELECTRICAL POWER AND INTERNAL CHARACTERISTICS 2 Min and Max limits are hard limits without additional tolerance. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 18 / 84 Rev.1.1 Apr. 2018 HSACTD003A 4.3.2 ELECTRICAL CHARACTERISTICS NOTES: ・ If multiple slaves are connected to the I2C signals in addition to this device, only 1 pull-up resistor on each of SDA and SCL should exist. Also, care must be taken to not violate the I2C specification for capacitive loading. ・ When pin VDDIO is not powered and set to 0V, INTN, DIN_SDA and SCK_SCL will be held to VDDIO plus the forward voltage of the internal static protection diodes, typically about 0.6V. ・ When pin VDDIO is disconnected from power or ground (e.g. Hi-Z), the device may become inadvertently powered up through the ESD diodes present on other powered signals. 3 Values are based on device characterization, not tested in production. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 19 / 84 Rev.1.1 Apr. 2018 HSACTD003A 4.3.3 I2C TIMING CHARACTERISTICS NOTE: Values are based on I2C Specification requirements, not tested in production. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 20 / 84 Rev.1.1 Apr. 2018 4.3.4 SPI TIMING CHARACTERISTICS 4 Values are based on device characterization. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 21 / 84 Rev.1.1 Apr. 2018 5 GENERAL OPERATION The device supports the reading of samples and device status upon interrupt or via polling. It contains a 12-bit 32 sample FIFO with programmable watermark. The device is internally clocked but also includes a manual trigger mode. It can be put into several low power modes, depending upon the desired sensing application. The device can run in full-featured mode from its fast internal clock or from a slower heartbeat clock, with limited functionality and at lower power. The device can connect as a slave to either a SPI or I2C master. 5.1 SENSOR SAMPLING X, Y and Z accelerometer data is stored in registers XOUT, YOUT, and ZOUT registers. The data is represented as 2’s complement format. The desired resolution and full scale acceleration range are set in the RANGE_C register. 5.2 OFFSET AND GAIN CALIBRATION The default digital offset and gain calibration data can be read from the device, if necessary, in order to reduce the effects of post-assembly influences and stresses which may cause the sensor readings to be offset from their factory values. 5.3 RESET The device can be completely reset via an I2C or SPI instruction. Writing register 0x24 with 0x40 (bit 6) causes a power-on reset operation to execute. No attempt should be made to access registers within 1mSec after issuing this operation. The device must be placed in STANDBY mode before executing the reset. The pin DOUT_A1 is sampled for the purposes of setting the I2C device address after this reset operation. NOTE: Immediately after a RESET or power-up event, several registers must be written with initialization values as shown below. The recommended sequence is: Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 22 / 84 Rev.1.1 Apr. 2018 5.4 RELOAD The device registers can be reloaded from OTP via an I2C or SPI instruction. Writing register 0x24 with 0x80 (bit 7) causes a reload operation to execute. The contents of OTP are reloaded into the register set. However any non-loaded register locations will not be affected. No attempt should be made to access registers within 1mSec after issuing this operation. The device must be placed in STANDBY mode before executing the reset. The pin DOUT_A1 is sampled for the purposes of setting the I2C device address after this reload operation. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 23 / 84 Rev.1.1 Apr. 2018 5.5 OPERATIONAL MODES The device has various modes of operation as described below: Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 24 / 84 Rev.1.1 Apr. 2018 5.6 MODE STATE MACHINE FLOW Figure 12. Mode Operational Flow shows the operational mode flow for the device. The device defaults to SLEEP mode following power-on. Mode transitions occur at an approximate rate of ~500Hz. Depending on the operation, the MODE State Machine may trigger events that autoclear or set the MCTRL[2:0] bits in register 0x10 after a particular command is chosen. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 25 / 84 Rev.1.1 Apr. 2018 6 INTERFACES 6.1 SPI VS I2C OPERATION MODES The device contains both I2C and SPI slave interfaces which share common pins. However, only one interface can be active for correct device operation. Once the device completes POR or a hard reset, both interfaces are active. After power-up and any reset of the device, the first transaction to the device must be writing to the selected enable bit, either “I2C_EN” or “SPI_EN” in register 0x0D. The situation where bits are set at the same time must be avoided or unstable device operation could occur. To keep the “disabled” interface from interfering in future transactions, the corresponding “enable” bit must be set in the register set. For example, if the 4wire SPI interface is to be active, write a value of 0x80 to register 0x0D. 6.2 I2C PHYSICAL INTERFACE The I2C slave interface operates at a maximum speed of 1 MHz in I2C “Fast Mode Plus”. The SDA (data) is an open-drain, bi-directional pin and the SCL (clock) is an input pin. The device always operates as an I2C slave. An I2C master initiates all communication and data transfers and generates the SCK_SCL clock that synchronizes the data transfer. The I2C device address depends upon the settings of various registers and pins as shown in the table below. An I2C master initiates all communication and data transfers and generates the SCK_SCL clock that synchronizes the data transfer. The I2C device address depends upon the state of pin DOUT_A1 during power-up as shown in the table below. The I2C interface remains active as long as power is applied to the VDDIO pin. In STANDBY mode the device responds to I2C read and write cycles, but interrupts cannot be cleared. All registers can be written in the SLEEP or STANDBY modes, but in CWAKE only the (0x10) Mode Control Register can be modified. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 26 / 84 Rev.1.1 Apr. 2018 6.2 I2C PHYSICAL INTERFACE (Continue) Internally, the registers which are used to store samples are clocked by the sample clock and gated by I2C activity. Therefore, in order to allow the device to collect and present samples in the sample registers at least one I2C STOP condition must be present between samples. Refer to the I2C specification for a detailed discussion of the protocol. Per I2C requirements, when the I2C interface is enabled, DIN_SDA is an open drain, bidirectional pin. Pins SCK_SCL and DIN_SDA each require an external pull-up resistor, typically 4.7kΩ. 6.3 I2C MESSAGE FORMAT NOTE: At least one I2C STOP condition must be present between samples in order for the device to update the sample data registers. The device uses the following general format for writing to the internal registers. The I2C master generates a START condition, and then supplies the 7-bit device ID. The 8th bit is the R/W# flag (write cycle = 0). The device pulls DIN_SDA low during the 9th clock cycle indicating a positive ACK. The second byte is the 8-bit register address of the device to access, and the last byte is the data to write. In a read cycle, the I2C master writes the device ID (R/W#=0) and register address to be read. The master issues a RESTART condition and then writes the device ID with the R/W# flag set to ‘1’. The device shifts out the contents of the register address. The I2C master may write or read consecutive register addresses by writing or reading additional bytes after the first access. The device will internally increment the register address. NOTE: See (0x0E) Feature Register 2 for address wrap details. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 27 / 84 Rev.1.1 Apr. 2018 6.4 SPI PHYSICAL INTERFACE The device always operates as an SPI slave. An SPI master must initiate all communication and data transfers and generate the SCK_SCL clock that synchronizes the data transfer. The CSN pin must be pulled up to VDDIO when the SPI interface is not in use. The SPI interface can operate in 3-wire or 4-wire mode. 6.5 SPI 3-WIRE MODE SPI 3-wire mode is disabled by default. To enable 3-wire mode, the first write to the device should immediately enable this feature in register (0x0D) Feature Register 1. In 3-wire mode the pins DOUT_A1 and DIN_SDA must be connected on the PCB. Anytime there is a reset to the device, a POR event, or a power cycle the SPI 3-wire configuration will reset to 4-wire mode. 6.6 SPI PROTOCOL The general protocol for the SPI interface is shown in the figures below. The falling edge of CSN initiates the start of the SPI bus cycle. The first byte of the transaction is the command/address byte. Because the register address space is 64 locations, a total of 6 address bits are required for each SPI bus cycle. During clock ‘1’, the R/W# bit is set to ‘0’ for a write cycle or ‘1’ for a read cycle. The interface supports 2 types of addressing: 1-byte (typically used) and 2-byte (to support legacy hardware). In the case of 2-byte addressing, the bits occurring during clocks 2 and 9-16 must be driven to ‘0’ for the address to be correctly decoded. Each read or write transaction always requires a minimum of 16 or 24 cycles of the SCK_SCL pin. When the SPI master is writing data, data may change when the clock is low, and must be stable on the clock rising edge. Similarly, output data written to the SPI master is shifted out on the falling edge of clock and can be latched by the master on the rising edge of the clock. Serial data in or out of the device is always MSB first. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 28 / 84 Rev.1.1 Apr. 2018 6.6 SPI PROTOCOL (Continue) NOTE: Either 1-byte or 2-byte addressing may be used for any SPI transaction, although for simplicity, the remaining timing diagrams show only 1-byte addressing. 6.7 SPI REGISTER WRITE CYCLE - SINGLE A single register write consists of a 16-clock transaction. As described above, the first bit is set to ‘0’ indicating a register write followed by the register address. 6.8 SPI REGISTER WRITE CYCLE - BURST A burst (multi-byte) register write cycle uses the address specified at the beginning of the transaction as the starting register address. Internally the address will auto-increment to the next consecutive address for each additional byte (8-clocks) of data written beyond clock 8. NOTE: See (0x0E) Feature Register 2 for address wrap details. 6.9 SPI REGISTER READ CYCLE - SINGLE A single register read consists of a 16-clock transaction. As described above, the first bit is set to ‘1’ indicating a register read followed by the register address. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 29 / 84 Rev.1.1 Apr. 2018 6.10 SPI REGISTER READ CYCLE - BURST A burst (multi-byte) register read cycle uses the address specified at the beginning of the transaction as the starting register address. Internally the address will auto-increment to the next consecutive address for each additional byte (8-clocks) of data read beyond clock 8. NOTE: See (0x0E) Feature Register 2 for address wrap details. 6.11 SPI STATUS OPTION The device supports an optional SPI status feature, only in SPI 4-wire mode. This feature is enabled in register (0x0E) Feature Register 2. During the first 6-bits of any SPI transaction (immediately after the falling edge of CSN), the DOUT_A1 pin will output six status bits related to the device. Following the 6th clock cycle, the device will float the DOUT_A1 pin before a possible read cycle begins. The status bits sent are shown below: Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 30 / 84 Rev.1.1 Apr. 2018 6.12 SPI HIGH-SPEED MODE To achieve SPI speed greater than 2MHz, use the following sequence: - Start SPI at low speed (less than 2MHz) - Enable SPI mode – ・ “SPI_EN” in section 7.7 (0x0D) Feature Register 1 - Enable high speed SPI mode – ・ “SPI_HS_EN” in section 7.20 (0x1C) Power Mode Control Register - Increase SPI speed up to 8MHz Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 31 / 84 Rev.1.1 Apr. 2018 7 REGISTER INTERFACE The device has a simple register interface which allows an SPI or I2C master to configure and monitor all aspects of the device. This section lists an overview of user programmable registers. By convention, bit 0 is the least significant bit (LSB) of a byte register. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 32 / 84 Rev.1.1 Apr. 2018 7.1 REGISTER SUMMARY Confidential 3-axis Accelerometer HSACTD003A 33 / 84 Rev.1.1 Apr. 2018 6.1.2. Sensor Sampling 4 ‘R’ registers are read-only. ‘W’ registers are read-write. 'WO' registers are write only. Confidential 3-axis Accelerometer HSACTD003A 34 / 84 Rev.1.1 Apr. 2018 7.2 (0X00) EXTENDED STATUS REGISTER 1 This register contains status for the I2C address of the device. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 35 / 84 Rev.1.1 Apr. 2018 7.3 (0X01) EXTENDED STATUS REGISTER 2 The device status register reports various conditions of the device data, clock and sniff circuitry. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 111 67548293 3-axis Accelerometer HSACTD003A 36 / 84 Rev.1.1 Apr. 2018 7.4 (0X02 – 0X07) XOUT, YOUT & ZOUT DATA OUTPUT REGISTERS The measurements from sensors for the 3-axes are available in these 3 registers. The most-significant bit of the value is the sign bit, and is sign extended to the higher bits. Software must set only one of the bits SPI_EN or I2C_EN in register 0x0D to ‘1’, depending upon if the I2C or SPI interface will be used for external communications. No data will appear in XOUT, YOUT and ZOUT registers if both the I2C_EN bit and SPI_EN bit are set to 0 (default). When the FIFO is enabled, the output of the FIFO is mapped to registers 0x02 to 0x07, and the data has a maximum resolution of 12-bits. During FIFO reads, software must start a read at address 0x02 and complete a read to address 0x07 for the FIFO pointers to increment correctly. Once an I2C start bit has been recognized by the device, registers will not be updated until an I2C stop bit has occurred. Therefore, if software desires to read the low and high byte registers ‘atomically’, knowing that the values have not been changed, it should do so by issuing a start bit, reading one register, then reading the other register then issuing a stop bit. Note that all 6 registers may be read in one burst with the same effect. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 37 / 84 Rev.1.1 Apr. 2018 7.5 (0X08) STATUS REGISTER 1 This register reports the operational mode of the device. Note that the lower 3bits, the MODE[2:0] field, do not immediately change once a command is written to the MODE register, but may take up to 3 transitions of the heartbeat clock. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 38 / 84 Rev.1.1 Apr. 2018 7.5 (0X08) STATUS REGISTER 1 (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 39 / 84 Rev.1.1 Apr. 2018 7.6 (0X09) STATUS REGISTER 2 This register reports the state of the interrupts (‘0’ means not pending; ‘1’ means pending). A bit in this register will only be set if the corresponding interrupt enable is set to ‘1’ in (0x17) Interrupt Control Register. Interrupts can be cleared in the following ways using (0x0E) Feature Register 2 bit 4: Interface I2C clearing method (default) I2C clearing method (optional) SPI clearing method Method Read Register 0x09 Write Register 0x09 Write Register 0x09 Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 40 / 84 Rev.1.1 Apr. 2018 7.6 (0X09) STATUS REGISTER 2 (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 41 / 84 Rev.1.1 Apr. 2018 7.7 (0X0D) FEATURE REGISTER 1 This register is used to select the interface mode as well as the operation style of the FIFO and interrupt in SWAKE mode. NOTE: Software must set only one of the bits SPI_EN or I2C_EN in register 0x0D to ‘1’, depending upon if the I2C or SPI interface will be used for external communications. No data will appear in XOUT, YOUT and ZOUT registers if both the I2C_EN bit and SPI_EN bit are set to 0 (default). (／) (／) Confidential ALPS ELECTRIC CO.,LTD. 11 10 67548293 3-axis Accelerometer HSACTD003A 42 / 84 Rev.1.1 Apr. 2018 7.7 (0X0D) FEATURE REGISTER 1 (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 43 / 84 Rev.1.1 Apr. 2018 7.8 (0X0E) FEATURE REGISTER 2 This register allows selection of various features for the FIFO, external trigger input, method of interrupt clearing and burst address wrapping. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 44 / 84 Rev.1.1 Apr. 2018 7.8 (0X0E) FEATURE REGISTER 2 (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 45 / 84 Rev.1.1 Apr. 2018 7.8 (0X0E) FEATURE REGISTER 2 (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 46 / 84 Rev.1.1 Apr. 2018 7.9 (0X0F) INITIALIZATION REGISTER 1 Software must write a fixed value to this register immediately after power-up or reset. This register will not typically read-back the value which was written (see below). Note: During the internal chip start-up sequence, the read-back value will be 0x45. The read-back value will become 0x40 after the start-up sequence completes. After the initialization value of 0x42 is written, the read-back value will be 0x43. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 47 / 84 Rev.1.1 Apr. 2018 7.10 (0X10) MODE CONTROL REGISTER This register is the primary control register for the accelerometer. The operational mode of the device, X/Y/Z axis enables, and the TRIG one-shot mode can be written through this register. The mode transitions controlled by this register may take up to 3 transitions of the heartbeat clock. Depending on the operation, the lower 3-bits (MCTRL[2:0]) may be automatically set or cleared by hardware if auto-triggered events are executed. In general, when software sets an operational mode using the MCTRL [2:0] bits, there might be a delay time of 2 to 10 mSec before the operational mode is reflected by the MODE[2:0] bits in Status Register 1. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 48 / 84 Rev.1.1 Apr. 2018 7.10 (0X10) MODE CONTROL REGISTER (Conitinue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 49 / 84 Rev.1.1 Apr. 2018 7.11 (0X11) RATE REGISTER 1 This register configures the sample rates for wake modes. The rates also depend upon the value in register 0x1C. The device has several power modes which can be adjusted to achieve a desired power consumption at a certain ODR. The tradeoff for lower power is either higher noise or lower ODR. See the table below. NOTE: The power mode bits referenced in 0x1C are different than for the SNIFF rates. NOTE: Software must set bits[7:4] to 0. NOTE: Specific setup steps are required in order to set up Register 0x11 value 0x0F (“Rate 15”), as shown below. These steps are not required when using the other modes: Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 50 / 84 Rev.1.1 Apr. 2018 7.11 (0X11) RATE REGISTER 1 (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 51 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.12 (0X12) SNIFF CONTROL REGISTER This register selects the sample rate for SNIFF mode and the clock rate for STANDBY mode. NOTE: The power mode bits referenced in 0x1C are different than for the WAKE rates. NOTE: Software must always write 0 to bit 4. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 52 / 84 Rev.1.1 Apr. 2018 7.12 (0X12) SNIFF CONTROL REGISTER (Continue) NOTE: Specific setup steps are required in order to set up Register 0x12 value 0x0F (“Rate 15”) for sniff, as shown below. These steps are not required when using the other modes: Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 53 / 84 Rev.1.1 Apr. 2018 7.12 (0X12) SNIFF CONTROL REGISTER (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 54 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.13 (0X13) SNIFF THRESHOLD CONTROL REGISTER This register sets the threshold values used by the SNIFF logic for activity detection. For each axis, a delta count is generated and compared to the threshold. When the delta count is greater than the threshold, a SNIFF wakeup event occurs. There is a unique sniff threshold for each axis, and an optional “false detection count” which requires multiple sniff detection events to occur before a wakeup condition is declared. These features are set by six shadow registers accessed by register 0x13[5:0] and register 0x14 bits [2:0]. The SNIFF block supports the logical AND or OR of the X/Y/Z SNIFF wakeup flags when generating a SNIFF wakeup interrupt. The SNIFF block supports two methods of calculating SNIFF delta counts: ・ Current Sample to Previous Sample (C2P) ○ The current sample and the immediate previous sample are subtracted to generate a delta ・ Current Sample to Baseline (C2B) ○ The current sample and the first sample captured when entering SNIFF mode are subtracted to generate a delta. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 55 / 84 Rev.1.1 Apr. 2018 7.13 (0X13) SNIFF THRESHOLD CONTROL REGISTER (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 56 / 84 Rev.1.1 Apr. 2018 7.13 (0X13) SNIFF THRESHOLD CONTROL REGISTER (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 57 / 84 Rev.1.1 Apr. 2018 7.14 (0X14) SNIFF CONFIGURATION REGISTER This register selects which of the six shadow registers is being accessed in register 0x13, and controls settings of the SNIFF hardware. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 58 / 84 Rev.1.1 Apr. 2018 7.14 (0X14) SNIFF CONFIGURATION REGISTER (Continue) Some example settings for the SNIFF_MUX field are shown below: Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 59 / 84 Rev.1.1 Apr. 2018 7.15 (0X15) RANGE AND RESOLUTION CONTROL REGISTER The RANGE register sets the resolution and range options for the accelerometer. All numbers are sign-extended, 2’s complement format. All results are reported in registers 0x02 to 0x07. When the FIFO is enabled, only 6 to 12-bit resolutions are supported due to the 12-bit width of the FIFO. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 60 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.15 (0X15) RANGE AND RESOLUTION CONTROL REGISTER (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 61 / 84 Rev.1.1 Apr. 2018 7.16 (0X16) FIFO CONTROL REGISTER This register selects the FIFO threshold level, operation mode, FIFO reset and enable. With the exception of FIFO_RESET, the FIFO_EN bit must be ‘1’ for any FIFO interrupts, thresholds, or modes to be enabled. The FIFO flags in register 0x08 will continue to report FIFO defaults even if the FIFO_EN is ‘0’. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 62 / 84 Rev.1.1 Apr. 2018 7.17 (0X17) INTERRUPT CONTROL REGISTER Confidential 3-axis Accelerometer HSACTD003A 63 / 84 Rev.1.1 Apr. 2018 7.17 (0X17) INTERRUPT CONTROL REGISTER (Continue) Confidential 3-axis Accelerometer HSACTD003A 64 / 84 Rev.1.1 Apr. 2018 7.18 (0X1A) INITIALIZATION REGISTER 3 Software must write a fixed value to this register immediately after power-up or reset. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 65 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.19 (0X1B) SCRATCHPAD REGISTER This register can store any 8-bit value and has no effect on hardware. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 111 67548293 3-axis Accelerometer HSACTD003A 66 / 84 Rev.1.1 Apr. 2018 7.20 (0X1C) POWER MODE CONTROL REGISTER This register selects the power setting for CWAKE, SWAKE and SNIFF modes. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 67 / 84 Rev.1.1 Apr. 2018 7.20 (0X1C) POWER MODE CONTROL REGISTER (Continue) Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 68 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.21 (0X20) DRIVE MOTION X REGISTER This register controls the test mode which moves the sensor in the X axis direction and initializes specific hardware bits. NOTE: Software must always write 0 to bits [7:4] and 1. NOTE: Software must always write 1 to bit 0. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 69 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.22 (0X21) DRIVE MOTION Y REGISTER This register controls the test mode which moves the sensor in the Y axis direction and initializes specific hardware NOTE: Software must always write 0 to bits [6:4] and [1:0]. NOTE: Software must always write 1 to bit 7 after writing to register 0x20[0]. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 70 / 84 Rev.1.1 Apr. 2018 HSACTD003A 7.23 (0X22) DRIVE MOTION Z REGISTER This register controls the test mode which moves the sensor in the Z axis direction. NOTE: Software must always write 0 to bits [7:4] and [1:0]. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 71 / 84 Rev.1.1 Apr. 2018 7.24 (0X24) RESET REGISTER This register can be used to reset the device. Anytime there is a reset to the device, a POR event, or a power cycle the SPI 3-wire configuration will reset to 4wire mode. (／) (／) Confidential ALPS ELECTRIC CO.,LTD. 11 10 67548293 3-axis Accelerometer HSACTD003A 72 / 84 Rev.1.1 Apr. 2018 7.25 (0X28) INITIALIZATION REGISTER 2 Software must write a fixed value to this register immediately after power-up or reset. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 73 / 84 Rev.1.1 Apr. 2018 7.26 (0X29) TRIGGER COUNT REGISTER This register selects the number of samples to be taken after the one-shot trigger is started. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 74 / 84 Rev.1.1 Apr. 2018 7.27 (0X2A – 0X2B) X-AXIS OFFSET REGISTERS This register contains a signed 2’s complement 15-bit value applied as an offset adjustment to the output of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software. NOTE: When modifying these registers with new gain or offset values, software should perform a read-modify-write type of access to ensure that unrelated bits do not get changed inadvertently. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 75 / 84 Rev.1.1 Apr. 2018 7.28 (0X2C – 0X2D) Y-AXIS OFFSET REGISTERS This register contains a signed 2’s complement 15-bit value applied as an offset adjustment to the output of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software. NOTE: When modifying these registers with new gain or offset values, software should perform a read-modify-write type of access to ensure that unrelated bits do not get changed inadvertently. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 76 / 84 Rev.1.1 Apr. 2018 7.29 (0X2E – 0X2F) Z-AXIS OFFSET REGISTERS This register contains a signed 2’s complement 15-bit value applied as an offset adjustment to the output of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software. NOTE: When modifying these registers with new gain or offset values, software should perform a read-modify-write type of access to ensure that unrelated bits do not get changed inadvertently. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 77 / 84 Rev.1.1 Apr. 2018 7.30 (0X2B & 0X30) X-AXIS GAIN REGISTERS The gain value is an unsigned 9-bit number. NOTE: When modifying these registers with new gain or offset values, software should perform a read-modify-write type of access to ensure that unrelated bits do not get changed inadvertently. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 78 / 84 Rev.1.1 Apr. 2018 7.31 (0X2D & 0X31) Y-AXIS GAIN REGISTERS The gain value is an unsigned 9-bit number. NOTE: When modifying these registers with new gain or offset values, software should perform a read-modify-write type of access to ensure that unrelated bits do not get changed inadvertently. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 79 / 84 Rev.1.1 Apr. 2018 7.32 (0X2F & 0X32) Z-AXIS GAIN REGISTERS The gain value is an unsigned 9-bit number. NOTE: When modifying these registers with new gain or offset values, software should perform a read-modify-write type of access to ensure that unrelated bits do not get changed inadvertently. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 80 / 84 Rev.1.1 Apr. 2018 8 INDEX OF TABLES Table 1. Order Information ..................................................................................................................... 5 5 Table 2. Pin Description ......................................................................................................................... 9 9 Table 3. Absolute Maximum Ratings .................................................................................................... 15 15 Table 4. Sensor Characteristics ........................................................................................................... 16 16 Table 5. Electrical Characteristics – Voltage and Current .................................................................... 17 17 Table 6. Electrical Characteristics – Interface ...................................................................................... 18 18 Table 7. I2C Timing Characteristics ..................................................................................................... 19 19 Table 8. SPI Interface Timing Parameters ........................................................................................... 20 20 Table 9. Recommended Initialization Sequence .................................................................................. 21 21 Table 10. Operational Modes ............................................................................................................... 23 23 Table 11. I2C Address Selection .......................................................................................................... 25 25 Table 12. Register Summary ............................................................................................................... 33 33 Table 13. Extended Status Register 1 Settings .................................................................................... 34 34 Table 14. Extended Status Register 2 Settings .................................................................................... 35 35 Table 15. XOUT, YOUT, ZOUT Data Output Registers ........................................................................ 36 36 Table 16. Status Register 1 Settings .................................................................................................... 38 38 Table 17. Status Register 2 Settings .................................................................................................... 40 40 Table 18. Feature Register 1 Settings .................................................................................................. 42 42 Table 19. Feature Register 2 Settings .................................................................................................. 45 45 Table 20. Initialization Register 1 Settings ........................................................................................... 46 46 Table 21. Mode Control Register Settings ............................................................................................ 48 48 Table 22. Rate Register 1 Settings ...................................................................................................... 49 49 Table 23. Setup Steps for CWAKE Using “Rate 15” ............................................................................. 50 50 Table 24. Sniff Control Register Settings ............................................................................................. 52 52 Table 25. Setup Steps For Sniff Using “Rate 15” ................................................................................. 53 53 Table 26. Sniff Threshold Control Register Settings ............................................................................. 56 56 Table 27. Sniff Configuration Register Settings .................................................................................... 58 58 Table 28. Range and Resolution Control Register Settings ................................................................. 60 60 Table 29. FIFO Control Register Settings ............................................................................................ 61 61 Table 30. Interrupt Control Register Settings ....................................................................................... 63 63 Table 31. Initialization Register 3 Settings ........................................................................................... 64 64 Table 32. Scratchpad Register ............................................................................................................. 65 65 Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 81 / 84 Rev.1.1 Apr. 2018 8 INDEX OF TABLES (Continue) Table 33. Power Mode Control Register Settings ................................................................................. 67 67 Table 34. Drive Motion X Register Settings .......................................................................................... 68 68 Table 35. Register 0x21 Read-Back Value .......................................................................................... 69 69 Table 36. Drive Motion Y Register Settings .......................................................................................... 69 69 Table 37. Drive Motion Z Register Settings .......................................................................................... 70 70 Table 38. Reset Register Settings ....................................................................................................... 71 71 Table 39. Initialization Register 2 Settings ........................................................................................... 72 72 Table 40. Trigger Register Settings ...................................................................................................... 73 73 Table 41. X-Axis Offset Registers ........................................................................................................ 74 74 Table 42. Y-Axis Offset Registers ........................................................................................................ 75 75 Table 43. Z-Axis Offset Registers ........................................................................................................ 73 76 Table 44. X-Axis Gain Registers .......................................................................................................... 77 77 Table 45. Y-Axis Gain Registers .......................................................................................................... 78 78 Table 46. Z-Axis Gain Registers .......................................................................................................... 79 79 Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 82 / 84 Rev.1.1 Apr. 2018 9 Revision History Revision Date 1.0 13.Nov. 2017 1.1 4.Apr. 2018 Page 4,84 Note First edition Add 11. Asking that use this product Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer HSACTD003A 83 / 84 Rev.1.1 Apr. 2018 10 LEGAL 1. ALPS reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and to this document at any time and discontinue any product without notice. The information contained in this document has been carefully checked and is believed to be accurate. However, ALPS shall assume no responsibilities for inaccuracies and make no commitment to update or to keep current the information contained in this document. 2. ALPS products are designed only for commercial and normal industrial applications and are not suitable for other purposes, such as: medical life support equipment; nuclear facilities; critical care equipment; military / aerospace; automotive; security or any other applications, the failure of which could lead to death, personal injury or environmental or property damage. Use of the products in unsuitable applications are at the customer’s own risk and expense. 3. ALPS shall assume no liability for incidental, consequential or special damages or injury that may result from misapplication or improper use of operation of the product. 4. No license, express or implied, by estoppel or otherwise, to any intellectual property rights of ALPS or any third party is granted under this document. 5. ALPS makes no warranty or representation of non-infringement of intellectual property rights of any third party with respect to the products. ALPS specifically excludes any liability to the customers or any third party regarding infringement of any intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party, relating to any combination, machine, or process in which the ALPS products are used. 6. Examples of use described herein are provided solely to guide use of ALPS products and merely indicate targeted characteristics, performance and applications of products. ALPS shall assume no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 7. Information described in this document including parameters, application circuits and its constants and calculation formulas, programs and control procedures are provided for the purpose of explaining typical operation and usage. “Typical” parameters that may be provided in ALPS data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals,” must be validated for each customer application by customer’s technical experts. In no event shall the information described be regarded as a guarantee of conditions or characteristics of the products. Therefore, the customer should evaluate the design sufficiently as whole system under the consideration of various external or environmental conditions and determine their application at the customer’s own risk. ALPS shall assume no responsibility or liability for claims, damages, costs and expenses caused by the customer or any third party, owing to the use of the above information. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293 3-axis Accelerometer 84 / 84 Rev.1.1 Apr. 2018 HSACTD003A 11. Asking that use this product １． For the export of products which are controlled items subject to foreign and domestic export laws and regulations, you must obtain approval and/or follow the formalities of such laws and regulations. ２． Products must not be used for military and/or antisocial purposes such as terrorism, and shall not be supplied to any party intending to use the products for such purposes. ３． Unless provided otherwise, the products have been designed and manufactured for application to equipment and devices which are sold to end-users in the market, such as AV (audio visual) equipment, home electric equipment, office and commercial electronic equipment, information and communication equipment or amusement equipment. The products are not intended for use in, and must not be used for, any application of nuclear equipment, driving control equipment for aerospace or any other unauthorized use. With the exception of the above mentioned banned applications, for applications involving high levels of safety and liability such as medical equipment, burglar alarm equipment, disaster prevention equipment and undersea equipment, please contact an Alps sales representative and/or evaluate the total system on the applicability. Also, implement a fail-safe design, protection circuit, redundant circuit, malfunction protection and/or fire protection into the complete system for safety and reliability of the total system. ４． Before using products which were not specifically designed for use in automotive applications, please contact an Alps sales representative. ５． The actual performance may vary under any special or extraordinary environments or conditions where excessive distortion or mechanical stress is applied on the products. ex) Sealing or coating the products with resin or other coating materials. The strucure in which the printed circuit board is under excessive distortion. ６． Mechanical sensor are designed to handle high-g shock events, but direct mechanical shock to the package will generate high g forces and should be avoided. SMT assembly houses should use automated assembly equipment with either plastic nozzles or nozzles with compliant (soft i.e. rubber or silicone) tips. ７． Recommendations for assembly : ・ Do not use metal or ceramic nozzle tips during assembly. - These cause excessive g forces and therefore are NOT recommended. ・ Place the sensor with minimal direct force during assembly. - This is achieved by optimizing the placement force control in the g-sensor library for chip shooters or IC placers. ・ Place the sensor with minimum pick and place assembly speeds. - This is achieved by optimizing the speed settings control in the g-sensor library for chip shooters or IC placers. ・ Discard mishandled sensors. - If the sensor is dropped from a height of 50mm or greater it should be discarded and not used. - Direct impact to a hard surface can also generate high g forces. The best practice is to discard any part that has been dropped. ・ Handle partially finished PCB assemblies carefully. - Transport assemblies in shock-absorbent carriers. - Do NOT expose partial assemblies to bending, flexing or excessive shocks during product assembly. ８． Ultrasonic cleaning of the PCB assembly is not recommended to avoid damaging the product. Confidential ALPS ELECTRIC CO.,LTD. (／) (／) 11 10 67548293