AS4C128M16D2-25BINTR

AS4C128M16D2 Revision History AS4C128M16D2- 84-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amended page 74 corrected package dimensions "F" to be " E " and "SF" to be " SE Date March 2014 October 2014 Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Confidential 0 Version 2.0 – October/2014 AS4C128M16D2 128M x 16 bit DDRII Synchronous DRAM (SDRAM) Advanced (Rev. 2.0, October. /2014) Confidential Features - Description High speed data transfer rates with system frequency up to 400 MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4 ,5 , 6 and 7 Programmable Additive Latency: 0, 1, 2, 3 , 4, 5 and 6 Write Latency = Read Latency -1 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 4 and 8 Automatic and Controlled Precharge Command Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase between 0°C and 85°C ODT (On-Die Termination) Weak Strength Data-Output Driver Option Bidirectional differential Data Strobe (Single-ended data-strobe is an optional feature) On-Chip DLL aligns DQ and DQs transitions with CK transitions DQS can be disabled for single-ended data strobe Differential clock inputs CK and CK JEDEC Power Supply 1.8V ± 0.1V VDDQ =1.8V ± 0.1V Available in 84-ball FBGA RoHS compliant PASR Partial Array Self Refresh tRAS lockout supported The AS4C128M16D2 is an eight bank DDR DRAM organized as 8 banks x 16Mbit x 16. The AS4C128M16D2 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is designed to comply with the following key DDR2 SDRAM features:(1) posted CAS with additive latency, (2) write latency = read latency-1, (3) On Die Termination. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchronized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Table 1. Ordering Information Part Number AS4C128M16D2-25BCN AS4C128M16D2-25BIN Clock Frequency 400MHz 400MHz Data Rate 800Mbps/pin 800Mbps/pin Power Supply VDD 1.8V, VDDQ 1.8V VDD 1.8V, VDDQ 1.8V Package 84 ball FBGA 84 ball FBGA B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package C: indicates commercial temperature I: indicates industrial temperature N: indicates Pb and Halogen Free ROHS Table 2. Speed Grade Information Speed Grade DDR2-800 Confidential Clock Frequency CAS Latency 400 MHz 5 1 tRCD (ns) tRP (ns) 5 5 Version 2.0 – October/2014 AS4C128M16D2 2Gb DDR2 SDRAM Addressing Configuration 128Mb x 16 # of Bank 8 Bank Address Confidential BA0 ~ BA2 Auto precharge A10/AP Row Address A0 ~ A13 Column Address A0 ~ A9 2 Version 2.0 – Oct/2014 AS4C128M16D2 Confidential 3 Version 2.0 – October/2014 AS4C128M16D2 Confidential 4 Version 2.0 – Oct/2014 AS4C128M16D2 Simplified State Diagram Initialization Sequence CKEL OCD calibration Self Refreshing SRF CKEH PR Setting MRS EMRS Idle MRS REF All banks precharged Refreshing CKEL ACT CKEL CKEH Precharge Power Down Activating CKEL CKEL CKEL Automatic Sequence Active Power Down Command Sequence CKEH CKEL Bank Active Read Write Write Read WRA Writing RDA Read Write Reading RDA WRA RDA Writing with Autoprecharge PR, PRA PR, PRA PR, PRA Reading with Autoprecharge CKEL = CKE low, enter Power Down CKEH = CKE high, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh Precharging Note: Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured in full detail. Confidential 5 Version 2.0 – Oct/2014 AS4C128M16D2 Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A13 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Power up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95V max, AND - Vref tracks VDDQ/2. or - Apply VDD before or at the same time as VDDL. - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200us after stable power and clock (CK, CK), then apply NOP or deselect & take CKE high. 4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.) 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and A12.) 8. Issue a Mode Register Set command for “DLL reset”. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL. 12. At least 200 clocks after step 8, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS. 13. The DDR2 SDRAM is now ready for normal operation. Confidential 6 Version 2.0 – Oct/2014 AS4C128M16D2 *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Initialization Sequence after Power Up Programming the Mode Register For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, single-ended strobe and ODT (On Die Termination) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers (EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means initialization including those can be executed any time after power-up without affecting array contents. Confidential 7 Version 2.0 – Oct/2014 AS4C128M16D2 Confidential 8 Version 2.0 – Oct/2014 AS4C128M16D2 DDR2 SDRAM Extended Mode Register Set EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. Extended mode register(1) is written by asserting low on CS, RAS, CAS, WE and high on BA0 and low on BA1, and controlling rest of pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling reduced strength data-output drive. A3~A5 determines the additive latency. A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Confidential 9 Version 2.0 – Oct/2014 AS4C128M16D2 EMRS(1) Programming BA2 0 A15*1~A13 BA1 BA0 0 0*1 1 A12 A11 A10 Qoff RDQS DQS A7 A6 A5 Rtt OCD program A4 A3 Additive latency A1 A0 Rtt D.I.C DLL Rtt (NOMINAL) MRS 0 0 ODT Disable A0 0 1 75 ohm 0 Enable 1 0 1 Disable 1 1 150 ohm 50 ohm 0 0 1 EMRS(1) 1 0 EMRS(2) 1 1 EMRS(3):Reserved A5 A4 A3 0 OCD exit 0 0 0 0 0 1 Reserved 0 0 1 1 1 0 Reserved 0 1 0 2 0 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Reserved A8 A7 0 0 0 0 1 1 1 Enable OCD defaults * : After setting to default, OCD mode needs to be exited by setting A9-A7 to 000. Qoff (Optional) * 0 Output buffer enabled A1 1 Output buffer disabled 0 * : Outputs disabled - DQs, DQSs, DQSs, DQSs, 1 RDQS, RDQS. This feature is used in conjunction with dimm IDD measurements when IDDQ is not desired to be included. Additive Latency Output Driver Impendence Control Normal Weak Driver Size 100% 60% DQS 0 Enable 1 Disable A11 RDQS Enable 0 Disable 1 Enable * DLL En able OCD operation A9 A10 Extended Mode Register A2 0 A12 Address Field A2 A6 BA0 * A8 MRS mode BA1 1 A9 If RDQS is enabled, the D M Function is disabled. RDQS is active for reads and don’t care for writes. A11 (RDQS Enable) A10 (DQS Enable) 0 (Disable) 0 (Enable) 0 (Disable) Strobe Function Matrix RDQS DQS DQS DM Hi-z DQS DQS 1 (Disable) DM Hi-z DQS Hi-z 1 (Enable) 0 (Enable) RDQS RDQS DQS DQS 1 (Enable) 1 (Disable) RDQS Hi-z DQS Hi-z RDQS/DM *1 : A14 and A15 is reserved for future usage. Confidential 10 Version 2.0 – Oct/2014 AS4C128M16D2 EMRS(2) Programming*¹: PASR BA2 BA1 BA0 A15 *2 ~ A13 0 1 0 A12 A11 A10 A9 0 *2 A8 A7 A6 A5 A4 A3 A2 0*1 A1 A0 Extended Mode Register(2) PASR A7 High Temperature Self Refresh rate enable 0 Commercial temperature default 1 Industrial temperature option: use if Tc exceeds 85 oC Address Field *1 : BA0 , BA1, and BA2 must be programmed to 0 when setting the mode register during initialization. *2 : A14 and A15 is reserved for future usage. O *3 : While Tc > 85 C, Double refresh rate (tREFI: 3.9us) is required, and to enter self refresh mode at this temperature range it must be required an EMRS command to change itself refresh rate. The PASR bits allows the user to dynamically customize the memory array size to the actual needs. This feature allows the device to reduce standby current by refreshing only the memory arrays that contain essential data. The refresh options are full array, one-half array, one-quarter array, three-fourth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. Please see the following table. P ASR[2] P ASR[1] 0 0 0 0 1 1 1 1 P ASR[0] 0 0 1 1 0 0 1 1 ACTIVE SECTION 0 1 0 1 0 1 0 1 Full array 1/2 array (Banks 0,1, 2, 3) 1/4 array (Bank 0, 1) 1/8 array (Bank 0) 3/4 array (Banks 2,3,4,5,6,7) 1/2 array (Banks 4, 5, 6, 7) 1/4 array (Bank 6,7) 1/8 array (Bank 7) EMRS(3) Programming: Reserved*1 BA2 0 BA1 BA0 A15 *2 ~ A13 1 1 0 *2 A12 A11 A10 A9 A8 A7 0*1 A6 A5 A4 A3 A2 A1 A0 Address Field Extended Mode Register(3) *1 : EMRS(3) is reserved for future use and all bits except BA0, BA1, BA2 must be programmed to 0 when setting the mode register during initialization. *2 : A14 and A15 is reserved for future usage. Confidential 11 Version 2.0 – Oct/2014 AS4C128M16D2 On-Die Termination (ODT) On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, UDQS/UDQS, LDQS/LDQS, UDM and LDM via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes. ODT is turned off and not supported in SELF REFRESH mode. VDDQ VDDQ sw1 sw2 VDDQ sw3 Rval3 Rval2 Rval1 DRAM Input Buffer Input Pin Rval1 sw1 VSSQ Rval3 Rval2 sw2 VSSQ sw3 VSSQ Switch (sw1, sw2, sw3) is enabled by ODT pin. Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR. Termination included on all DQs, UDQS/UDQS, LDQS/LDQS, UDM and LDM pins. Functional representation of ODT Confidential 12 Version 2.0 – Oct/2014 AS4C128M16D2 ODT Truth Table The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10and A11 in the EMRS. To activate termination of any of these pins, the ODT function has to be enabled in the EMRS by address bits A6 and A2. X=Don’t Care 0=Signal Low 1=Signal High Confidential 13 Version 2.0 – Oct/2014 AS4C128M16D2 DC Electrical Characteristics and Operation Conditions : Parameter / Condition Symbol min. nom. max. Units Notes Rtt eff. impedance value for EMRS(A6,A2)= 0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1 Rtt eff. impedance value for EMRS(A6,A2)= 1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1 Rtt eff. impedance value for EMRS(A6,A2)= 1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1 delta VM -6 +6 % 2 Deviation of VM with respect to VDDQ/2 1) Measurement Definition for Rtt(eff) : Apply VIHac and VILac to test pin separately, then measure current I(VIHac) and I(VILac) respectively Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac)) 2) Measurement Definition for VM : Measure voltage (VM) at test pin (midpoint) with no load: delta VM = (( 2* VM / VDDQ) - 1 ) x 100% AC Electrical Characteristics and Operation Conditions : Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Mode) max. Units 2 2 tCK Notes tAC(min) tAC(max) + 0.7 ns 1 tAC(min) + 2 2 tCK + tAC(max) + 1 ns 3 ODT turn-off delay 2.5 ODT turn-off ODT turn-off (Power-Down Mode) min. tCK 2.5 tAC(min) tAC(max) + 0.6 ns 2 tAC(min) + 2 2.5 tCK + tAC(max) + 1 ns 3 tCK 4 tCK 4 tANPD ODT to Power Down Mode Entry Latency 3 tAXPD ODT Power Down Exit Latency 8 X 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. is when the ODT resistance is fully on. Both are measured from tAOND. 2) ODT turn off time min. is when the device stars to turn-off ODT resistance. ODT turn off time max. is when the bus is in high impedance. Both are measured from tAOFD. 3) For Standard Active Power-down - with MRS A12 =”0” - the non-power-down timings ( tAOND, tAON, tAOFD and tAOF ) apply 4) tANPD and tAXPD define the timing limit when either Power Down Mode Timings (tAONPD, tAOFPD) or Non-Power Down Mode timings (tAOND, tAOFD) have to be applied. Confidential 14 Version 2.0 – Oct/2014 AS4C128M16D2 ODT Timing for Active / Standby (Idle) Mode and Standard Active Power-Down Mode T-n T-5 T-6 T-4 T-3 T-2 T-1 T0 CK, CK tIS CKE tIS tAXPD tIS tIS ODT tANPD tAOND tAOFD Rtt tAON(min) DQ tAOF(min) tAOF(max) tAON(max) ODT1 1) Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down Mode timings have to be applied. 2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND. 3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance. ODT turn off time max. (tAOF,max) is when the bus is in high impedance. Both are measured from tAOFD. ODT Timing for Precharge Power-Down and Lo w Power Power -Down Mode T-7 T-5 T-6 T-4 T-3 T-2 T-1 T0 T1 CK, CK CKE ODT tAXPD tIS tANPD tIS tAOFPD,min tAOFPD,max DQ tAONPD,min Rtt tAONPD,max ODT2 1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to be applied. Confidential 15 Version 2.0 – Oct/2014 AS4C128M16D2 Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses of BA0-BA2 are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If an R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0,1,2,3,4,5 and 6 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2 Confidential 16 Version 2.0 – Oct/2014 AS4C128M16D2 Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation ( WE high ) or a write operation ( WE low ). The DDR2 SDRAM pro- vides a wide variety of fast access modes. The boundary of the burst cycle is restricted to specific segments of the page length. For example, the 16Mbit x 16 I/O x 8 Bank chip has a page length of 1024 bits ( defined by CA0-CA9 ). In case of a 4-bit burst operation ( burst length = 4 ) the page length of 1024 bits is divided into 256 uniquely addressable segments ( 4-bits x 16 I/O each ). The 4-bit burst operation will occur entirely within one of the 256 segments ( defined by CA0-CA7 ) beginning with the column address supplied to the device during the Read or Write Command ( CA0-CA9 ). The second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. In case of an 8-bit burst operation ( burst length = 8 ) the page length of 1024 bits is divided into 128 uniquely addressable double segments ( 8-bits x 16 I/O each ). The 8-bit burst operation will occur entirely within one of the 128 double segments ( defined by CA0-CA6 ) beginning with the column address supplied to the deivce during the Read or Write Command ( CA0-CA9 ). A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. For 8 bit burst operation ( BL = 8 ) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. Burst interruption is allowed with 8 bit burst operation. For details see the “Burst Interrupt” - Section of this datasheet. Read Burst Timing Example : (CL = 3, AL = 0, RL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T12 CK, CK CMD READ A NOP tCCD READ B NOP NOP READ C NOP NOP NOP NOP tCCD DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout C0 Dout C1 Dout C2 Dout C3 RB Confidential 17 Version 2.0 – Oct/2014 AS4C128M16D2 Posted CAS Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 -1 0 2 1 3 4 5 6 7 8 9 10 11 12 CK, CK Activate Bank A CMD Read Bank A Write Bank A AL = 2 DQS, DQS WL = RL -1 = 4 CL = 3 tRCD RL = AL + CL = 5 DQ Din0 Din1 Din2 Din3 Dout0 Dout1Dout2Dout3 " tRAC" PostCAS1 Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8 0 2 1 3 4 5 6 7 8 9 10 11 12 CK, CK CMD DQS, DQS Activate Read Bank A Bank A Write Bank A WL = RL -1 = 4 CL = 3 AL = 2 tRCD RL = AL + CL = 5 DQ Dout0 Dout1 Dout2 Dout3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tRAC" PostCAS3 Confidential 18 Version 2.0 – Oct/2014 AS4C128M16D2 Read followed by a write to the same bank, Activate to Read delay > tRCDmin: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK CMD Read Bank A Activate Bank A Write Bank A tRCD>tRCDmin. WL = 3 DQS, DQS RL = 4 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 "tRAC" PostCAS5 Confidential 19 Version 2.0 – Oct/2014 AS4C128M16D2 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the “Burst Interruption” section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length Starting Address ( A2 A1 A0 ) Sequential Addressing (decimal) Interleave Addressing (decimal) x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 4 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 8 Note: 1) Page length is a function of I/O organization and column addressing. 2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR components. Confidential 20 Version 2.0 – Oct/2014 AS4C128M16D2 Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each sub- sequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS). Basic Burst Read Timing tCH tCL CK CK, CK CK DQS DQS, DQS DQS tRPST tRPRE DO DQ DO DO DO tDQSQmax t QH tDQSQmax don’t care tQH Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS REA D A NOP NOP NOP NOP NOP NOP NOP NOP