AS4C16M16D1A-5TIN

16Mx16 DDR1-AS4C16M16D1A Revision History AS4C16M16D1A - 66-pin TSOPII PACKAGE Revision Details Date Rev 1.1 Rev 1.2 Preliminary datasheet Production Released July 2015 Aug 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 64 - Rev.1.2 August 2015 16Mx16 DDR1-AS4C16M16D1A Overview Features • Fast clock rate: 200MHz • Differential Clock CK & CK • Bi-directional DQS • DLL enable/disable by EMRS • Fully synchronous operation • Internal pipeline architecture • Four internal banks, 4M x 16-bit for each bank • Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved • Individual byte write mask control • DM Write Latency = 0 • Auto Refresh and Self Refresh • 8192 refresh cycles / 64ms • Precharge & active power down • Power supplies: VDD & VDDQ = 2.5V ± 0.2V • Interface: SSTL_2 I/O Interface • Operating Temperature: - Commercial (0°C~70°C) - Industrial (-40°C~85°C) The AS4C16M16D1 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 256 Mbits. It is internally configured as a quad 4M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK .d Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C16M16D1 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, AS4C16M16D1 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory band-width, result in a device particularly well suited to high performance main memory and graphics applications. • Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb free and Halogen free Table 1. Ordering Information Product part No Clock Temperature Data Rate Package AS4C16M16D1A-5TCN 200MHz Commercial 0°C to 70°C 400Mbps/pin 66pin TSOPII AS4C16M16D1A-5TIN 200MHz Industrial -40°C to 85°C 400Mbps/pin 66pin TSOPII Confidential - 2 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Figure 1. Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD Confidential 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS - 3 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Figure 2. Block Diagram CK CK DLL CLOCK BUFFER COMMAND DECODER COLUMN COUNTER A10/AP CONTROL SIGNAL GENERATOR MODE REGISTER 4M x 16 CELL ARRAY (BANK #1) Column Decoder ~ A9 A11 A12 BA0 BA1 Row Decoder ADDRESS BUFFER A0 REFRESH COUNTER DATA STROBE BUFFER LDQS UDQS DQ0 4M x 16 CELL ARRAY (BANK #2) Column Decoder DQ Buffer Row Decoder ~ DQ15 LDM UDM Confidential 4M x 16 CELL ARRAY (BANK #0) Column Decoder Row Decoder CS RAS CAS WE Row Decoder CKE - 4 of 64 - 4M x 16 CELL ARRAY (BANK #3) Column Decoder Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Pin Descriptions Table 2. Pin Details Symbol Type Description CK, CK Input Differential Clock: CK, CK are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. Both CK and CK increment the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0, BA1 Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. A0-A12 Input Address Inputs: A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge). CS Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS Input Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. CAS Input Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGH" or “LOW”. WE Input Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. LDQS, Input / UDQS Output Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. LDM, Input UDM DQ0 - DQ15 Confidential Input / Output Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes. - 5 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A   VDD Supply Power Supply: 2.5V ± 0.2V . VSS Supply Ground VDDQ Supply DQ Power: 2.5V ± 0.2V. Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VREF Supply Reference Voltage for Inputs: +0.5*VDDQ NC - Confidential No Connect: These pins should be left unconnected. - 6 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3 shows the truth table for the operation commands. Table 3. Truth Table (Note (1), (2)) Command State CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-12 CS RAS CAS WE Idle(3) H X X V Row address L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X L L H L Write Active(3) H X X V L H L L Write and AutoPrecharge H X X V H Column address (A0 ~ A8) L Active(3) L H L L Read Active(3) H X X V L H L H Read and Autoprecharge H X X V H Column address (A0 ~ A8) L Active(3) L H L H Mode Register Set Idle H X X OP code L L L L Extended MRS Idle H X X OP code L L L L No-Operation Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V H X X X L H H H X X X X X X X BankActivate Burst Stop (SelfRefresh) Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit Data Input Mask Disable Idle Any H L L X H X X X X X X X (PowerDown) Active Any H L L X H X X X X X X X (PowerDown) Active H X L X X X Data Input Mask Enable(5) Active H X H X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 2, 4, and 8 burst operation. 5. LDM and UDM can be enabled respectively. Confidential - 7 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Mode Register Set (MRS) The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A12 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies. Table 4. Mode Register Bitmap BA1 BA0 A12 0 A8 0 1 X 0 A11 A9 RFU must be set to “0” A7 Test Mode 0 Normal mode 0 DLL Reset 1 Test mode BA0 Mode 0 MRS 1 EMRS A10 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A8 A7 A6 T.M. A5 A4 A3 CAS Latency A4 CAS Latency Reserved 0 Reserved 1 2 0 1 3 0 Reserved 1 Reserved 0 2.5 1 Reserved A2 BT A3 Burst Type 0 Sequential 1 Interleave A1 A0 Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Address Field Mode Register A0 Burst Length 0 Reserved 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Reserved • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8. Table 5. Burst Length A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Confidential - 8 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A   • Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4 and 8. Table 6. Addressing Mode A3 Addressing Mode 0 Sequential 1 Interleave • Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 7. Burst Address ordering Burst Length A2 X X X X X X 0 0 0 0 1 1 1 1 2 4 8 Start Address A1 X X 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sequential Interleave 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 • CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ≤ CAS Latency X tCK Table 8. CAS Latency A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 clocks 1 1 1 Reserved Confidential - 9 of 64 - Rev.1.2 August 2015     • 16Mx16 DDR1-AS4C16M16D1A Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table 9. Test Mode A8 A7 Test Mode 0 0 Normal mode 1 0 DLL Reset • (BA0, BA1) Table 10. MRS/EMRS BA1 BA0 A12 ~ A0 RFU 0 MRS Cycle RFU 1 Extended Functions (EMRS) Confidential - 10 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Extended Mode Register Set (EMRS) The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE . The state of A0 ~ A12, BA0 and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). A1 is used for setting driver strength to normal, or weak. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes. Table 11. Extended Mode Register Bitmap BA1 BA0 A12 A11 A10 0 1 A9 A8 A7 RFU must be set to “0” BA0 0 Mode MRS A6 0 A1 0 Drive Strength Full 1 EMRS 0 1 Weak 1 0 1 1 Confidential A6 A5 A4 A3 A2 A1 A0 Address Field DS1 RFU must be set to “0” DS0 DLL Extended Mode Register Comment A0 0 DLL Enable 1 Disable RFU Reserved For Future Matched impedance Output driver matches impedance - 11 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Table 12. Absolute Maximum Rating Symbol Item Rating Unit VIN, VOUT Input, Output Voltage - 0.5~ VDDQ + 0.5 V VDD, VDDQ Power Supply Voltage - 1~3.6 V Commercial 0~70 °C Industrial -40~85 °C TA Ambient Temperature TSTG Storage Temperature -55~150 °C TSOLDER Soldering Temperature 260 °C PD Power Dissipation 1 W IOS Short Circuit Output Current 50 mA Note1: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Note2: These voltages are relative to Vss Table 13. Recommended D.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Symbol Parameter Min. Max. Unit Note VDD Power Supply Voltage 2.3 2.7 V VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.7 V VREF Input Reference Voltage 0.49*VDDQ 0.51* VDDQ V VIH (DC) Input High Voltage (DC) VREF + 0.15 VDDQ + 0.3 V VIL (DC) Input Low Voltage (DC) -0.3 VREF – 0.15 V VTT Termination Voltage VREF - 0.04 VREF + 0.04 V VIN (DC) Input Voltage Level, CK and CK inputs -0.3 VDDQ + 0.3 V VID (DC) Input Different Voltage, CK and CK inputs 0.36 VDDQ + 0.6 V II Input leakage current -2 2 µA IOZ Output leakage current -5 5 µA IOH Output High Current -16.2 - mA VOH = 1.95V IOL Output Low Current Note: All voltages are referenced to VSS. 16.2 - mA VOL = 0.35V Min. Max. Unit Table 14. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 °C) Symbol Parameter CIN1 Input Capacitance (CK, CK ) 2 3 pF CIN2 Input Capacitance (All other input-only pins) 2 3 pF CI/O DQ, DQS, DM Input/Output Capacitance 4 5 pF Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested Confidential - 12 of 64 - Rev.1.2 August 2015    16Mx16 DDR1-AS4C16M16D1A  Table 15. D.C. Characteristics (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Parameter & Test Condition Symbol OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT : One bank; Active-ReadPrecharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE=LOW PRECHARGE FLOATING STANDBY CURRENT: CKE = HIGH; CS =HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM PRECHARGE QUIET STANDBY CURRENT: CKE = HIGH; CS =HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and other control input stadle at HIGH or LOW; VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-down mode; CKE=LOW; tCK=tCK(min) ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Sell Refresh Mode ; CKE≦ 0.2V;tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputs change only during Active, READ , or WRITE command Confidential - 13 of 64 - -5 Unit Note Max. IDD0 65 mA IDD1 70 mA IDD2P 5 mA IDD2F 30 mA IDD2Q 20 mA IDD3P 20 mA IDD3N 55 mA IDD4R 100 mA IDD4W 100 mA IDD5 100 mA IDD6 2 mA IDD7 140 mA Rev.1.2 1 August 2015    16Mx16 DDR1-AS4C16M16D1A  Table 16. Electrical Characteristics and Recommended A.C.Operating Condition (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Symbol -5 Parameter CL = 2 CL = 2.5 CL = 3 Min. 7.5 6 5 0.45 0.45 tCLMIN or tCHMIN Max. 12 12 10 0.55 0.55 - Unit Note ns ns ns tCK tCK ns 2 tCK Clock cycle time tCH tCL tHP Clock high level width Clock low level width Clock half period tHZ Data-out-high impedance time from CK, CK - 0.7 ns 3 tLZ Data-out-low impedance time from CK, CK -0.7 0.7 ns 3 -0.6 0.6 ns -0.7 0.7 ns 0.9 0.4 0.72 0 0.25 0.4 0.35 0.35 0.7 0.7 0.4 0.4 tHP - tQHS 55 70 40 15 15 10 15 2 10 200 75 tWR + tRP 1.75 2.2 0.2 0.2 0.4 1.1 0.6 1.25 0.6 70k 7.8 0.5 - ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK ns µs tCK ns ns ns ns ns tCK tCK tDQSCK DQS-out access time from CK, CK tAC Output access time from CK, CK tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tWPST tDQSH tDQSL tIS tIH tDS tDH tQH tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tMRD tREFI tXSRD tXSNR tDAL tDIPW tIPW tQHS tDSS tDSH DQS-DQ Skew Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS write preamble DQS write postamble DQS in high level pulse width DQS in low level pulse width Address and Control input setup time Address and Control input hold time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ/DQS output hold time from DQS Row cycle time Refresh row cycle time Row active time Active to Read or Write delay Row precharge time Row active to Row active delay Write recovery time Internal Write to Read Command Delay Mode register set cycle time Average Periodic Refresh interval Self refresh exit to read command delay Self refresh exit to non-read command delay Auto Precharge write recovery + precharge time DQ and DM input puls width Control and Address input pulse width Data Hold Skew Factor DQS falling edge to CK setup time DQS falling edge hold time from CK Confidential - 14 of 64 - Rev.1.2 4 5 6 6 7 August 2015    16Mx16 DDR1-AS4C16M16D1A  Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Symbol Parameter Min. Max. Unit VIH (AC) Input High Voltage (AC) VREF + 0.31 - V VIL (AC) Input Low Voltage (AC) - VREF – 0.31 V 0.7 VDDQ + 0.6 V 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V VID (AC) Input Different Voltage, CK and CK inputs VIX (AC) Input Crossing Point Voltage, CK and CK inputs Note: 1) Enables on-chip refresh and address counters. 2) Min(tCL, tCH) refers to the smaller of the actual clock low time and actual clock high time as provided to the device. 3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving(HZ), or begins driving(LZ). 4) The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 5) The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 6) For command/address slew rate ≧0.5V/ns and