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256M DDR2 -AS4C16M16D2 Revision History AS4ϭϲDϭϲϮ - ϴϰ-ball FBGA PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date DĂLJ201ϱ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH Confidential - 1/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 &RQILGHQWLDO 16M x 16 bit DDRII Synchronous DRAM (SDRAM) Advanced (Rev. 1.0, Ma\/201) Features ¥ -('(&6WDQGDUG&RPSOLDQW ¥ 3URJUDPPDEOH0RGH ([WHQGHG0RGHUHJLVWHUV ¥ -('(&VWDQGDUG9,2667/BFRPSDWLEOH ¥ 3RVWHG&$6DGGLWLYHODWHQF\$/ ¥ 3RZHUVXSSOLHV9'' 9''4 9±9 ¥ :5,7(ODWHQF\ 5($'ODWHQF\W&. ¥ 2SHUDWLQJWHPSHUDWXUH &RPPHUFLDO°Ca°C ,QGXVWULDO°Ca°C ¥ %XUVWOHQJWKRU ¥ 6XSSRUWV-('(&FORFNMLWWHUVSHFLILFDWLRQ ¥ '//HQDEOHGLVDEOH ¥ )XOO\V\QFKURQRXVRSHUDWLRQ ¥ )DVWFORFNUDWH0+] ¥ 2II&KLS'ULYHU2&' ,PSHGDQFH$GMXVWPHQW $GMXVWDEOHGDWDRXWSXWGULYHVWUHQJWK ¥ 'LIIHUHQWLDO&ORFN&. &. ¥ 2QGLHWHUPLQDWLRQ2'7 ¥ %LGLUHFWLRQDOVLQJOHGLIIHUHQWLDOGDWDVWUREH '46 '46 ¥ 5R+6FRPSOLDQW ¥ LQWHUQDOEDQNVIRUFRQFXUUHQWRSHUDWLRQ ¥ ELWSUHIHWFKDUFKLWHFWXUH ¥ ,QWHUQDOSLSHOLQHDUFKLWHFWXUH ¥ 3UHFKDUJH DFWLYHSRZHUGRZQ Confidential ¥ %XUVWW\SH6HTXHQWLDO,QWHUOHDYH ¥ $XWR5HIUHVKDQG6HOI5HIUHVK ¥ UHIUHVKF\FOHVPV $YHUDJHUHIUHVKSHULRG µV#°C7&°C µV#°C7&5°C ¥ 3DFNDJHEDOO[[PPPD[)%*$ 3E)UHHDQG+DORJHQ)UHH - 2/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Overview 7KH0E''5LVDKLJKVSHHG&026'RXEOH'DWD5DWH7ZR''5V\QFKURQRXVG\QDPLFUDQGRPDFFHVV PHPRU\6'5$0FRQWDLQLQJ0ELWVLQDELWZLGHGDWD,2V,WLVLQWHUQDOO\FRQILJXUHGDVDTXDGEDQN'5$0 EDQNV[0EDGGUHVVHV[,2V 7KH GHYLFH LV GHVLJQHG WR FRPSO\ ZLWK ''5 '5$0 NH\ IHDWXUHV VXFK DV SRVWHG &$6 ZLWK DGGLWLYH ODWHQF\ :ULWHODWHQF\ 5HDGODWHQF\2II&KLS'ULYHU2&'LPSHGDQFHDGMXVWPHQWDQG2Q'LH7HUPLQDWLRQ2'7 $OORIWKHFRQWURODQGDGGUHVVLQSXWVDUHV\QFKURQL]HGZLWKDSDLURIH[WHUQDOO\VXSSOLHGGLIIHUHQWLDOFORFNV,QSXWV DUHODWFKHGDWWKHFURVVSRLQWRIGLIIHUHQWLDOFORFNV&.ULVLQJDQG&.IDOOLQJ$OO,2VDUHV\QFKURQL]HGZLWKDSDLURI ELGLUHFWLRQDO VWUREHV '46 DQG '46 LQ D VRXUFHV\QFKURQRXVIDVKLRQ7KH DGGUHVV EXV LV XVHG WRFRQYH\ URZ FROXPQDQGEDQNDGGUHVVLQIRUPDWLRQLQ5$6&$6PXOWLSOH[LQJVW\OH$FFHVVHV EHJLQZLWKWKHUHJLVWUDWLRQRID %DQN $FWLYDWH FRPPDQG DQG WKHQ LW LV IROORZHG E\ D 5HDG RU :ULWH FRPPDQG 5HDG DQG ZULWH DFFHVVHV WR WKH ''56'5$0DUHRUELWEXUVWRULHQWHGDFFHVVHVVWDUWDWDVHOHFWHGORFDWLRQDQGFRQWLQXHIRUDSURJUDPPHG QXPEHURIORFDWLRQVLQDSURJUDPPHGVHTXHQFH 2SHUDWLQJWKHIRXUPHPRU\EDQNVLQDQLQWHUOHDYHGIDVKLRQDOORZV UDQGRP DFFHVV RSHUDWLRQ WR RFFXU DW D KLJKHU UDWH WKDQ LV SRVVLEOH ZLWK VWDQGDUG '5$0V $Q DXWR SUHFKDUJH IXQFWLRQPD\EHHQDEOHGWRSURYLGHDVHOIWLPHGURZSUHFKDUJHWKDWLVLQLWLDWHGDWWKHHQGRIWKHEXUVWVHTXHQFH $ VHTXHQWLDODQGJDSOHVVGDWDUDWHLVSRVVLEOHGHSHQGLQJRQEXUVWOHQJWK&$6ODWHQF\DQGVSHHGJUDGHRIWKHGHYLFH Confidential - 3/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Table . Speed Grade Information 6SHHG*UDGH Clock Frequency CAS Latency ''5 0+]  tRCD (ns)  tRP (ns)  Table . Ordering Information Part Number 2UJ $6&0'%&1 [ $6&0'%,1 [ 7HPSHUDWXUH 0D[&ORFN0+]  &RPPHUFLDOƒ&WRƒ&  ,QGXVWULDOƒ&WRƒ& Package EDOO)%*$ EDOO)%*$ &LQGLFDWHVCommercial temperature I: indicates Industrial temperature N: LQGLFDWHV ROHS compliant 3E)UHHDQG+DORJHQ)UHH Confidential - 4/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 1. Ball Assignment (FBGA Top View) $    VDD NC % DQ14 & «     VSS VSSQ UDQS# VDDQ VSSQ UDM UDQS. VSSQ DQ15 VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ ' DQ12 VSSQ DQ11 DQ10 VSSQ DQ13 ( VDD NC VSS VSSQ LDQS# VDDQ ) DQ6 VSSQ LDM LDQS VSSQ DQ7 * VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ + DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 - VDDL VREF VSS VSSDL CK VDD CKE WE# RAS# CK# ODT BA0 BA1 CAS# CS# A10 A1 A2 A0 A3 A5 A6 A4 A7 A9 A11 A8 A12 NC NC NC . / NC 0 1 VSS 3 5 Confidential VDD - 5/66 - VDD VSS Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 2. Block Diagram CK CK# DLL CLOCK BUFFER COMMAND DECODER A10/AP COLUMN COUNTER MODE REGISTER Column Decoder DATA STROBE BUFFER DQ0 4M x 16 CELL ARRAY (BANK #2) Column Decoder DQ Buffer Row Decoder ~ DQ15 ODT LDM UDM Confidential 4M x 16 CELL ARRAY (BANK #1) ADDRESS BUFFER REFRESH COUNTER LDQS LDQS# UDQS UDQS# 4M x 16 CELL ARRAY (BANK #0) Column Decoder Row Decoder A0~A9 A11 A12 BA0 BA1 CONTROL SIGNAL GENERATOR Row Decoder CS# RAS# CAS# WE# Row Decoder CKE - 6/66 - 4M x 16 CELL ARRAY (BANK #3) Column Decoder Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 3. State Diagram &.(/ 2&' FDOLEUDWLRQ ,QLWLDOL]DWLRQ 6HTXHQFH 65) + &.( 35 6HWWLQJ 05 (05 (05 (05 (056 ,GOH $OOEDQNV SUHFKDUJHG 6HOI 5HIUHVKLQJ 5() 5HIUHVKLQJ &. $&7 &. (/ (/ &. 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 EMR(3) 1RIXQFWLRQLVGHILQHGLQH[WHQGHGPRGHUHJLVWHU7KHGHIDXOWYDOXHRIWKHH[WHQGHGPRGHUHJLVWHULVQRW GHILQHGWKHUHIRUHWKHH[WHQGHGPRGHUHJLVWHUPXVWEHSURJUDPPHGGXULQJLQLWLDOL]DWLRQIRUSURSHURSHUDWLRQ Table 8. Extended Mode Register EMR (3) Bitmap %$ %$ $ $ $ $   $ $ $  $  $ $ $ $ $ $GGUHVV)LHOG ([WHQGHG0RGH5HJLVWHU NOTE 1:$OOELWVLQ(05H[FHSW%$DQG%$DUHUHVHUYHGIRUIXWXUHXVHDQGPXVWEHVHWWRZKHQSURJUDPPLQJWKH(05  Confidential - 15/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 ! Off-chip drive (OCD) impedance adjustment ''56'5$0VXSSRUWVGULYHUFDOLEUDWLRQIHDWXUHDQGWKHIROORZLQJIORZFKDUWLVDQH[DPSOHRIVHTXHQFH(YHU\ FDOLEUDWLRQPRGHFRPPDQGVKRXOGEHIROORZHGE\³2&'FDOLEUDWLRQPRGHH[LW´EHIRUHDQ\RWKHUFRPPDQGEHLQJ LVVXHG$OO05VKRXOGEHSURJUDPPHGEHIRUHHQWHULQJ2&'LPSHGDQFHDGMXVWPHQWDQG2'72Q'LH7HUPLQDWLRQ VKRXOGEHFDUHIXOO\FRQWUROOHGGHSHQGLQJRQV\VWHPHQYLURQPHQW Figure 4. OCD impedance adjustment sequence Before entering OCD impedance adjustment, all MR should be programmed and ODT should be carefully controlled depending on system environment Start EMRS:OCD calibration mode exit EMRS:Drive(1) DQ &DQS HIGH;DQS# LOW Test EMRS:Drive(0) DQ &DQS LOW;DQS# HIGH ALL OK ALL OK Test EMRS:OCD calibration mode exit EMRS:OCD calibration mode exit EMRS:Enter Adjust Mode EMRS:Enter Adjust Mode BL=4 code input to all DQs Inc, Dec, or NOP BL=4 code input to all DQs Inc, Dec, or NOP EMRS:OCD calibration mode exit EMRS:OCD calibration mode exit EMRS:OCD calibration mode exit End Confidential - 16/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2
 Extended mode register for OCD impedance adjustment 2&' LPSHGDQFH DGMXVWPHQW FDQ EH GRQH XVLQJ WKH IROORZLQJ (056 PRGH ,Q GULYH PRGH DOO RXWSXWV DUH GULYHQRXWE\''56'5$0,Q'ULYHPRGHDOO'4'46VLJQDOVDUHGULYHQ+,*+DQGDOO'46VLJQDOVDUH GULYHQ/2:,Q'ULYHPRGHDOO'4'46VLJQDOVDUHGULYHQ/2:DQGDOO'46VLJQDOVDUHGULYH+,*+,Q DGMXVW PRGH %/   RI RSHUDWLRQ FRGH GDWD PXVW EH XVHG ,Q FDVH RI 2&' FDOLEUDWLRQ GHIDXOW RXWSXW GULYHU FKDUDFWHULVWLFV KDYH D QRPLQDO LPSHGDQFH YDOXH RI  2KPV GXULQJ QRPLQDO WHPSHUDWXUH DQG YROWDJH FRQGLWLRQV 2XWSXW GULYHU FKDUDFWHULVWLFV IRU 2&' FDOLEUDWLRQ GHIDXOW DUH VSHFLILHG LQ WKH IROORZLQJ WDEOH 2&' DSSOLHVRQO\WRQRUPDOIXOOVWUHQJWKRXWSXWGULYHVHWWLQJGHILQHGE\(056DQGLIKDOIVWUHQJWKLVVHW2&'GHIDXOW GULYHUFKDUDFWHULVWLFVDUHQRWDSSOLFDEOH:KHQ2&'FDOLEUDWLRQDGMXVWPRGHLVXVHG2&'GHIDXOWRXWSXWGULYHU FKDUDFWHULVWLFV DUH QRW DSSOLFDEOH $IWHU 2&' FDOLEUDWLRQ LV FRPSOHWHG RU GULYHU VWUHQJWK LV VHW WR GHIDXOW VXEVHTXHQW(056FRPPDQGVQRWLQWHQGHGWRDGMXVW2&'FKDUDFWHULVWLFVPXVWVSHFLI\$a$DV¶¶LQRUGHU WRPDLQWDLQWKHGHIDXOWRUFDOLEUDWHGYDOXH Table 9. OCD drive mode program A9 A8 A7 operation                2&'FDOLEUDWLRQPRGHH[LW 'ULYH'4'46+,*+DQG'46/2: 'ULYH'4'46/2:DQG'46+,*+ $GMXVWPRGH 2&'FDOLEUDWLRQGHIDXOW
 OCD impedance adjust 7RDGMXVWRXWSXWGULYHULPSHGDQFHFRQWUROOHUVPXVWLVVXHWKH$'-867(056FRPPDQGDORQJZLWKDELWEXUVW FRGHWR''56'5$0DVLQWKHIROORZLQJWDEOH)RUWKLVRSHUDWLRQ%XUVW/HQJWKKDVWREHVHWWR%/ YLD 056FRPPDQGEHIRUHDFWLYDWLQJ2&'DQGFRQWUROOHUVPXVWGULYHWKLVEXUVWFRGHWRDOO'4VDWWKHVDPHWLPH '7 LQ WKH IROORZLQJ WDEOH PHDQV DOO '4 ELWV DW ELW WLPH  '7 DW ELW WLPH  DQG VR IRUWK 7KH GULYHU RXWSXW LPSHGDQFHLVDGMXVWHGIRUDOO''56'5$0'4VVLPXOWDQHRXVO\DQGDIWHU2&'FDOLEUDWLRQDOO'4VRIDJLYHQ ''56'5$0ZLOOEHDGMXVWHGWRWKHVDPHGULYHUVWUHQJWKVHWWLQJ 7KHPD[LPXPVWHSFRXQWIRUDGMXVWPHQWLVDQGZKHQWKHOLPLWLVUHDFKHGIXUWKHULQFUHPHQWRUGHFUHPHQW FRGHKDVQRHIIHFW7KHGHIDXOWVHWWLQJPD\EHDQ\VWHSZLWKLQWKHVWHSUDQJH:KHQ$GMXVWPRGHFRPPDQG LVLVVXHG$/IURPSUHYLRXVO\VHWYDOXHPXVWEHDSSOLHG Table 10. OCD adjust mode program 4bit burst code inputs to all DQs DT0 DT1 DT2 DT3                                     2WKHU&RPELQDWLRQV Confidential Pull-up driver strength 123 ,QFUHDVHE\VWHS 'HFUHDVHE\VWHS 123 123 ,QFUHDVHE\VWHS 'HFUHDVHE\VWHS ,QFUHDVHE\VWHS 'HFUHDVHE\VWHS - 17/66 - Operation Pull-down driver strength 123 123 123 ,QFUHDVHE\VWHS 'HFUHDVHE\VWHS ,QFUHDVHE\VWHS ,QFUHDVHE\VWHS 'HFUHDVHE\VWHS 'HFUHDVHE\VWHS 5HVHUYHG Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 ! ODT (On Die Termination) 2Q 'LH 7HUPLQDWLRQ 2'7 LV D IHDWXUH WKDW DOORZV D '5$0 WR WXUQ RQRII WHUPLQDWLRQ UHVLVWDQFH IRU HDFK '4 8'468'46/'46/'468'0DQG/'0VLJQDOYLDWKH2'7FRQWUROSLQ7KH2'7IHDWXUHLVGHVLJQHGWR LPSURYH VLJQDO LQWHJULW\ RI WKH PHPRU\ FKDQQHO E\ DOORZLQJ WKH '5$0 FRQWUROOHU WR LQGHSHQGHQWO\ WXUQ RQRII WHUPLQDWLRQUHVLVWDQFHIRUDQ\RUDOO'5$0GHYLFHV 7KH 2'7 IXQFWLRQ LV VXSSRUWHG IRU $&7,9( DQG 67$1'%$/ DQG&/ 5/ $/&/ :/ 5/ %/ @ Figure 17.2. Posted CAS# operation: AL=0 Read followed by a write to the same bank             &. &. $/  &0' $FWLYH $%DQN :ULWH $%DQN 5HDG $%DQN &/  '46 '46 :/ 5/  ! W5&' 5/ $/&/  '4 'RXW 'RXW 'RXW 'RXW 'LQ 'LQ 'LQ 'LQ >$/ DQG&/ 5/ $/&/ :/ 5/ %/ @ Confidential - 44/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 18. Data output (read) timing &. W&/ W&+ &. &. '46 '46 '46 '46 W535( '4 W5367 Q W'464PD[ Q Q Q W'464PD[ W4+ W4+ Figure 19.1. Burst read operation: RL=5 (AL=2, CL=3, BL=4) &. &. &0' 7 7 3RVWHG&$6 5($'$ 123 7 123 7 7 123 7 123 7 123 7 123 123 7 123 W'46&. '46 '46 $/  &/  5/  '4V 'RXW$ 'RXW$ 'RXW$ 'RXW$ Figure 19.2. Burst read operation: RL=3 (AL=0 and CL=3, BL=8) &. &. &0' '46 '46 7 5($'$ 7 123 7 123 7 7 123 7 123 7 123 7 123 123 7 123 W'46&. &/  5/  '4V Confidential 'RXW$ 'RXW$ 'RXW$ 'RXW$ 'RXW$ - 45/66 - 'RXW$ 'RXW$ 'RXW$ Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 20. Burst read followed by burst write: RL=5, WL= (RL-1) =4, BL=4 7 &. &. &0' 7 3RVW&$6 5($'$ 7Q 123 7Q 7Q 3RVW&$6 :5,7($ 123 7Q 123 7Q 123 7Q 123 7Q 123 123 W57:5HDGWR:ULWHWXUQDURXQGWLPH '46 '46 5/  :/ 5/  '4V 'RXW$ 'RXW$ 'RXW$ 'LQ$ 'RXW$ 'LQ$ 'LQ$ 'LQ$ NOTE : The minimum time from the burst read command to the burst write command is defined by a read-to-writeturn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation. Figure 21. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4 7 &. &. &0' 7 3RVW&$6 5($'$ 123 7 7 3RVW&$6 5($'% 123 7 123 7 7 123 7 123 7 123 123 '46 '46 $/  &/  5/  '4V 'RXW$ 'RXW$ 'RXW$ 'RXW$ 'RXW% 'RXW% 'RXW% NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. Confidential - 46/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 22. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8) &. &. &0' 5HDG$ 123 123 5HDG% 123 123 123 123 123 123 '46 '46 '4V $ $ $ $ % % % % % % % % NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited. NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited. NOTE 4: Read burst interruption is allowed to any bank inside DRAM. NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt. NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command. NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Figure 23. Data input (write) timing W'46+ '46 W'46/ '46 '46 '46 W:35( '4 W:36/ 9,+DF ' 9,/DF W'6 '0 Confidential '0LQ ' 9,+GF ' 9,/GF W'+ W'6 9,+DF '0LQ 9,/DF ' W'+ 9,+GF '0LQ - 47/66 - '0LQ 9,/GF Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 24.1. Burst write operation: RL=5 (AL=2, CL=3), WL=4, BL=4 &. &. &0' 7 7 7 3RVWHG&$6 :5,7($ 123 7 123 7 123 &DVHZLWKW'466PD[ '46 '46 7 123 123 W'466 W'66 W'466 7 123 W'66 123 7Q 3UHFKDUJH &RPSOHWLRQRIWKH %XUVW:ULWH :/ 5/  ! W:5 '4V '1$ &DVHZLWKW'466PLQ '46 '46 7 W'466 W'6+ '1$ '1$ '1$ W'466 W'6+ ! W:5 :/ 5/  '4V '1$ '1$ '1$ '1$ Figure 24.2. Burst write operation: RL=3 (AL=0, CL=3), WL=2, BL=4 &. &. &0' 7 7 :5,7($ 123 7 7 123 7 123 123  W'466 '46 '46 '4V Confidential 7 123 ! W:5 '1$ 7P 123 3UHFKDUJH 7Q %DQN$ $FWLYDWH &RPSOHWLRQRIWKH %XUVW:ULWH :/ 5/  '1$ 7P ! W53 '1$ '1$ - 48/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 25. Burst write followed by burst read: RL=5 (AL=2, CL=3, WL=4, tWTR=2, BL=4) &. 7 7 7 7 7 7 7 7 7 7 &. :ULWHWR5HDG &/%/W:75 &.( '46 '46 123 123 123 3RVW&$6 5($'$ 123 123 123 123 123 '46 '46 :/ 5/  $/  &/  5/  ! W:75 '4 '1$ '1$ '1$ '1$ '287$ NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4 bit write data from the input buffer into sense amplifiers in the array. tWTR is defined in the timing parameter table of this standard. Figure 26. Seamless burst write operation RL=5, WL=4, BL=4 &. 7 7 7 7 7 7 7 7 7 &. &0' '46 '46 '4 3RVW&$6 :ULWH$ 123 3RVW&$6 :ULWH% 123 123 123 123 123 123 '46 '46 :/ 5/  '1$ '1$ '1$ '1$ '1% '1% '1% '1% NOTE : The seamless burst write operation is supported by enabling a write command every other clock for BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. Confidential - 49/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 27. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8) &. &. &0' 123 :ULWH$ 123 :ULWH% 123 123 123 123 123 123 '46 '46 '4V $ $ $ $ % % % % % % % % NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited. NOTE 3: Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited. NOTE 4: Write burst interruption is allowed to any bank inside DRAM. NOTE 5: Write burst with Auto Precharge enabled is not allowed to interrupt. NOTE 6: Write burst interruption is allowed by another Write with Auto Precharge command. NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL + BL/2 + tWR where tWR starts with the rising clock after the uninterrupted burst end and not from the end of actual burst end. Confidential - 50/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 28. Write data mask 'DWD0DVN7LPLQJ '46 '46 '4 9,+DF9,+GF '0 'DWD0DVN)XQFWLRQ:/ $/ %/ VKRZQ 9,+DF9,+GF 9,/DF9,/GF 9,/DF9,/GF W'6 W'+ W'6 W'+ &DVHPLQW'466 &. &. &200$1' '46 '46 W:5 :ULWH :/ W'466 '4 '0 &DVHPD[W'466 '46 '46 W'466 '4 '0 Confidential - 51/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 29.1. Burst read operation followed by precharge: (RL=4, AL=1, CL=3, BL=4, tRTP 2 clocks) 7 &. 7 7 7 7 7 7 7 7 &. 3RVW&$6 5HDG$ &0' 123 123 123 3UHFKDUJH 123 %DQN$ $FWLYH 123 123 $/%/ FONV '46 '46 $/  &/  ! W53 5/  '4 '287$ '287$ '287$ '287$ ! W5$6 ! W573 &/  Figure 29.2.Burst read operation followed by precharge: (RL=4, AL=1, CL=3, BL=8, tRTP2 clocks) &. &. 7 &0' '46 '46 '4 V 7 3RVW&$6 5($'$ 7 123 7 123 7 123 123 7 3UHFKDUJH$ 7 123 7 7 123 123 $/%/FONV &/  $/  5/  '287 '287 '287 '287 '287 '287 '287 '287 $ $ $ $ $ $ $ $ ! W573 )LUVWELWSUHIHWFK Confidential 6HFRQGELWSUHIHWFK - 52/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 29.3. Burst read operation followed by precharge: (RL=5, AL=2, CL=3, BL=4, tRTP2 clocks) &. 7 7 7 7 7 7 7 7 7 &. &0' 3RVW&$6 5($'$ 123 123 123 123 3UHFKDUJH$ 123 %DQN$ $FWLYDWH 123 $/%/FONV '46 '46 $/  &/  ! W53 5/  '287 '287 '287 '287 $ $ $ $ '4 V ! W5$6 &/  ! W573 Figure 29.4. Burst read operation followed by precharge: (RL=6, AL=2, CL=4, BL=4, tRTP2 clocks) &. 7 7 7 7 7 7 7 7 7 &. &0' '46 '46 3RVW&$6 5($'$ 123 123 123 3UHFKDUJH$ 123 123 %DQN$ $FWLYDWH 123 $/%/FONV $/  &/  ! W53 5/  '287 '287 '287 '287 $ $ $ $ '4 V ! W5$6 &/  ! W573 Confidential - 53/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 29.5. Burst read operation followed by precharge: (RL=4, AL=0, CL=4, BL=8, tRTP>2 clocks) 7 &. 7 7 7 7 7 7 7 7 &. 3RVW&$6 5($'$ &0' 123 123 123 123 123 3UHFKDUJH$ 123 %DQN$ $FWLYDWH $/PD[W573W&. '46 '46 &/  $/  ! W53 5/  '4 V '287 '287 '287 '287 '287 '287 '287 '287 $ $ $ $ $ $ $ $ ! W5$6 )LUVWELWSUHIHWFK ! W573 6HFRQGELWSUHIHWFK URXQGHGWRQH[WLQWHJHU Figure 30.1. Burst write operation followed by precharge: WL= (RL-1) =3 &. 7 7 7 7 7 7 7 7 7 &. &0' 3RVW&$6 :ULWH$ 123 123 123 123 123 123 123 3UHFKDUJH$ &RPSOHWLRQRIWKH%XUVW:ULWH '46 '46 '4 V Confidential ! W:5 :/  '1$ '1$ '1$ '1$ - 54/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 30.2. Burst write followed by precharge: WL= (RL-1) =4 7 &. 7 7 7 7 7 7 7 7 &. 3RVW&$6 :ULWH$ &0' 123 123 123 123 123 123 123 3UHFKDUJH$ &RPSOHWLRQRIWKH%XUVW:ULWH ! W:5 '46 '46 :/  '4 V '1$ '1$ '1$ '1$ Figure 31.1. Burst read operation with auto precharge: (RL=4,AL=1, CL=3, BL=8, tRTP2 clocks) 7 &. &. &0' 7 3RVW&$6 5($'$ 7 123 123 $XWRSUHFKDUJH '46 '46 '4 V 7 7 123 123 7 123 7 123 7 7 123 %DQN$ $FWLYDWH ! W53 $/%/FONV &/  $/  5/  ! W573 '287 '287 '287 '287 '287 '287 '287 '287 $ $ $ $ $ $ $ $ W573 )LUVWELWSUHIHWFK Confidential 6HFRQGELWSUHIHWFK - 55/66 - 3UHFKDUJHEHJLQVKHUH Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 31.2. Burst read operation with auto precharge: (RL=4, AL=1, CL=3, BL=4, tRTP>2 clocks) 7 &. 7 7 7 7 7 7 7 7 &. 3RVW&$6 5($'$ &0' 123 123 123 123 123 %DQN$ $FWLYDWH 123 ! $/W573W53 $XWRSUHFKDUJH '46 '46 123 $/  &/  5/  '4 V 'RXW$ 'RXW$ 'RXW$ 'RXW$ W573 W53 )LUVWELWSUHIHWFK 3UHFKDUJHEHJLQVKHUH Figure 31.3. Burst read operation with auto precharge followed by activation to the same bank (tRC Limit): RL=5(AL=2, CL=3, internal tRCD=3, BL=4,tRTP2 clocks) 7 &. &. 7 7 7 7 7 7 7 7 $  &0' '46 '46 3RVW&$6 5($'$ 123 123 123 123 123 123 %DQN$ $FWLYDWH ! W5$6PLQ $XWR3UHFKDUJH%HJLQV $/  &/  5/  ! W53 '4 V 'RXW$ 'RXW$ 'RXW$ 'RXW$ &/  ! W5& Confidential 123 - 56/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 31.4. Burst read operation with auto precharge followed by an activation to the same bank (tRP Limit): (RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP2 clocks) 7 &. &. 7 7 7 7 7 7 7 7 $  3RVW&$6 5($'$ &0' 123 123 123 ! W5$6PLQ 123 123 %DQN$ $FWLYDWH 123 123 $XWR3UHFKDUJH%HJLQV '46 '46 $/  ! W53 &/  5/  '4 V 'RXW$ 'RXW$ 'RXW$ 'RXW$ &/  ! W5& Figure 32.1. Burst write with auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 7 &. 7 7 7 7 7 7 7 7P &. $  &0' 3RVW&$6 :5$%DQN$ 123 123 123 123 123 123 123 %DQN$ $FWLYH &RPSOHWLRQRIWKH%XUVW:ULWH '46 '46 '4 V Confidential $XWR3UHFKDUJH%HJLQV ! :5 :/ 5/  '1$ '1$ ! W53 '1$ '1$ ! W5& - 57/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 32.2. Burst write with auto-precharge (WR+tRP): WL=4, WR=2, BL=4, tRP=3 7 &. 7 7 7 7 7 7 7 7 &. $  &0' 3RVW&$6 :5$%DQN$ 123 123 123 123 123 123 %DQN$ $FWLYH 123 &RPSOHWLRQRIWKH%XUVW:ULWH $XWR3UHFKDUJH%HJLQV '46 '46 ! :5 :/ 5/  '4 V '1$ '1$ ! W53 '1$ '1$ ! W5& Figure 33. Refresh command &. 7 7 7 7 7P 7Q 7Q &. +,*+ &.( &0' Confidential ! W53 3UHFKDUJH 123 ! W5)& 123 5() ! W5)& 5() - 58/66 - 123 $1< Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 34. Self refresh operation 7 &. W&+ W&. 7 7 7 7 7 7 7P 7Q W&/ &. ! W;615 W53 &.( ! W;65' 9,+DF 9,/DF W$2)' 2'7 W,6 W,6 9,/DF W,6 W,6 W,+ W,+ W,6 VIH(ac) 6HOI VIH(dc) VIL(ac) 5HIUHVK VIL(dc) &0' W,+ 123 123 123 9DOLG 127('HYLFHPXVWEHLQWKH$OOEDQNVLGOHVWDWHSULRUWRHQWHULQJ6HOI5HIUHVKPRGH 127(2'7PXVWEHWXUQHGRIIW$2)'EHIRUHHQWHULQJ6HOI5HIUHVKPRGHDQGFDQEH WXUQHGRQDJDLQZKHQW;65'WLPLQJLVVDWLVILHG 127(W;65'LVDSSOLHGIRU5HDGRUD5HDGZLWKDXWRSUHFKDUJHFRPPDQG W;615LVDSSOLHGIRUDQ\FRPPDQGH[FHSWD5HDGRUD5HDGZLWKDXWRSUHFKDUJHFRPPDQG Figure 35. Basic power down entry and exit timing diagram &. &. &.( &RPPDQG W,+ W,6 9$/,' W,+ 123 W,6 123 123 W&.(PLQ W,6 W,+ 9$/,' 9$/,' RU123 W;3W;$5' W;$5'6 ([LW3RZHU'RZQPRGH (QWHU3RZHU'RZQPRGH W,+ W&.(PLQ Don't Care Figure 36.1.CKE intensive environment &. &. W&.( W&.( &.( W&.( W&.( NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation Confidential - 59/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 36.2.CKE intensive environment &. &. &.( W&.( W&.( W&.( W;3 &0' W&.( W;3 5() 5() W5(), —V NOTE: The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all AC and DC timing & voltage specifications and DLL operation with temperature and voltage drift Figure 37. Read to power-down entry &. 7 7 7 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ &. &0' 5' 5HDGRSHUDWLRQVWDUWVZLWKDUHDGFRPPDQGDQG &.(VKRXOGEHNHSW+,*+XQWLOWKHHQGRIEXUVWRSHUDWLRQ %/  &.( $/&/ 4 '4 4 4 W,6 4 '46 '46 &. 7 7 7 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ &. &0' 5' &.(VKRXOGEHNHSW+,*+XQWLOWKHHQGRIEXUVWRSHUDWLRQ %/  &.( $/&/ '4 4 4 4 4 4 4 4 4 W,6 '46 '46 Confidential - 60/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 38. Read with autoprecharge to power-down entry &. 7 7 7 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ &. &0' 5'$ 35( %/  &.(VKRXOGEHNHSW+,*+XQWLOWKHHQGRIEXUVWRSHUDWLRQ $/%/ZLWKW573 QV W5$6PLQVDWLVILHG &.( $/&/ 4 '4 4 4 W,6 4 '46 '46 &. 7 7 7 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ &. 6WDUWLQWHUQDOSUHFKDUJH &0' 5' 35( %/  &.(VKRXOGEHNHSW+,*+XQWLOWKHHQGRIEXUVWRSHUDWLRQ $/%/ZLWKW573 QV W5$6PLQVDWLVILHG &.( $/&/ 4 '4 4 4 4 4 4 4 W,6 4 '46 '46 Figure 39. Write to power-down entry &. 7 7 7P 7P 7P 7P 7[ 7[ 7[ 7\ 7\ 7\ 7\ 7[ 7[ 7[ 7[ 7[ &. &0' :5 %/  &.( :/ 4 '4 4 4 W,6 4 W:75 '46 '46 &. 7 7 7P 7P 7P 7P 7P 7P &. &0' &.( :5 %/  :/ '4 4 4 4 4 4 4 4 W,6 4 W:75 '46 '46 Confidential - 61/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 40. Write with autoprecharge to power-down entry &. 7 7 7P 7P 7P 7P 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ 7[ &. &0' 35( :5$ %/  &.( :/ 4 '4 4 4 W,6 4 :5  '46 '46 &. 7 7 7P 7P 7P 7P 7P 7P 7[ &. 6WDUWLQWHUQDO3UHFKDUJH &0' :5$ 35( %/  &.( :/ 4 '4 4 4 4 4 4 4 W,6 4 :5  '46 '46 :5LVSURJUDPPHGWKURXJK056 Figure 41. Refresh command to power-down entry &. 7 7 7 7 7 7 7 7 7 7 7 7 &. &0' 5() &.(FDQJRWR/2:RQHFORFNDIWHUDQ$XWRUHIUHVKFRPPDQG &.( W,6 Confidential - 62/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 42. Active command to power-down entry 7 &0' 7 7 7 7 7 7 7 7 7 7 7 $&7 &.(FDQJRWR/2:RQHFORFNDIWHUDQ$FWLYHFRPPDQG &.( W,6 Figure 43. Precharge/precharge-all command to power-down entry 7 &0' 7 7 7 7 7 7 7 7 7 7 7 35RU35$ &.(FDQJRWR/2:RQHFORFNDIWHUD3UHFKDUJHRU3UHFKDUJHDOOFRPPDQG &.( W,6 Figure 44. MRS/EMRS command to power-down entry 7 &0' 7 056RU (056 7 7 7 7 7 7 7 7 7 7 W05' &.( W,6 Confidential - 63/66 - Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 45. Asynchronous CKE LOW event 6WDEOHFORFNV W&. &. &. &.( W'HOD\ &.(DV\QFKURQRXVO\GURSV/2: W,6 &ORFNVFDQEHWXUQHGRIIDIWHUWKLVSRLQW Figure 46. Clock frequency change in precharge power down mode &. &. 7 &0' 7 7 123 123 7 7[ 7[ 7\ 7\ 7\ 7\ 123 123 7\ '// 5(6(7 7] 123 9DOLG )UHTXHQF\&KDQJH2FFXUVKHUH &.( 2'7 W,6 W53 W$2)' 0LQLPXPFORFNVUHTXLUHGEHIRUH FKDQJLQJIUHTXHQF\ Confidential W,6 &ORFNV W;3 6WDEOHQHZFORFNEHIRUHSRZHU GRZQH[LW - 64/66 - W,+ 2'7LVRIIGXULQJ'//5(6(7 Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 Figure 47. 84-Ball TFBGA Package Outline Drawing Information PIN A1 INDEX Top View Bottom View Side View DETAIL : "A" Symbol $ $ ' ( ' ( ) H E Confidential Dimension in inch Min Nom Max                            - 65/66 - Dimension in mm Min Nom Max                            Rev.1.0 May 2015 256M DDR2 -AS4C16M16D2 PART NUMBERING SYSTEM AS4C DRAM 6MD 6M=6Mx D=''5  B =00MHz B = FBGA C/I C=Commercial (0¡ C
5¡ C) I=Industrial (-40¡ C
95¡ C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 66/66 - Rev.1.0 May 2015