AS4C1G8MD3L-12BCN

8Gb: x4, x8, x16 DDR3L SDRAM Description Revision History 8Gb: x4, x8, x16 DDR3L SDRAM AS4C2GM4D3L– 256 Meg x 4 x 8 banks* AS4C1G8MD3L– 128 Meg x 8 x 8 banks AS4C512M16D3L – 64 Meg x 16 x 8 banks Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amend Table 1 noted. Date February 2016 June 2016 * not released yet Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 0 8Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM AS4C2GM4D3L– 256 Meg x 4 x 8 banks* AS4C1G8MD3L– 128 Meg x 8 x 8 banks AS4C512M16D3L – 64 Meg x 16 x 8 banks • TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C • Self refresh temperature (SRT) • Automatic self refresh (ASR) • Write leveling • Multipurpose register • Output driver calibration Features • VDD = V DDQ = 1.35V (1.283–1.45V) • Backward compatible to V DD = V DDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward compatible in 1.5V applications • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode Options Marking • Configuration – 2 Gig x 4 – 1 Gig x 8 – 512 Meg x 16 • FBGA package (Pb-free) – x4, x8 – 78-ball (9mm x 13.2mm) • FBGA package (Pb-free) – x16 – 96-ball (9mm x 14mm) • Timing – cycle time – 938ps @ CL = 14 (DDR3-2133) – 1.07ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) • Operating temperature – Commercial (0°C ≤ T C ≤ +95°C) – Industrial (–40°C ≤ T C ≤ +95°C) 2GM4 1GM8 512M16 B B -09 -10 -12 C I Key Timing Parameters Speed Grade -12 Data Rate (MT/s) 1600 Target tRCD-tRP-CL tRCD 11-11-11 (ns) 13.75 tRP (ns) 13.75 CL (ns) 13.75 Table 1:Ordering Information Part Number AS4C2GM4D3L-12BCN* AS4C2GM4D3L-12BIN* AS4C1G8MD3L-12BCN AS4C1G8MD3L-12BIN AS4C512M16D3L-12BCN AS4C512M16D3L-12BIN Clock Frequency 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz Data Rate(MT/s) 1600 1600 1600 1600 1600 1600 Power Supply 1.35V (1.283–1.45V) 1.35V (1.283–1.45V) 1.35V (1.283–1.45V) 1.35V (1.283–1.45V) 1.35V (1.283–1.45V) 1.35V (1.283–1.45V) Package 78-ball (9mm x 13.2mm) FBGA 78-ball (9mm x 13.2mm) FBGA 78-ball (9mm x 13.2mm) FBGA 78-ball (9mm x 13.2mm)  FBGA 96-ball (9mm x 14mm) FBGA 96-ball (9mm x 14mm) FBGA Notes: 1.Alliance Memory Inc will only offer the -12 1.25ns @ CL = 11 (DDR3-1600) option 2.* not released yet Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 1 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description Table 2: Addressing Parameter Configuration 2 Gig x 4 1 Gig x 8 512 Meg x 16 256 Meg x 4 x 8 banks 128 Meg x 8 x 8 banks 64 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 64K (A[15:0]) 64K (A[15:0]) 64K (A[15:0]) Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) 4K (A[13,11, 9:0]) 2K (A[11,9:0]) 1K (A[9:0]) 2KB 2KB 2KB Column address Page size Figure 1: DDR3L Part Numbers AS4C512M16D3L-12BCN Example Part Number: Configuration Speed Package Lead Temperature Free { AS4C N AS = Alliance Memory 4C= DRAM Temperature Configuration 2 Gig x 4 2GM4 Commercial C 1 Gig x 8 1GM8 Industrial temperature I 512 Meg x 16 512M16 -12 Speed Grade Package 78-ball 9.0mm x 13.2mm FBGA tCK 96-ball 9.0mm x 14.0mm FBGA = 1.25ns, CL = 11 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 2 Mark B B Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Industrial Temperature ............................................................................................................................... 12 General Notes ............................................................................................................................................ 12 Functional Block Diagrams ............................................................................................................................. 14 Ball Assignments and Descriptions ................................................................................................................. 16 Package Dimensions ....................................................................................................................................... 22 Electrical Specifications .................................................................................................................................. 24 Absolute Ratings ......................................................................................................................................... 24 Input/Output Capacitance .......................................................................................................................... 25 Thermal Characteristics .................................................................................................................................. 26 Electrical Specifications – I DD Specifications and Conditions ........................................................................... 27 Electrical Characteristics – 1.35V IDD Specifications ......................................................................................... 38 Electrical Specifications – DC and AC .............................................................................................................. 39 DC Operating Conditions ........................................................................................................................... 39 Input Operating Conditions ........................................................................................................................ 40 DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 44 DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 47 DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 49 ODT Characteristics ....................................................................................................................................... 50 1.35V ODT Resistors ................................................................................................................................... 51 ODT Sensitivity .......................................................................................................................................... 52 ODT Timing Definitions ............................................................................................................................. 52 Output Driver Impedance ............................................................................................................................... 56 34 Ohm Output Driver Impedance .............................................................................................................. 57 DDR3L 34 Ohm Driver ................................................................................................................................ 58 DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 59 DDR3L Alternative 40 Ohm Driver ............................................................................................................... 60 DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 60 Output Characteristics and Operating Conditions ............................................................................................ 62 Reference Output Load ............................................................................................................................... 65 Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 65 Slew Rate Definitions for Differential Output Signals .................................................................................... 67 Speed Bin Tables ............................................................................................................................................ 68 Electrical Characteristics and AC Operating Conditions ................................................................................... 73 Command and Address Setup, Hold, and Derating ........................................................................................... 93 Data Setup, Hold, and Derating ...................................................................................................................... 100 Commands – Truth Tables ............................................................................................................................. 108 Commands ................................................................................................................................................... 111 DESELECT ................................................................................................................................................ 111 NO OPERATION ........................................................................................................................................ 111 ZQ CALIBRATION LONG ........................................................................................................................... 111 ZQ CALIBRATION SHORT .......................................................................................................................... 111 ACTIVATE ................................................................................................................................................. 111 READ ........................................................................................................................................................ 111 WRITE ...................................................................................................................................................... 112 PRECHARGE ............................................................................................................................................. 113 REFRESH .................................................................................................................................................. 113 SELF REFRESH .......................................................................................................................................... 114 DLL Disable Mode ..................................................................................................................................... 115 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 3 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description Input Clock Frequency Change ...................................................................................................................... 119 Write Leveling ............................................................................................................................................... 121 Write Leveling Procedure ........................................................................................................................... 123 Write Leveling Mode Exit Procedure ........................................................................................................... 125 Initialization ................................................................................................................................................. 126 Voltage Initialization / Change ....................................................................................................................... 128 VDD Voltage Switching ............................................................................................................................... 129 Mode Registers .............................................................................................................................................. 130 Mode Register 0 (MR0) ................................................................................................................................... 131 Burst Length ............................................................................................................................................. 131 Burst Type ................................................................................................................................................. 132 DLL RESET ................................................................................................................................................ 133 Write Recovery .......................................................................................................................................... 133 Precharge Power-Down (Precharge PD) ...................................................................................................... 134 CAS Latency (CL) ....................................................................................................................................... 134 Mode Register 1 (MR1) ................................................................................................................................... 135 DLL Enable/DLL Disable ........................................................................................................................... 135 Output Drive Strength ............................................................................................................................... 136 OUTPUT ENABLE/DISABLE ...................................................................................................................... 136 TDQS Enable ............................................................................................................................................. 136 On-Die Termination .................................................................................................................................. 137 WRITE LEVELING ..................................................................................................................................... 137 POSTED CAS ADDITIVE Latency ................................................................................................................ 137 Mode Register 2 (MR2) ................................................................................................................................... 138 CAS WRITE Latency (CWL) ........................................................................................................................ 139 AUTO SELF REFRESH (ASR) ....................................................................................................................... 139 SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 140 SRT vs. ASR ............................................................................................................................................... 140 DYNAMIC ODT ......................................................................................................................................... 140 Mode Register 3 (MR3) ................................................................................................................................... 141 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 141 MPR Functional Description ...................................................................................................................... 142 MPR Register Address Definitions and Bursting Order ................................................................................. 143 MPR Read Predefined Pattern .................................................................................................................... 149 MODE REGISTER SET (MRS) Command ........................................................................................................ 149 ZQ CALIBRATION Operation ......................................................................................................................... 150 ACTIVATE Operation ..................................................................................................................................... 151 READ Operation ............................................................................................................................................ 153 WRITE Operation .......................................................................................................................................... 164 DQ Input Timing ....................................................................................................................................... 172 PRECHARGE Operation ................................................................................................................................. 174 SELF REFRESH Operation .............................................................................................................................. 174 Extended Temperature Usage ........................................................................................................................ 176 Power-Down Mode ........................................................................................................................................ 177 RESET Operation ........................................................................................................................................... 185 On-Die Termination (ODT) ............................................................................................................................ 187 Functional Representation of ODT ............................................................................................................. 187 Nominal ODT ............................................................................................................................................ 187 Dynamic ODT ............................................................................................................................................... 189 Dynamic ODT Special Use Case ................................................................................................................. 189 Functional Description .............................................................................................................................. 189 Synchronous ODT Mode ................................................................................................................................ 195 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 4 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description ODT Latency and Posted ODT .................................................................................................................... 195 Timing Parameters .................................................................................................................................... 195 ODT Off During READs .............................................................................................................................. 198 Asynchronous ODT Mode .............................................................................................................................. 200 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 202 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 204 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 206 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 5 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description List of Figures Figure 1: DDR3L Part Numbers ........................................................................................................................ 2 Figure 2: Simplified State Diagram ................................................................................................................. 11 Figure 3: 2 Gig x 4 Functional Block Diagram .................................................................................................. 14 Figure 4: 1 Gig x 8 Functional Block Diagram .................................................................................................. 15 Figure 5: 512 Meg x 16 Functional Block Diagram ........................................................................................... 15 Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16 Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17 Figure 8: 78-Ball FBGA – x4, x8 (SN) ................................................................................................................ 22 Figure 9: 96-Ball FBGA – x16 (HA) .................................................................................................................. 23 Figure 10: Thermal Measurement Point ......................................................................................................... 26 Figure 11: DDR3L 1.35V Input Signal .............................................................................................................. 43 Figure 12: Overshoot ..................................................................................................................................... 44 Figure 13: Undershoot ................................................................................................................................... 45 Figure 14: V IX for Differential Signals .............................................................................................................. 45 Figure 15: Single-Ended Requirements for Differential Signals ........................................................................ 45 Figure 16: Definition of Differential AC-Swing and tDVAC ............................................................................... 46 Figure 17: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 48 Figure 18: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .............. 49 Figure 19: ODT Levels and I-V Characteristics ................................................................................................ 50 Figure 20: ODT Timing Reference Load .......................................................................................................... 53 Figure 21: tAON and tAOF Definitions ............................................................................................................ 54 Figure 22: tAONPD and tAOFPD Definitions ................................................................................................... 54 Figure 23: tADC Definition ............................................................................................................................. 55 Figure 24: Output Driver ................................................................................................................................ 56 Figure 25: DQ Output Signal .......................................................................................................................... 63 Figure 26: Differential Output Signal .............................................................................................................. 64 Figure 27: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 65 Figure 28: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 66 Figure 29: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 67 Figure 30: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) .............................................. 96 Figure 31: Nominal Slew Rate for tIH (Command and Address – Clock) ............................................................ 97 Figure 32: Tangent Line for tIS (Command and Address – Clock) ..................................................................... 98 Figure 33: Tangent Line for tIH (Command and Address – Clock) ..................................................................... 99 Figure 34: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 104 Figure 35: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 105 Figure 36: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 106 Figure 37: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 107 Figure 38: Refresh Mode ............................................................................................................................... 114 Figure 39: DLL Enable Mode to DLL Disable Mode ........................................................................................ 116 Figure 40: DLL Disable Mode to DLL Enable Mode ........................................................................................ 117 Figure 41: DLL Disable tDQSCK .................................................................................................................... 118 Figure 42: Change Frequency During Precharge Power-Down ........................................................................ 120 Figure 43: Write Leveling Concept ................................................................................................................. 121 Figure 44: Write Leveling Sequence ............................................................................................................... 124 Figure 45: Write Leveling Exit Procedure ....................................................................................................... 125 Figure 46: Initialization Sequence ................................................................................................................. 127 Figure 47: V DD Voltage Switching .................................................................................................................. 129 Figure 48: MRS to MRS Command Timing ( tMRD) ......................................................................................... 130 Figure 49: MRS to nonMRS Command Timing ( tMOD) .................................................................................. 131 Figure 50: Mode Register 0 (MR0) Definitions ................................................................................................ 132 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 6 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description Figure 51: READ Latency .............................................................................................................................. 134 Figure 52: Mode Register 1 (MR1) Definition ................................................................................................. 135 Figure 53: READ Latency (AL = 5, CL = 6) ....................................................................................................... 138 Figure 54: Mode Register 2 (MR2) Definition ................................................................................................. 139 Figure 55: CAS WRITE Latency ...................................................................................................................... 139 Figure 56: Mode Register 3 (MR3) Definition ................................................................................................. 141 Figure 57: Multipurpose Register (MPR) Block Diagram ................................................................................. 142 Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 145 Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 146 Figure 60: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 147 Figure 61: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 148 Figure 62: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 150 Figure 63: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 151 Figure 64: Example: tFAW ............................................................................................................................. 152 Figure 65: READ Latency .............................................................................................................................. 153 Figure 66: Consecutive READ Bursts (BL8) .................................................................................................... 155 Figure 67: Consecutive READ Bursts (BC4) .................................................................................................... 155 Figure 68: Nonconsecutive READ Bursts ....................................................................................................... 156 Figure 69: READ (BL8) to WRITE (BL8) .......................................................................................................... 156 Figure 70: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 157 Figure 71: READ to PRECHARGE (BL8) .......................................................................................................... 157 Figure 72: READ to PRECHARGE (BC4) ......................................................................................................... 158 Figure 73: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 158 Figure 74: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 158 Figure 75: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 160 Figure 76: Data Strobe Timing – READs ......................................................................................................... 161 Figure 77: Method for Calculating tLZ and tHZ ............................................................................................... 162 Figure 78: tRPRE Timing ............................................................................................................................... 162 Figure 79: tRPST Timing ............................................................................................................................... 163 Figure 80: tWPRE Timing .............................................................................................................................. 165 Figure 81: tWPST Timing .............................................................................................................................. 165 Figure 82: WRITE Burst ................................................................................................................................ 166 Figure 83: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 167 Figure 84: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 167 Figure 85: Nonconsecutive WRITE to WRITE ................................................................................................. 168 Figure 86: WRITE (BL8) to READ (BL8) .......................................................................................................... 168 Figure 87: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 169 Figure 88: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 170 Figure 89: WRITE (BL8) to PRECHARGE ........................................................................................................ 171 Figure 90: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 171 Figure 91: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 172 Figure 92: Data Input Timing ........................................................................................................................ 173 Figure 93: Self Refresh Entry/Exit Timing ...................................................................................................... 175 Figure 94: Active Power-Down Entry and Exit ................................................................................................ 179 Figure 95: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 179 Figure 96: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 180 Figure 97: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 180 Figure 98: Power-Down Entry After WRITE .................................................................................................... 181 Figure 99: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 181 Figure 100: REFRESH to Power-Down Entry .................................................................................................. 182 Figure 101: ACTIVATE to Power-Down Entry ................................................................................................. 182 Figure 102: PRECHARGE to Power-Down Entry ............................................................................................. 183 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 7 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: MRS Command to Power-Down Entry ......................................................................................... 183 Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 184 RESET Sequence ......................................................................................................................... 186 On-Die Termination ................................................................................................................... 187 Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 192 Dynamic ODT: Without WRITE Command .................................................................................. 192 Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 193 Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 194 Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 194 Synchronous ODT ...................................................................................................................... 196 Synchronous ODT (BC4) ............................................................................................................. 197 ODT During READs .................................................................................................................... 199 Asynchronous ODT Timing with Fast ODT Transition .................................................................. 201 Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 203 Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 205 Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 207 Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 207 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 8 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18 Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20 Table 5: Absolute Maximum Ratings .............................................................................................................. 24 Table 6: DDR3L Input/Output Capacitance .................................................................................................... 25 Table 7: Thermal Characteristics .................................................................................................................... 26 Table 8: Timing Parameters Used for I DD Measurements – Clock Units ............................................................ 27 Table 9: IDD0 Measurement Loop ................................................................................................................... 28 Table 10: IDD1 Measurement Loop .................................................................................................................. 29 Table 11: IDD Measurement Conditions for Power-Down Currents ................................................................... 30 Table 12: IDD2N and IDD3N Measurement Loop ................................................................................................ 31 Table 13: IDD2NT Measurement Loop .............................................................................................................. 31 Table 14: IDD4R Measurement Loop ................................................................................................................ 32 Table 15: IDD4W Measurement Loop ............................................................................................................... 33 Table 16: IDD5B Measurement Loop ................................................................................................................ 34 Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 35 Table 18: IDD7 Measurement Loop .................................................................................................................. 36 Table 19: IDD Maximum Limits Die Rev A ....................................................................................................... 38 Table 20: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 39 Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 40 Table 22: DDR3L 1.35V Input Switching Conditions – Command and Address ................................................. 41 Table 23: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 42 Table 24: DDR3L Control and Address Pins ..................................................................................................... 44 Table 25: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 44 Table 26: DDR3L 1.35V – Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ... 46 Table 27: Single-Ended Input Slew Rate Definition .......................................................................................... 47 Table 28: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 49 Table 29: On-Die Termination DC Electrical Characteristics ............................................................................ 50 Table 30: 1.35V RTT Effective Impedance ........................................................................................................ 51 Table 31: ODT Sensitivity Definition .............................................................................................................. 52 Table 32: ODT Temperature and Voltage Sensitivity ........................................................................................ 52 Table 33: ODT Timing Definitions .................................................................................................................. 53 Table 34: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 53 Table 35: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 57 Table 36: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 58 Table 37: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.35V ..................................... 58 Table 38: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.45V ..................................... 58 Table 39: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.283 ..................................... 59 Table 40: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 59 Table 41: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 59 Table 42: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 60 Table 43: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 60 Table 44: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 61 Table 45: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 62 Table 46: DDR3L Differential Output Driver Characteristics ............................................................................ 63 Table 47: DDR3L Differential Output Driver Characteristics V OX(AC) ................................................................. 64 Table 48: Single-Ended Output Slew Rate Definition ....................................................................................... 65 Table 49: Differential Output Slew Rate Definition .......................................................................................... 67 Table 50: DDR3L-1066 Speed Bins .................................................................................................................. 68 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 9 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Description Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 83: Table 84: Table 85: Table 86: Table 87: Table 88: Table 89: DDR3L-1333 Speed Bins .................................................................................................................. 69 DDR3L-1600 Speed Bins .................................................................................................................. 70 DDR3L-1866 Speed Bins .................................................................................................................. 71 DDR3L-2133 Speed Bins .................................................................................................................. 72 Electrical Characteristics and AC Operating Conditions .................................................................... 73 Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 83 DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based ................ 93 DDR3L-800/1066 Derating Values tIS/tIH – AC160/DC90-Based ........................................................ 94 DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC135/DC90-Based ................................. 94 DDR3L-1866/2133 Derating Values for tIS/tIH – AC125/DC90-Based ................................................. 94 DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL[AC]) for Valid ADD/CMD Transition .. 95 DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ....................... 100 DDR3L Derating Values for tDS/tDH – AC160/DC90-Based .............................................................. 101 DDR3L Derating Values for tDS/tDH – AC135/DC90-Based .............................................................. 101 DDR3L Derating Values for tDS/tDH – AC130/DC90-Based at 2V/ns ................................................. 102 DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition ............. 103 Truth Table – Command ................................................................................................................. 108 Truth Table – CKE .......................................................................................................................... 110 READ Command Summary ............................................................................................................ 112 WRITE Command Summary .......................................................................................................... 112 READ Electrical Characteristics, DLL Disable Mode ......................................................................... 118 Write Leveling Matrix ..................................................................................................................... 122 Burst Order .................................................................................................................................... 133 MPR Functional Description of MR3 Bits ........................................................................................ 142 MPR Readouts and Burst Order Bit Mapping ................................................................................... 143 Self Refresh Temperature and Auto Self Refresh Description ............................................................ 176 Self Refresh Mode Summary ........................................................................................................... 176 Command to Power-Down Entry Parameters .................................................................................. 177 Power-Down Modes ....................................................................................................................... 178 Truth Table – ODT (Nominal) ......................................................................................................... 188 ODT Parameters ............................................................................................................................ 188 Write Leveling with Dynamic ODT Special Case .............................................................................. 189 Dynamic ODT Specific Parameters ................................................................................................. 190 Mode Registers for RTT,nom ............................................................................................................. 190 Mode Registers for RTT(WR) ............................................................................................................. 191 Timing Diagrams for Dynamic ODT ................................................................................................ 191 Synchronous ODT Parameters ........................................................................................................ 196 Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 201 ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 203 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 10 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM State Diagram State Diagram Figure 2: Simplified State Diagram CKE L Power applied Power on MRS, MPR, write leveling Initialization Reset procedure Self refresh SRE ZQCL From any state RESET ZQ calibration MRS SRX REF ZQCL/ZQCS Refreshing Idle PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE READ WRITE AP READ AP READ Writing READ WRITE WRITE AP Reading READ AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Reading Precharging Automatic sequence Command sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 11 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Functional Description Functional Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Industrial Temperature The industrial temperature (IT) device requires that the case temperature not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when T C exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when T C is < 0°C or >95°C. General Notes • The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). • Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. • The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 12 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Functional Description • Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. • Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. • Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4, x8). • Dynamic ODT has a special use case: when DDR3 devices are architected for use in a single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer to the Dynamic ODT Special Use Case section. • A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: – – – – Connect UDQS to ground via 1kΩ* resistor. Connect UDQS# to V DD via 1kΩ* resistor. Connect UDM to V DD via 1kΩ* resistor. Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1kΩ resistors,* or float DQ[15:8]. *If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT. Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 13 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 2 Gig x 4 Functional Block Diagram ODT control ODT ZQ RZQ ZQCL, ZQCS CKE VSSQ To pull-up/pull-down networks ZQ CAL RESET# Control logic A12 CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Mode registers Refresh counter 16 16 Bank 0 rowaddress latch and decoder 65,536 DLL (1 . . . 4) Bank 0 memory array (65,536 x 512 x 32) 32 READ FIFO and data MUX 4 DQ[3:0] READ drivers BC4 RTT,nom 16,384 BC4 OTF A[15:0] BA[2:0] 19 Address register 3 sw1 RTT(WR) sw2 DM (1, 2) Bank control logic 32 Data interface Column decoder Columnaddress counter/ latch DQS, DQS# VDDQ/2 512 (x32) 12 DQ[3:0] DQS, DQS# VDDQ/2 32 I/O gating DM mask logic sw2 sw1 Sense amplifiers 3 RTT(WR) CK, CK# 16 Rowaddress MUX 19 Columns 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF RTT,nom 4 Data WRITE drivers and input logic 9 RTT,nom sw1 RTT(WR) sw2 DM 3 Columns 0, 1, and 2 CK, CK# Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 14 Column 2 (select upper or lower nibble for BC4) Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Functional Block Diagrams Figure 4: 1 Gig x 8 Functional Block Diagram ODT control ODT ZQ RZQ Control logic CKE VSSQ To ODT/output drivers ZQ CAL RESET# ZQCL, ZQCS A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# OTF Mode registers Refresh counter CK, CK# sw1 (1 . . . 8) 19 Bank 0 Memory array (65,536 x 256 x 64) Bank 0 rowaddress 65,536 latch and decoder 16 16 Sense amplifiers sw2 DLL 16 Rowaddress MUX 64 DQ8 READ FIFO and data MUX 8 19 Address register DQ[7:0] DQS, DQS# VDDQ/2 64 BC4 OTF RTT,nom sw1 RTT(WR) sw2 I/O gating DM mask logic 3 A[15:0] BA[2:0] TDQS# DQ[7:0] Read drivers BC4 16384 RTT(WR) RTT,nom Columns 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 (1, 2) Bank control logic 3 VDDQ/2 (256 x64) 64 8 Data interface Data Column decoder Columnaddress counter/ latch 11 DQS/DQS# Write drivers and input logic RTT,nom sw1 RTT(WR) sw2 8 DM/TDQS (shared pin) 3 Columns 0, 1, and 2 CK, CK# Column 2 (select upper or lower nibble for BC4) Figure 5: 512 Meg x 16 Functional Block Diagram ODT control ODT ZQ RZQ ZQ CAL RESET# Control logic CKE VSSQ To ODT/output drivers ZQCL, ZQCS A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# Mode registers Refresh counter 19 Column 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF 16 16 Bank 0 rowaddress latch and decoder 65,536 DLL (1 . . . 16) 128 READ FIFO and data MUX 16 DQ[15:0] READ drivers LDQS, LDQS#, UDQS, UDQS# BC4 128 18 Address register 3 RTT(WR) sw2 LDQS, LDQS# I/O gating DM mask logic Bank control logic (1 . . . 4) 128 Data interface Column decoder Columnaddress counter/ latch UDQS, UDQS# VDDQ/2 (128 x128) 10 RTT,nom sw1 BC4 OTF 3 DQ[15:0] VDDQ/2 Sense amplifiers A[15:0] BA[2:0] sw2 sw1 Bank 0 memory array (65,536 x 128 x 128) 16,384 RTT(WR) CK, CK# 16 Rowaddress MUX RTT,nom 16 Data WRITE drivers and input logic RTT,nom sw1 RTT(WR) sw2 7 (1, 2) LDM/UDM 3 Columns 0, 1, and 2 CK, CK# Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 15 Column 2 (select upper or lower nibble for BC4) Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 A15 VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS G H J K L M N Notes: 1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 16 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Figure 7: 96-Ball FBGA – x16 (Top View) 1 2 3 VDDQ DQ13 VSSQ 4 5 6 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 A15 VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS A B C D E F G H J K L M N P R T Notes: 1. Ball descriptions listed in Table 4 (page 20) are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 17 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Symbol Type Description A[15:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Command section. BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/ disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 18 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. Description DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. VDD Supply Power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible). VDDQ Supply DQ power supply: 1.35V (1.283–1.45V) /1.5V ±0.075V (backward compatible). Isolated on the device for improved noise immunity. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 19 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions Symbol Type Description A[15:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Command section. BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 20 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type Description RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. VDD Supply Power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible). VDDQ Supply DQ power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible). Isolated on the device for improved noise immunity. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC – External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 21 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions Package Dimensions Figure 8: 78-Ball FBGA – x4, x8 (SN) 0.155 Seating plane A 0.12 A 1.8 CTR Nonconductive overmold 78X Ø0.47 Dimensions apply to solder balls post-reflow on Ø0.42 SMD ball pads. Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N 13.2 ±0.1 9.6 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.28 MIN 9 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 22 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions Figure 9: 96-Ball FBGA – x16 (HA) 0.155 Seating plane A 0.12 A 1.8 CTR Nonconductive overmold 96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N P R T 14 ±0.1 12 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.29 MIN 9 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 23 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 5: Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 1 VDD VDD supply voltage relative to VSS –0.4 1.975 V VDDQ VDD supply voltage relative to VSSQ –0.4 1.975 V VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V 0 95 °C 2, 3 Operating case temperature – Industrial –40 95 °C 2, 3 Storage temperature –55 150 °C TC TSTG Operating case temperature – Commercial Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; IDD2Px must be derated by 30%. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 38 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Electrical Specifications – DC and AC DC Operating Conditions Table 20: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit Notes Supply voltage VDD 1.283 1.35 1.45 V 1–7 I/O supply voltage VDDQ 1.283 1.35 1.45 V 1–7 II –2 – 2 μA IVREF –1 – 1 μA Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Notes: 8, 9 1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ. 2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (for example, 1 second). 4. Under these supply voltages, the device operates to this DDR3L specification. 5. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 6. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device. 7. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see VDD Voltage Switching (page 129)). 8. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. 9. VREF (see Table 21). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 39 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Input Operating Conditions Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit VIN low; DC/commands/address busses VIL VSS N/A See Table 22 V VIN high; DC/commands/address busses VIH See Table 22 N/A VDD V Notes Input reference voltage command/address bus VREFCA(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 1, 2 I/O reference voltage DQ bus VREFDQ(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 2, 3 I/O reference voltage DQ bus in SELF REFRESH VREFDQ(SR) VSS 0.5 × VDD VDD V 4 VTT – 0.5 × VDDQ – V 5 Command/address termination voltage (system level, not direct DRAM input) Notes: 1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (non-common mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (non-common mode) on VREFDQ may not exceed ±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC). 4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. Minimum and maximum values are system-dependent. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 40 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Table 22: DDR3L 1.35V Input Switching Conditions – Command and Address Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866/2133 Units Command and Address 5 160 160 – mV VIH(AC135),min5 135 135 135 mV – – 125 mV VIH(DC90),min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90),min –90 –90 –90 mV Input low AC voltage: Logic 0 VIL(AC125),min5 – – –125 mV VIL(AC135),min5 –135 –135 –135 mV 5 –160 –160 – mV Input high AC voltage: Logic 1 VIH(AC160),min VIH(AC125),min Input high DC voltage: Logic 1 VIL(AC160),min 5 DQ and DM Input high AC voltage: Logic 1 VIH(AC160),min5 160 160 – mV 5 135 135 135 mV 5 – – 130 mV VIH(AC135),min VIH(AC125),min Input high DC voltage: Logic 1 VIH(DC90),min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90),min –90 –90 –90 mV Input low AC voltage: Logic 0 VIL(AC125),min5 VIL(AC135),min – – –130 mV 5 –135 –135 –135 mV 5 –160 –160 – mV VIL(AC160),min Notes: 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 210ps or VIH(AC150),min with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min with tDS(AC160) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 41 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Table 23: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Symbol Min Max Units Notes Differential input logic high – slew VIH,diff(AC)slew 180 N/A mV 4 Differential input logic low – slew VIL,diff(AC)slew N/A –180 mV 4 Differential input logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV 5 Differential input logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC) - VREF) mV 6 VIX VREF(DC) - 150 VREF(DC) + 150 mV 5, 7, 9 VIX (175) VREF(DC) - 175 VREF(DC) + 175 mV 5, 7–9 VDDQ/2 + 160 VDDQ mV 5 VDD/2 + 160 VDD mV 5 VSSQ VDDQ/2 - 160 mV 6 VSS VDD/2 - 160 mV 6 Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# Differential input crossing voltage relative to VDD/2 for CK, CK# Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes Single-ended low level for CK, CK# Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. VSEH VSEL Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ. Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe. Differential input slew rate = 2 V/ns. Defines slew rate reference points, relative to input crossing voltages. Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable. Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. VIX must provide 25mV (single-ended) of the voltages separation. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 42 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 11: DDR3L 1.35V Input Signal VIL and VIH levels with ringback VDD + 0.4V Narrow pulse width VDD Minimum VIL and VIH levels VIH MIN(AC) VIH MIN(DC) VIH(AC) VIH(DC) VIL MIN(DC) VIL MIN(AC) VDDQ VREF + 125/135/160mV VIH(AC) VREF + 90mV VIH(DC) VREF DC MAX + 1% .51 x VDD VREF = VDD/2 .49 x VDD VREF DC MIN - 1% VDD MAX 2% Total VREF DC MAX VREF DC MIN MAX 2% Total VIL(DC) VREFDQ + AC noise VREFDQ + DC error VREFDQ - DC error VREFDQ - AC noise VREF - 90mV VIL(DC) VREF - 125/135/160mV VIL(AC) VIL(AC) 0.0V VSS - 0.40V Narrow pulse width Note: VDDQ + 0.4V Overshoot VSS VSS - 0.40V Undershoot 1. Numbers in diagrams reflect nominal values. Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 43 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC DDR3L 1.35V AC Overshoot/Undershoot Specification Table 24: DDR3L Control and Address Pins Parameter DDR3L-800 DRR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3L-2133 Maximum peak amplitude allowed for overshoot area (see Figure 12) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 13) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD (see Figure 12) 0.67 V/ns 0.5 V/ns 0.4 V/ns 0.33 V/ns 0.28 V/ns 0.25 V/ns Maximum undershoot area below VSS (see Figure 13) 0.67 V/ns 0.5 V/ns 0.4 V/ns 0.33 V/ns 0.28 V/ns 0.25 V/ns Table 25: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins Parameter DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3L-2133 Maximum peak amplitude allowed for overshoot area (see Figure 12) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 13) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD/VDDQ (see Figure 12) 0.25 V/ns 0.19 V/ns 0.15 V/ns 0.13 V/ns 0.11 V/ns 0.10 V/ns Maximum undershoot area below VSS/VSSQ (see Figure 13) 0.25 V/ns 0.19 V/ns 0.15 V/ns 0.13 V/ns 0.11 V/ns 0.10 V/ns Figure 12: Overshoot Maximum amplitude Overshoot area Volts (V) VDD/VDDQ Time (ns) Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 44 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 13: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) Figure 14: VIX for Differential Signals VDD, VDDQ VDD, VDDQ CK#, DQS# CK#, DQS# X VIX VIX VDD/2, VDDQ/2 X X VDD/2, VDDQ/2 VIX X VIX CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ Figure 15: Single-Ended Requirements for Differential Signals VDD or VDDQ VSEH,min VDD/2 or VDDQ/2 VSEH CK or DQS VSEL,max VSEL VSS or VSSQ Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 45 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 16: Definition of Differential AC-Swing and tDVAC tDVAC VIH,diff(AC)min VIH,diff,min CK - CK# DQS - DQS# 0.0 VIL,diff,max VIL,diff(AC)max tDVAC Half cycle Table 26: DDR3L 1.35V – Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback DDR3L-800/1066/1333/1600 tDVAC tDVAC DDR3L-1866/2133 tDVAC tDVAC tDVAC Slew Rate (V/ns) at 320mV (ps) at 270mV (ps) at 270mV (ps) at 250mV (ps) at 260mV (ps) >4.0 189 201 163 168 176 4.0 189 201 163 168 176 3.0 162 179 140 147 154 2.0 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 55 1.2 Note 1 44 5 22 24 1.0 Note 1