AS4C1M16S-C&I
Revision History
Revision
Rev 1.0
Rev 2.0
Details
Preliminary datasheet
Add 166MHZ and commercial & industrial parts.
Date
February 2015
March 2015
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
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Rev. 2.0
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AS4C1M16S-C&I
1M x 16 bit Synchronous DRAM (SDRAM)
Advanced (Rev. 2.0, March /2015)
Features
Overview
The 16Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 16 Mbits. It is
internally configured as a dual 512K word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 512K x 16 bit banks is organized
as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue
for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The SDRAM provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth and particularly well suited
to high performance PC applications
Fast access time: 5.4/5.4ns
Fast clock rate: 166/143 MHz
Self refresh mode: standard
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Industrial Temperature: -40~85°C
JEDEC standard +3.3V0.3V power supply
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
-Pb and Halogen Free
Table 1. Key Specifications
AS4C1M16S-C&I
tCK3
Clock Cycle time(min.)
tAC3
Access time from CLK (max.)
tRAS
Row Active time(min.)
tRC
Row Cycle time(min.)
-6/7
6/7
5.4/5.4
42/42
60/63
Table 2.Ordering Information
Part Number
Frequency Package
AS4C1M16S-7TCN
143MHz
50-Pin TSOPII
AS4C1M16S-6TIN
166MHz
50-Pin TSOPII
AS4C1M16S-6TCN
166MHz
50-Pin TSOPII
Temperature
Commercial
Industrial
Commercial
ns
ns
ns
ns
Temp Range
0~70℃
-40~85℃
0~70℃
T: indicates TSOP II package
C: Commercial
I: Industrial
N: indicates Pb and Halogen Free
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Figure 1 Pin Assignment (Top View)
VDD
1
50
VSS
DQ0
2
49
DQ15
DQ1
3
48
DQ14
VSSQ
4
47
VSSQ
DQ2
5
46
DQ13
DQ3
6
45
DQ12
VDDQ
7
44
VDDQ
DQ4
8
43
DQ11
DQ5
9
42
DQ10
VSSQ
10
41
VSSQ
DQ6
11
40
DQ9
DQ7
12
39
DQ8
VDDQ
13
38
VDDQ
LDQM
14
37
NC
WE#
15
36
UDQM
CAS#
16
35
CLK
RAS#
17
34
CKE
CS#
18
33
NC
A11
19
32
A9
A10/AP
20
31
A8
A0
21
30
A7
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VDD
25
26
VSS
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Figure 2. Block Diagram
CLK
CLOCK
BUFFER
COMMAND
DECODER
A10/AP
COLUMN
COUNTER
2048x256x16
CELL ARRAY
(BANK #0)
CONTROL
SIGNAL
GENERATOR
Column Decoder
DQ0
DQs
Buffer
MODE
REGISTER
~
CS#
RAS#
CAS#
WE#
Row
Decoder
CKE
DQ15
LDQM, UDQM
~
A0
ADDRESS
BUFFER
Row
Decoder
A9
A11
REFRESH
COUNTER
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2048x256x16
CELL ARRAY
(BANK #1)
Column Decoder
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Pin Descriptions
Table 3. Pin Details
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device enters
Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
A11
Input
Bank Activate: A11 (BA) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A10
Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 512K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access
is started by asserting CAS# "LOW." Then, the Read or Write command is
selected by asserting WE# "LOW" or "HIGH."
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK. The
WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
LDQM,
Input
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O
buffer controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is
sampled HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during
a write cycle. Output data is masked (two-clock latency) when LDQM/UDQM is
sampled HIGH during a read cycle. UDQM masks DQ15-DQ8, and LDQM masks
DQ7-DQ0.
UDQM
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DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
VDDQ
Supply
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V 0.3V )
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
Supply
Power Supply: 3.3V 0.3V
VSS
Supply
Ground
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Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table
4 shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
State
CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
Idle(3)
H
X
X
V
V
V
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
V
V
L
V
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
V
V
H
V
L
H
L
L
Read
Active(3)
H
X
V
V
L
V
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
V
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
BankActivate
Burst Stop
OP code
(SelfRefresh)
Clock Suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
Active
Any(5)
H
H
L
X
L
X
X
X
X
X
X
X
Active
L
H
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
X
Note: 1. V=Valid, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by A11 signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
X
Power Down Mode Exit
(PowerDown)
Data Write/Output Enable
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Active
H
X
6
L
X
X
X
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AS4C1M16S-C&I
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", A11 = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BA signals. By latching the
row address on A0 to A10 at the time of this command, the selected row access is initiated. The read
or write operation in the same bank can occur after a time delay of tRCD (min.) from the time of bank
activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by t RC (min.).
The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to
reduce chip area; therefore it restricts the back-to-back activation of the two banks. tRRD (min.)
specifies the minimum time required between activating different banks. After this command is used,
the Write command and the Block Write command perform the no mask write operation.
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Row Addr.
Bank A
Col Addr.
Bank B
Row Addr.
R/W A with
AutoPrecharge
Bank B
Activate
RAS# - CAS# delay(tRCD)
COMMAND
Bank A
Activate
NOP
NOP
Bank A
Row Addr.
RAS# - RAS# delay time(tRRD)
NOP
NOP
Bank A
Activate
RAS# - Cycle time(tRC)
AutoPrecharge
Begin
Don’t Care
Figure 3. BankActivate Command Cycle (Burst Length = n)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by A11 signal. The precharged bank
is switched from the active state to the idle state. This command can be asserted anytime after t RAS
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank
can be active is specified by tRAS (max.). Therefore, the precharge function must be performed in any
active bank within tRAS (max.). At the end of precharge, the precharged bank is still in the idle state
and is ready to be activated again.
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if both
banks are not in the active state. Both banks are then switched to the idle state.
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in
an active bank. The bank must be active for at least tRCD (min.) before the Read command is issued.
During read bursts, the valid data-out element from the starting column address will be available
following the CAS# latency after the issue of the Read command. Each subsequent data-out element
will be valid by the next positive clock edge (refer to the following figure). The DQs go into highimpedance at the end of the burst unless other command is initiated. The burst length, burst
sequence, and CAS# latency are determined by the mode register, which is already programmed. A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
CAS# Latency=2
tCK2, DQ
DOUT A0
CAS# Latency=3
tCK3, DQ
NOP
NOP
NOP
NOP
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
NOP
NOP
DOUT A3
Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank or
the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
READ B
CAS# Latency=2
tCK2, DQ
NOP
DOUT A0
CAS# Latency=3
tCK3, DQ
NOP
NOP
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
NOP
DOUT B3
Figure 5. Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read data
and the Write command (refer to the following three figures). If the data output of the burst read
occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least one
clock prior to the Write command to avoid internal bus contention.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
DQM
COMMAND
NOP
NOP
Bank A
Activate
NOP
CAS# Latency=2
tCK2, DQ
NOP
READ A
WRITE A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
Figure 6. Read to Write Interval (Burst Length 4, CAS# Latency = 2)
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
NOP
READ A
NOP
NOP
CAS# Latency=2
tCK2, DQ
WRITE B
NOP
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
Figure 7. Read to Write Interval (Burst Length 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
NOP
NOP
NOP
CAS# Latency=3
tCK3, DQ
NOP
DOUT A0
WRITE B
NOP
NOP
DIN B0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
Don’t Care
Figure 8. Read to Write Interval (Burst Length ≧ 4, CAS# Latency = 3)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
ADDRESS
Bank
Row
Bank (s)
tRP
COMMAND
READ A
CAS# Latency=2
tCK2, DQ
NOP
NOP
NOP
DOUT A0
CAS# Latency=3
tCK3, DQ
Precharge
NOP
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
NOP
Activate
NOP
DOUT A3
Figure 9. Read to Precharge (CAS# Latency = 2, 3)
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5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {tRP (min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row
in an active bank. The bank must be active for at least tRCD (min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
DQ
WRITE A
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don’t care
NOP
NOP
The first data element and the write
are registered on the same clock edge
Figure 10. Burst Write Operation (Burst Length = 4)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
DQ
NOP
WRITE A
WRITE B
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
NOP
NOP
NOP
Figure 11. Write Interrupted by a Write (Burst Length = 4)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
READ B
CAS# Latency=2
tCK2, DQ
DIN A0
don’t care
CAS# Latency=3
tCK3, DQ
DIN A0
don’t care
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
don’t care
NOP
NOP
NOP
DOUT B3
Input data must be removed from the DQ at
least one clock cycle before the Read data
appears on the outputs to avoid data contention
Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element is
registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the last
data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command
is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DQM
tRP
COMMAND
WRITE
NOP
NOP
Precharge
Bank
Col n
ADDRESS
NOP
NOP
Activate
NOP
ROW
Bank (s)
tWR
DIN
n
DQ
DIN
N+1
Don’t Care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T9
T8
CLK
COMMAND
Bank A
Activate
NOP
NOP
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
Bank A
Activate
tDAL
DQ
DIN A0
tDAL=tWR+tRP
DIN A1
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
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8
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in
the Mode register to make SDRAM useful for a variety of different applications. The default values of
the Mode Register after power-up are undefined; therefore this command must be issued at the
power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the
mode register. Two clock cycles are required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as both banks are in the idle state.
Table 5. Mode Register Bitmap
A11
0
A10
RFU*
A9
WBL
A8
A7
Test Mode
A9
0
1
Write Burst Mode
Burst
Single Bit
A6
A5
A4
CAS# Latency
A3
BT
A8 A7
Test Mode
0
0
Normal
1
0 Vendor Use Only
0
1 Vendor Use Only
A2
A3
0
1
A1
A0
Burst Length
Burst Type
Sequential
Interleave
A6
0
0
0
0
1
A5
A4
CAS# Latency
A2
A1
A0
Burst Length
0
0
Reserved
0
0
0
1
0
1
Reserved
0
0
1
2
1
0
2 clocks
0
1
0
4
1
1
3 clocks
0
1
1
8
0
0
Reserved
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
DQ
tRP
Hi-Z
PrechargeAll
Mode Register
Set Command
Don’t Care
Any
Command
Figure 15. Mode Register Set Cycle
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Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 1, 2, 4, 8, or full page.
Table 6. Burst length
A2
A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Full Page
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential
Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length
of 4 and 8.
Table 7. Addressing Mode Select Field
A3
Addressing Mode
0
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 8. Burst Definition
Burst
Length
2
4
8
A2
X
X
X
X
X
X
0
0
0
0
1
1
1
1
Start Address
A1
A0
X
0
X
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Full page location = 0-255
Confidential
Sequential
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
n, n+1, n+2, n+3, …255, 0,
1, 2, … n-1, n, …
13
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Rev. 2.0
Not Support
March /2015
AS4C1M16S-C&I
CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field. tCAC
(min) CAS# Latency X tCK
Table 9. CAS Latency
A6
A5
A4
CAS# Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2 clocks
0
1
1
3 clocks
1
X
X
Reserved
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
Table 10. Test Mode field
A8
A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
X
Vendor Use Only
Write Burst Length (A9)
This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-Read-Burst-Write
mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected.
Table 11. Write Burst Length
A9
Write Burst Mode
0
Burst-Read-Burst-Write
1
Burst-Read-Single-Write
Note: A11 should stay “L” during mode set cycle.
9
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).
This prevents unwanted commands from being registered during idle or wait states.
10
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command
is only effective in a read/write burst without the auto precharge function. The terminated read burst
ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write
burst is shown in the following figure.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
Burst
Stop
NOP
NOP
NOP
NOP
The burst ends after a delay equal to the CAS# Latency
CAS# Latency=2
tCK2, DQ
DOUT A0
CAS# Latency=3
tCK3, DQ
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Figure 16. Termination of a Burst Read Operation (Burst Length ＞ 4, CAS# Latency =
T0
T1
T2
T3
T4
T5
T6
T7
2, 3)
T8
CLK
COMMAND
DQ
NOP
WRITE A
NOP
NOP
Burst
Stop
DIN A0
DIN A1
DIN A2
don’t care
NOP
NOP
NOP
NOP
Figure 17. Termination of a Burst Write Operation (Burst Length = X)
11
Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and
Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to
the No Operation command.
12
AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto refresh
operation is specified by tRC (min.). To provide the AutoRefresh command, both banks need to be in
the idle state and the device must not be in power down mode (CKE is high in the previous cycle).
This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP (min), must be met before successive auto refresh operations are
performed.
13
SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for
data retention and low power operation. Once the SelfRefresh command is registered, all the inputs
to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh
addressing and timing is internally generated to reduce power consumption. The SDRAM may
remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the
external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
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14
SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or
Device Deselect commands must be issued for tXSR (min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
15
Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
16
Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the
subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. tPDE (min.) is required when the device exits from the PowerDown mode. Any subsequent
commands can be issued after one clock cycle from the end of this command.
17
Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every word
of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output buffers.
LDQM/UDQM is also used for device selection, byte selection and bus control in a memory system.
LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
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Table 12. Absolute Maximum Rating
Symbol
Item
Values
Unit
Note
VIN, VOUT
Input, Output Voltage
- 1.0 ~ 4.6
V
1
VDD, VDDQ
Power Supply Voltage
-1.0 ~ 4.6
V
1
Commercial
0 ~ 70
°C
1
Industrial
-40 ~ 85
°C
1
TA
Ambient Temperature
TSTG
Storage Temperature
- 55 ~ 125
°C
1
TSOLDER
Soldering Temperature
260
°C
1
PD
IOS
Power Dissipation
Short Circuit Output Current
1
50
W
mA
1
1
Table 13. Recommended D.C. Operating Conditions (TA = -40~85°C)
Symbol
Parameter
Min.
Max.
Unit
Note
VDD
Power Supply Voltage
3.0
3.6
V
2
VDDQ
Power Supply Voltage(for I/O Buffer)
3.0
3.6
V
2
VIH
LVTTL Input High Voltage
2.0
VDDQ+0.3
V
2
VIL
LVTTL Input Low Voltage
- 0.3
0.8
V
2
IIL
Input Leakage Current
( 0V VIN VDD, All other pins not under test = 0V )
- 10
10
A
IOZ
Output Leakage Current
Output disable, 0V VOUT VDDQ)
- 10
10
A
VOH
LVTTL Full Drive Output "H" Level Voltage
2.4
－
V
IOUT = -2mA
VOL
LVTTL Full Drive Output "L" Level Voltage
－
0.4
V
IOUT = 2mA
Min.
Max.
Unit
Input Capacitance
2
5
pF
Input/Output Capacitance
4
7
pF
Table 14. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C)
Symbol
CI
CI/O
Parameter
Note: These parameters are periodically sampled and are not 100% tested.
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Table 15. D.C. Characteristics (VDD = 3.3V 0.3V, TA = -40~85°C)
Description/Test condition
Symbol
Operating Current
tRC tRC(min), Outputs Open
One bank active
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# VIH(min), CKE VIH
Input signals are changed every 2clks
Precharge Standby Current in power down mode
tCK = 15ns, CKE VIL(max)
Precharge Standby Current in power down mode
tCK = , CKE VIL(max)
Active Standby Current in non-power down mode
tCK = 15ns, CKE VIH(min), CS# VIH(min)
Input signals are changed every 2clks
Active Standby Current in non-power down mode
CKE VIH(min), CLK VIL(max), tCK =
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
tRC tRC(min)
Self Refresh Current
CKE 0.2V ; for other inputs VIH≧VDD - 0.2V, VIL 0.2V
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18
-6
-7
Max.
Unit Note
IDD1
80
70
IDD2N
25
25
IDD2P
2
2
IDD2PS
2
2
IDD3N
40
40
IDD3NS
35
35
IDD4
110
100
3, 4
IDD5
90
80
3
IDD6
2
2
3
mA
Rev. 2.0
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AS4C1M16S-C&I
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)
Symbol
tRC
-6
A.C. Parameter
-7
Unit Note
Min.
Max.
Min.
Max.
60
-
63
-
9
18
-
21
-
9
18
-
21
-
12
-
14
-
42
100K
42
100K
2
-
2
-
CL* = 2
7.5
-
8
-
CL* = 3
6
-
7
-
tWR
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate
command (same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time
tCK
Clock cycle time
tCH
Clock high time
2.5
-
2.5
-
tCL
Clock low time
2.5
-
2.5
-
tAC
Access time from CLK
(positive edge)
CL* = 2
-
6
-
6.5
CL* = 3
-
5.4
-
5.4
tCCD
CAS# to CAS# Delay time
1
-
1
-
tOH
Data output hold time
2
-
2
-
tLZ
Data output low impedance
1
-
1
-
tHZ
Data output high impedance
-
5.4
-
5.4
tIS
Data/Address/Control Input set-up time
2
-
2
-
11
tIH
Data/Address/Control Input hold time
0.8
-
0.8
-
11
tPDE
PowerDown Exit set-up time
tIS+tCK
-
tIS+tCK
-
tCK
tREFI
Refresh Interval Time
-
15.6
-
15.6
s
tXSR
Exit Self-Refresh to any Command
tRC+tIS
-
tRC+tIS
-
ns
tRCD
tRP
tRRD
tRAS
ns
9
9
tCK
10
ns
11
tCK
10
ns
8
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns.VIL (Min) = -1.0V for pulse
width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
6. A.C. Test Conditions
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Table 17. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2KΩ
Output
Output
30pF
Z0=50Ω
870Ω
Figure 18.1 LVTTL D.C. Test Load (A)
30pF
Figure 18.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11. Assumed input rise and fall time tT (tR & tF) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 s, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command.
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Timing Waveforms
Figure 19. AC Parameters for Write Timing (Burst Length=4)
T0
CLK
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCH
tCL
CKE
tIS
tIS
Begin Auto
Precharge Bank A
tIH
Begin Auto
Precharge Bank B
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RAx
RBx
RAy
tIS
A0-A9
RAx
CAx
RBx
CBx
RAy
CAy
DQM
tRCD
tDAL
tIS
tRC
DQ
Ax0
Activate
Command
Bank A
Ax1
Write with
Auto Precharge
Command
Bank A
Ax2
Activate
Command
Bank B
tWR
tIH
Hi-Z
Ax3
Bx0
Bx1
Write with
Auto Precharge
Command
Bank B
Bx2
Bx3
Ay0
Activate
Command
Bank A
Write
Command
Bank A
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Don’t Care
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Figure 20. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
CLK
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
tCH tCL
CKE
tIS
Begin Auto
Precharge Bank B
tIS
tIH
tIH
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RAx
RBx
RAy
tIS
A0-A9
RAx
CAx
RBx
CBx
RAy
tRRD
tRAS
DQM
tRC
tAC
tRCD
DQ
Hi-Z
tRP
tHZ
tLZ
Ax0
Ax1
Bx0
Bx1
tHZ
tOH
Activate
Command
Bank A
Read
Command
Bank A
Read with
Precharge
Auto Precharge Command
Command
Bank A
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Don’t Care
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Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
tRP
tRC
tRC
CAx
tRCD
DQM
DQ
Ax0
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Ax1
Read
Command
Bank A
Don’t Care
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Figure 22. Power on Sequene and Auto Refresh
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
Is reguired
Minimum for 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
DQ
tRP
tMRD
Hi-Z
Precharge All
Command
Inputs must be
Stable for
200μs
1st Auto Refresh(*)
Command
2nd Auto Refresh(*)
Command
Mode Register
Set Command
Any
Command
Don’t Care
Note(*): The Auto Refresh command can be issue before or after Mode Register Set command
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Figure 23. Self Refresh Entry & Exit Cycle
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
*Note 2
CKE
tXSR
*Note 5
*Note 1
*Note 8
*Note 3,4
tPDE
tIS tIH
*Note 6
tIS
*Note 7
CS#
RAS#
*Note 9
CAS#
WE#
A11
A10
A0-A9
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Exit
Self Refresh Entry
Auto Refresh
Don’t Care
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
5.
6.
7.
8.
9.
To Exit SelfRefresh Mode
System clock restart and be stable before returning CKE high.
Enable CKE and CKE should be set high for valid setup time and hold time.
CS# starts from high.
Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Confidential
25
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 24.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
tHZ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Clock Suspend
1 Cycle
Ax2
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Don’t Care
Confidential
26
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 24.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
tHZ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Don’t Care
Confidential
27
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 25. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Activate
Command
Bank A
Confidential
DAx1
Clock Suspend
1 Cycle
Write
Command
Bank A
DAx2
DAx3
Clock Suspend
3 Cycles
Clock Suspend
2 Cycles
Don’t Care
28
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 26. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
CLK
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tIH tIS
tPDE
CKE
Valid
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
tHZ
Hi-Z
Ax0
ACTIVE
Activate
Read
STANDBY
Command
Command
Bank A
Bank A
Power
Down
Power Down
Mode Exit
Mode Entry
Confidential
Ax1
Ax2
Clock Suspension
Start
Ax3
Clock Suspension
End
Precharge
Command
Bank A
Power Down
Mode Entry
29
Rev. 2.0
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Command
Don’t Care
March /2015
AS4C1M16S-C&I
Figure 27.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
A0-A9
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Aw2
Aw3
Read
Command
Bank A
Ax0
Ax1
Read
Command
Bank A
Ay0
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Az0
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
Confidential
30
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 27.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
A0-A9
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Aw2
Read
Command
Bank A
Aw3
Ax0
Read
Command
Bank A
Ax1
Ay0
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
Confidential
31
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 28. Random Column Write (Page within same Bank)
(Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
A0-A9
RBw
RBz
CBw
CBx
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0
Activate
Command
Bank B
Write
Command
Bank B
DBx1
Write
Command
Bank B
DBy0 DBy1 DBy2
Write
Command
Bank B
DBy3
DBz0
Precharge
Command
Bank B
Activate
Command
Bank B
DBz1
Write
Command
Bank B
Don’t Care
Confidential
32
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 29.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
A0-A9
RBx
CBx
RBy
RAx
CAx
RBy
tAC
tRCD
DQM
DQ
RAx
CBy
tRP
Hi-Z
Bx0
Activate
Command
Bank B
Confidential
Read
Command
Bank B
Bx1
Bx2
Bx3
Bx4
Bx5
Activate
Command
Bank A
33
Bx6
Bx7
Ax0
Read
Command
Bank A
Precharge
Command
Bank B
Ax1
Ax2
Ax3
Activate
Command
Bank B
Ax4
Ax5
Ax6
Ax7
Read
Command
Bank B
Don’t Care
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 29.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
A0-A9
RBx
CBx
RBy
RAx
CAx
RBy
tAC
tRCD
DQM
DQ
RAx
CBy
tRP
Hi-Z
Bx0
Activate
Command
Bank B
Read
Command
Bank B
Bx1
Bx2
Bx3
Bx4
Activate
Command
Bank A
Bx5
Bx6
Read
Command
Bank A
Bx7
Ax0
Precharge
Command
Bank B
Ax1
Ax2
Ax3
Activate
Command
Bank B
Ax4
Ax5
Ax6
Read
Command
Bank B
Ax7
By0
Precharge
Command
Bank A
Don’t Care
Confidential
34
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 30. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
RAy
RBx
CBx
tRCD
DQM
DQ
RBx
RAy
tWR*
CAy
tRP
tWR*
Hi-Z
DAx0
Activate
Command
Bank A
DAx1 DAx2 DAx3
Write
Command
Bank A
DAx4
DAx5 DAx6
DAx7
Activate
Command
Bank B
DBx0
DBx1 DBx2 DBx3
Write
Command
Bank B
Precharge
Command
Bank A
DBx4
DBx5 DBx6
Activate
Command
Bank A
DAy0
DAy1 DAy2
Write
Command
Bank A
DAy3
Precharge
Command
Bank B
Don’t Care
*tWR>tWR (min.)
Confidential
DBx7
35
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 31.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Ax1
Ax2
Ax3
Read
Command
Bank A
DAy0 DAy1
Write
Command
Bank A
DAy3
The Write Data
is Masked with a
Zero Clock
Latency
Az0
Read
Command
Bank A
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Don’t Care
Confidential
36
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 31.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Confidential
Ax1
Ax2
Ax3
Read
Command
Bank A
DAy0 DAy1
Write
Command
Bank A
37
DAy3
The Write Data
is Masked with a
Zero Clock
Read
Latency
Command
Bank A
Rev. 2.0
Az0
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Don’t Care
March /2015
AS4C1M16S-C&I
Figure 32.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
T5 T6
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAy
RBx
CBw
CBx
Ax3
Bw0
CBy
CAy
CBz
tRCD
DQM
tAC
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Activate
Command
Bank B
Ax2
Read
Command
Bank B
Bw1
Read
Command
Bank B
Bx0
Bx1
Read
Command
Bank B
By0
By1
Read
Command
Bank A
Ay0
Ay1
Read
Command
Bank B
Bz0
Bz1
Precharge
Command
Bank A
Bz2
Bz3
Precharge
Command
Bank B
Don’t Care
Confidential
38
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 32.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBx
CBx
CBy
CBz
CAy
tRCD
DQM
tAC
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Confidential
Read
Command
Bank A
Activate
Command
Bank B
Ax1
Ax2
Read
Command
Bank B
Ax3
Bx0
Read
Command
Bank B
Bx1
By0
Read
Command
Bank B
By1
Bz0
Read
Command
Bank A
Bz1
Ay0
Precharge
Command
Bank B
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Don’t Care
39
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 33. Interleaved Column Write Cycle (Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CAy
CBz
tWR
tRCD
tWR
DQM
tRRD>tRRD (min)
DQ
Hi-Z
DAx0
Activate
Command
Bank A
Confidential
DAx1
DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
40
DBy1
Write
Command
Bank B
DAy0 DAy1 DBz0
Write
Command
Bank A
DBz1
DBz2
Write
Command
Bank B
Precharge
Command
Bank A
Rev. 2.0
DBz3
Precharge
Command
Bank B
Don’t Care
March /2015
AS4C1M16S-C&I
Figure 34.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
High
Begin Auto
Precharge
Bank A
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBx
CAx
RBy
RBx
CBx
CAy
RBy
CBy
RAz
tRP
DQM
DQ
RAz
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Activate
Command
Bank B
Ax2
Ax3
Bx0
Read with
Auto Precharge
Command
Bank B
Bx1
Bx2
Bx3
Read with
Auto precharge
Command
Bank A
Ay0
Ay1
Ay2
Activate
Command
Bank B
Ay3
By0
By1
By2
Read with
Activate
Auto Precharge Command
Command
Bank A
Bank B
Don’t Care
Confidential
41
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 34.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
CBy
tRP
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Confidential
Read
Command
Bank A
Activate
Command
Bank B
Ax1
Ax2
Ax3
Bx0
Read with
Auto Precharge
Command
Bank B
Bx1
Bx2
Read with
Auto Precharge
Command
Bank A
Bx3
Ay0
Ay1
Ay2
Activate
Command
Bank B
Ay3
By0
By1
By2
Read with
Auto Precharge
Command
Bank B
Don’t Care
42
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 35. Auto Precharge after Write Burst (Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
CBy
tDAL
DQM
DQ
Hi-Z
DAx0 DAx1
Activate
Command
Bank A
Confidential
DAx2
Write
Command
Bank A
Activate
Command
Bank B
DAx3
DBx0 DBx1 DBx2
DBx3
Write with
Auto Precharge
Command
Bank B
DAy0 DAy1 DAy2
Write with
Auto Precharge
Command
Bank A
DAy3
DBy0 DBy1 DBy2
Activate
Command
Bank B
DBy3
Write with
Auto Precharge
Command
Bank B
Don’t Care
43
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 36.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBy
RBx
CAx
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Ax
Activate
Command
Bank A
Read
Command
Bank A
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Bx+4
The burst counter wraps
Activate
Read
Command from the highest order
Command
page
address
back
to
zero
Bank B
Bank B
during this time interval
44
Bx+6
Precharge
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
Bx+5
Rev. 2.0
Burst Stop
Command
Activate
Command
Bank B
Don’t Care
March /2015
AS4C1M16S-C&I
Figure 36.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBy
RBx
CAx
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Ax
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Read
Command
Bank B
Bx+4
Bx+5
Precharge
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Activate
Command
Bank B
Don’t Care
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
45
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 37. Full Page Write Cycle (Burst Length=Full Page)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RBy
RBx
CAx
RBx
CBx
RBy
DQM
Data is ignored
DQ
Hi-Z
DAx
Activate
Command
Bank A
Confidential
DAx+1
Write
Command
Bank A
DAx+2
DAx+3
DAx-1
DAx
DAx+1
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
DBx
DBx+1
DBx+2
DBx+3
DBx+4
DBx+5
Write
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
46
Precharge
Command
Bank B
Burst Stop
Command
Rev. 2.0
Activate
Command
Bank B
Don’t Care
March /2015
AS4C1M16S-C&I
Figure 38. Byte Read and Write Operation (Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
CAy
CAz
LDQM
UDQM
DQ0-DQ7
Ax0
DQ8-DQ15
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax1
Ax2
Upper Byte
is masked
DAy1
Ax3
Lower Byte
is masked
DAy0
DAy1
Write
Command
Bank A
Day2
DAy3
Upper Byte
is masked
Az0
Read
Command
Bank A
Az1
Az2
Az1
Az2
Lower Byte
is masked
Az3
Lower Byte
is masked
Don’t Care
Confidential
47
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 39. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
High
Begin Auto
Precharge
Bank A
CS#
RAS#
CAS#
WE#
A11
A10
RBu
A0-A9
RBu
RAu
CBu
RAu
CAu
RBw
RAv
RBv
RBv
CBv
tRP
RAv
CAv
RBw
tRP
tRP
DQM
DQ
Bu0
Activate
Command
Bank B
Confidential
Activate
Command
Bank A
Read
Bank B
with Auto
Precharge
Bu1
Bu2
Bu3
Read
Bank A
with Auto
Precharge
Au0
Au1
Au2
Activate
Command
Bank B
48
Au3
Bv0
Bv1
Activate
Command
Bank A
Read
Bank B
with Auto
Precharge
Bv2
Bv3
Read
Bank A
with Auto
Precharge
Av0
Av1
Av2
Av3
Activate
Command
Bank B
Don’t Care
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 40. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
A0-A9
RAx
RBx
RBw
CAx
CBx
CBy
CAy
CAz
CBz
RBw
tRP
DQM
tRRD
DQ
tRCD
Hi-Z
Ax0
Activate
Command
Bank A
Confidential
Ax1
Bx0
Activate
Read
Command
Command
Bank B
Bank B
Read
Read
Command
Command
Bank A
Bank A
Ay0
Ay1
Read
Command
Bank B
By0
By1
Read
Command
Bank A
Az0
Az1
Az2
Read
Command
Bank B
Bz0
Bz1
Bz2
Precharge
Activate
Command Bank B
Command
(Precharge Temination) Bank B
Don’t Care
49
Rev. 2.0
March /2015
AS4C1M16S-C&I
Figure 41. Full Page Random Column Write (Burst Length=Full Page)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
A0-A9
RAx
RBx
RBw
CAx
CBx
CBy
CAy
CAz
CBz
RBw
tWR
tRP
DQM
tRRD
DQ
tRCD
Hi-Z
DAx0 DAx1
Activate
Command
Bank A
Confidential
Activate
Command
Bank B
Write
Command
Bank A
DBx0
DAy0
DAy1 DBy0 DBy1
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
DAz0
DAz1
Write
Command
Bank A
DAz2
DBz0
DBz1
DBz2
Write
Command
Bank B
Precharge
Activate
Command Bank B
Command
(Precharge Temination) Bank B
Write Data
are masked
50
Rev. 2.0
Don’t Care
March /2015
AS4C1M16S-C&I
Figure 42. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
RAy
CAx
RAy
tWR
RAz
CAy
RAz
tRP
tRP
DQM
DQ
DAx0 DAx1
Activate
Command
Bank B
Confidential
Precharge
Write
Command
Command
Bank A
Bank A
Precharge Termination
of a Write Burst
Write Data are masked
Ay0
Activate
Command
Bank A
Read
Command
Bank A
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Precharge Termination
of a Read Burst
Don’t Care
51
Rev. 2.0
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AS4C1M16S-C&I
Figure 43. 50 Pin TSOP II Package Outline Drawing Information
50
HE
E
0.254
26
L
L1
1
25
S
Symbol
B
e
L
L1
y
Dimension in inch
Min
Normal
Max
0.047
－
－
0.002
0.005
0.008
0.035
0.039
0.043
0.008
0.018
－
0.006
－
－
0.82
0.825
0.83
0.395
0.400
0.405
0.031
－
－
Min
－
0.05
0.9
0.2
－
20.82
10.03
－
A
A1
A2
B
c
D
E
e
0.455
0.463
0.471
11.56
HE
0.016
0.020
0.024
0.40
L
0.0315
－
－
－
L1
0.035
－
－
－
S
0.004
－
－
－
y
－
0
8
0
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension: mm
Confidential
C
A1 A2
A
D
52
Dimension in mm
Normal
－
0.125
1.0
－
0.155
20.95
10.16
0.80
Max
1.20
0.20
1.1
0.45
－
21.08
10.29
－
11.76
0.50
0.80
0.88
－
－
11.96
0.60
－
－
0.10
8
Rev. 2.0
March /2015
AS4C1M16S-C&I
PART NUMBERING SYSTEM
AS4C
DRAM
1M16S
1M16=1Mx16
S=SDRAM
6/7
6=166MHz
7=143MHz
T
C/I
N
T = TSOP II
C=Commercial
(0° C～70° C)
I=Industrial
(-40° C～85° C)
Indicates Pb and
Halogen Free
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt
are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and
its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in
this document. The data contained herein represents Alliance's best data and/or estimates at the time of
issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers
and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer.
Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance
products including liability or warranties related to fitness for a particular purpose, merchantability, or
infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
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property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
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significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies
that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising
from such use.
Confidential
53
Rev. 2.0
March /2015
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