AS4C32M16SA-7TCNTR

AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 512Mbit Single-Data-Rate (SDR) SDRAM AS4C32M16SA-7TCN & AS4C32M16SA-7TIN AS4C32M16SA-7CN & AS4C32M16SA-7IN 32Mx16 (8M x 16 x 4 Banks) $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV REVISION HISTORY Rev. 1.0 March 2012 initial version Rev. 1.1 April 2012 Revised Operating-; Standby- and Refresh Currents Rev. 2.0 February 2014 Die Shrink – A revision ZĞǀ͘ϯ͘ϬƉƌŝůϮϬϭϱ ĚĚ'ŽƉƚŝŽŶ Rev. 4.0 March 2016 Correcting errors: Page 3 transfer rates up to 166 MHz ===> transfer rates up to 143MHz Page 4 data transfer rates up to 166 MHz =====> data transfer rates up to 143 MHz data rate of up to 166 MHz=========>data rate of upto 143 MHz Page 5 - pin labelling errors I/O1 ==> DQ0 I/O16 ==> DQ15 Page 6 = pin labelling errors VDD===> VCC VDDQ===> VCCQ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Overview This section gives an overview of the 512M SDRAM product and describes its main characteristics. Features    4 banks x 8Mbit x 16 organization High speed data transfer rates up to 143 MHz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge               Single Pulsed RAS Interface Data Mask for Read/Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential Type 1, 2, 4, 8 for Interleave Type Multiple Burst Read with Single Write Operation Automatic and Controlled Pre-charge Command Random Column Address every CLK (1-N Rule) Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 8192 cycles/64 ms Available in 54 Pin TSOP II Available in 54 Ăůů&' II LVTTL Interface Single +3.3 V ±0.3 V Power Supply ROHS Compliant*    $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Table 1 - Performance Table -7 6\VWHP)UHTXHQF\I&. 0+] &ORFN&\FOH7LPHW&. QV &ORFN$FFHVV7LPHW$&&$6/DWHQF\  QV &ORFN$FFHVV7LPHW$&&$6/DWHQF\  QV Description The AS4C32M16SA is a four bank Synchronous DRAM organized as 4 banks x 8Mbit x 16. The AS4C32M16SA achieves high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an inter-leaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device. Table 2 – Ordering Information for ROHS Compliant Products Product part No Org Temperature Max Clock (MHz) Package AS4C32M16SA-7TCN 32M x 16 Commercial 0¡C to 70¡C 143 54pin TSOP II AS4C32M16SA-7TIN 32M x 16 Industrial -40¡C to 85¡C 143 54pin TSOP II AS4C32M16SA-7BCN 32M x 16 Commercial 0¡C to 70¡C 143 54 Ball FBGA AS4C32M16SA-7BIN 32M x 16 Industrial -40¡C to 85¡C 143 54 Ball FBGA $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 3LQ3ODVWLF7623,, [3,1&21),*85$7,21 7RS9LHZ VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 3LQ1DPHV VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS CLK Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable A0–A12 Address Inputs BA0, BA1 Bank Select DQ0–DQ15 Data Input/Output LDQM, UDQM Data Mask VCC Power (+3.0V~3.3V) VSS Ground VCCQ Power for I/O’s (+3.0V~3.3V) VSSQ Ground for I/O’s NC Not connected 356164V-01 $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV %$//)%*$ [3,1&21),*85$7,21 7RS9LHZ 3LQ1DPHV configuration for x 16 devices: 1 V
S
S 2 3 7 8 9 CLK Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQ15
VS
S
Q A VCCQ
DQ14 DQ13
VCCQ B VS
S
Q
DQ2
DQ1 A0–A12 Address Inputs DQ12 DQ11
VS
S
Q C VCCQ
DQ4
BA0, BA1 Bank Select DQ10 D VS
S
Q
DQ6
DQ5 DQ0–DQ15 Data Input/Output V
S
S E VCC
LDQM
DQ7 LDQM, UDQM Data Mask C
K
E F C
AS
RAS
WE VCC Power (+3.0V~3.3V) VSS Ground VCCQ Power for I/O’s (+3.0V~3.3V) VSSQ Ground for I/O’s NC Not connected DQ8 DQ9
VCCQ NC
UDQM C
LK
DQ0
VCC DQ3 A12 A11 A9 G BA0
BA1
C
S A8 A7 A6 H A0 A1 A10 V
S
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VCC $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV &DSDFLWDQFH $EVROXWH0D[LPXP5DWLQJV (at Ta=0 to 25 °C, VCC = VCCQ = 3.3 V ± 0.3 V) Operating temperature range..........0 to 70 °C for normal -40 to 85 °C for Industrial Storage temperature range .........................-55 to 150 °C Input/output voltage ........................... -0.3 to (VCC+0.3) V Power supply voltage ................................... -0.3 to 4.6 V Power dissipation ...................................................... 1 W Data out current (short circuit) ............................... 50 mA 3DUDPHWHU 6\PERO 0LQ 0D[ 8QLW Input Capacitance: CLK CCLK Input Capacitance: All other input CIN pins and balls Input/output Capacitance: DQ CIO 4.5 6 pF 2.5 6 pF 4 6 pF 1RWH *1RWHCapacitance is sampled and not 100% tested. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. %ORFN'LDJUDP [&RQILJXUDWLRQ Row Addresses Column Addresses A0 - A9, AP, BA0, BA1 Row address buffer Column address buffer Refresh Counter Row decoder Row decoder Memory array Memory array Memory array Memory array Bank 0 8192 x 1024 x 16 bit Bank 1 8192 x 1024 x16 bit Input buffer Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Column address counter A0 - A12, BA0, BA1 Bank 2 8192 x 1024 x 16 bit Output buffer Bank 3 8192 x 1024 x 16 bit Control logic & timing generator UDQM LDQM WE CAS RAS CS CKE CLK DQ0 - DQ15 $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 6LJQDO3LQ'HVFULSWLRQ 3LQ 7\SH 6LJQDO 3RODULW\ )XQFWLRQ CLK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A12 Input Level — During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: • 64M x 8 SDRAM CA0–CA9, CA11. • 32M x 16 SDRAM CA0–CA9. In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input Level — Selects which bank is to be active. DQx Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. LDQM UDQM Input Pulse VCC, VSS Supply VCCQ VSSQ Supply Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the input buffers and the core logic. — — Isolated power supply and ground for the output buffers to provide improved noise immunity. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 2SHUDWLRQ'HILQLWLRQ All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the thruth table for the operation commands. 2SHUDWLRQ Row Activate 'HYLFH 6WDWH &.( Q &.( Q &6 5$6 &$6 :( Idle3 $ $ '40 $ $ %6 %6 H X L L H H X V V V 3 H X L H L H X V L V Read w/Autoprecharge Active 3 H X L H L H X V H V Write Active3 H X L H L L X V L V Write with Autoprecharge Active3 H X L H L L X V H V Row Precharge Any H X L L H L X X L V Precharge All Any H X L L H L X X H X Mode Register Set Idle H X L L L L X V V V No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Auto Refresh Idle H H L L L H X X X X Self Refresh Entry Idle H L L L L H X X X X Idle (Self Refr.) H X X X L H L H H X X X X X Idle Active4 H X X X H L L H H X X X X X Any (Power Down) H X X X L H L H H L X X X X Data Write/Output Enable Active H X X X X X L X X X Data Write/Output Disable Active H X X X X X H X X X Read Self Refresh Exit Power Down Entry Power Down Exit Active 1RWHV 1. V = Valid , x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. These are state of bank designated by BS0, BS1 signals. 4. Power Down Mode can not entry in the burst cycle. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Power On and Initialization 7KHGHIDXOWSRZHURQVWDWHRIWKHPRGHUHJLVWHULVVXSSOLHUVSHFLILFDQGPD\EHXQGHILQHG7KHIROORZLQJSRZHURQDQG LQLWLDOL]DWLRQVHTXHQFHJXDUDQWHHVWKHGHYLFHLVSUHFRQGLWLRQHGWRHDFKXVHU¶VVSHFLILFQHHGV/LNHDFRQYHQWLRQDO'5$0 WKH 6\QFKURQRXV '5$0 PXVW EH SRZHUHG XS DQG LQLWLDOL]HG LQ D SUHGHILQHG PDQQHU 'XULQJ SRZHU RQ DOO 9&& DQG 9&&4SLQVPXVWEHEXLOWXSVLPXOWDQHRXVO\WRWKHVSHFLILHGYROWDJHZKHQWKHLQSXWVLJQDOVDUHKHOGLQWKH³123´VWDWH 7KH SRZHURQ YROWDJH PXVW QRW H[FHHG 9&&9 RQ DQ\ RI WKH LQSXW SLQV RU9&&VXSSOLHV 7KH &/. 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1, 0 8 000 001 010 011 100 101 110 111 Full Page nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 Cn, Cn+1, Cn+2.... 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 not supported 5HIUHVK0RGH SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -beforeRAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. '40)XQFWLRQ DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). 3RZHU'RZQ In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for mode entry and exit. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $XWR3UHFKDUJH Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the 5HDGZLWK$XWR3UHFKDUJH function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CA10 is high when a Write Command is issued, the :ULWHZLWK$XWR3UHFKDUJH function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in. $XWR3UHFKDUJH does not apply to full-page burst mode. 3UHFKDUJH&RPPDQG There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3. Writes require a time delay twr from the last data out to apply the precharge command. A full-page burst may be truncated with a Precharge command to the same bank. Bank Selection by Address Bits: A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 X X all Banks %XUVW7HUPLQDWLRQ Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the I/O pins before the Burst Stop Command is registered will be written to the memory. The full-page burst is used in conjunction with Burst Terminate Command to generate arbitrary burst lengths. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Recommended Operation and Characteristics for LV-TTL 966 99&&9&&4 9“9 Limit Values Parameter min. max. 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Write Cycle   W W :5 '4: $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Notes for AC Parameters:  )RUSURSHUSRZHUXSVHHWKHRSHUDWLRQVHFWLRQRIWKLVGDWDVKHHW  $&WLPLQJWHVWVKDYH9,/ 9DQG9,+ 9ZLWKWKHWLPLQJUHIHUHQFHGWRWKH9FURVVRYHUSRLQW7KH WUDQVLWLRQWLPHLVPHDVXUHGEHWZHHQ9,+DQG9,/$OO$&PHDVXUHPHQWVDVVXPHW7 QVZLWKWKH$&RXWSXW ORDGFLUFXLWVKRZQLQ)LJXUH W&. 9,+ &/. 9 9,/ W,6 W7 W,+ 2KP 9 &200$1' = 2KP W$& W/= ,2 W$& S) W2+ 9 287387 W+= Figure 1.  ,IFORFNULVLQJWLPHLVORQJHUWKDQQVDWLPHW7±QVKDVWREHDGGHGWRWKLVSDUDPHWHU  ,IW7LVORQJHUWKDQQVDWLPHW7±QVKDVWREHDGGHGWRWKLVSDUDPHWHU  7KHVH SDUDPHWHU DFFRXQW IRU WKH QXPEHU RI FORFN F\FOH DQG GHSHQG RQ WKH RSHUDWLQJ IUHTXHQF\ RI WKH FORFNDVIROORZV the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6HOI5HIUHVK([LWLVDV\QFKURQRXVRSHUDWLRQDQGEHJLQVRQWKHQGSRVLWLYHFORFNHGJHDIWHU&.(UHWXUQV KLJK 6HOI 5HIUHVK ([LW LV QRW FRPSOHWH XQWLO D WLPH SHULRG HTXDO WR W5& LV VDWLVILHG RQFH WKH 6HOI 5HIUHVK ([LW FRPPDQGLVUHJLVWHUHG  5HIHUHQFHG WR WKH WLPH ZKLFK WKH RXWSXW DFKLHYHV WKH RSHQ FLUFXLW FRQGLWLRQ QRW WR RXWSXW YROWDJH OHYHOV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 7LPLQJ'LDJUDPV 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a Burst Write Operation 8.2 Termination of a Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Power Down Mode 13. Self Refresh (Entry and Exit) 14. Auto Refresh (CBR) $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 7LPLQJ'LDJUDPV(Cont’d) 15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst 19.1 CAS Latency = 2 19.2 CAS Latency = 3 20. Full Page Burst Operation 20.1 Full Page Burst Read, CAS Latency = 2 20.2 Full Page Burst Read, CAS Latency = 3 21. Full Page Burst Operation 21.1 Full Page Burst Write, CAS Latency = 2 21.2 Full Page Burst Write, CAS Latency = 3 $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV  %DQN$FWLYDWH&RPPDQG&\FOH &$6ODWHQF\  T0 T1 T T T CLK T T .......... ADDRESS Bank A Col. Addr. Bank A Row Addr. Bank A Row Addr. Bank B Row Addr. .......... tRCD COMMAND Bank A Activate tRRD NOP Write A with Auto Precharge NOP : “H” or “L” Bank B Activate .......... Bank A Activate NOP tRC  %XUVW5HDG2SHUDWLRQ %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s READ A NOP NOP DOUT A0 NOP NOP DOUT A1 DOUT A0 DOUT A2 DOUT A1 NOP NOP NOP NOP DOUT A3 DOUT A2 DOUT A3 $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV  5HDG,QWHUUXSWHGE\D5HDG %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK tCCD COMMAND READ A READ B CAS latency = 2 NOP DOUT A0 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 T3 T4 T5 NOP NOP DOUT B3 5HDGWR:ULWH,QWHUYDO %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T6 T7 T8 CLK Minimum delay between the Read and Write Commands = 4+1 = 5 cycles tDQW DQM COMMAND I/O’s tDQZ NOP READ A NOP NOP NOP NOP WRITE B DIN B0 DOUT A0 NOP NOP DIN B1 DIN B2 Must be Hi-Z before the Write Command : “H” or “L” $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 0LQLPXP5HDGWR:ULWH,QWHUYDO %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK tDQW DQM tDQZ 1 Clk Interval COMMAND NOP NOP BANK A ACTIVATE NOP READ A WRITE A NOP NOP NOP DIN A1 DIN A2 DIN A3 Must be Hi-Z before the Write Command CAS latency = 2 DIN A0 tCK2, I/O’s : “H” or “L” 1RQ0LQLPXP5HDGWR:ULWH,QWHUYDO %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP DIN B0 DIN B1 DIN B2 DIN B0 DIN B1 DIN B2 CLK tDQW DQM tDQZ COMMAND CAS latency = 2 tCK1, I/O’s CAS latency = 3 tCK2, I/O’s NOP READ A NOP NOP DOUT A0 READ A NOP WRITE B DOUT A1 Must be Hi-Z before the Write Command DOUT A0 : “H” or “L” $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV  %XUVW:ULWH2SHUDWLRQ %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP I/O’s WRITE A DIN A0 NOP NOP NOP DIN A1 DIN A2 DIN A3 The first data element and the Write are registered on the same clock edge. NOP NOP NOP NOP don’t care Extra data is ignored after termination of a Burst. :ULWH,QWHUUXSWHGE\D:ULWH %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK tCCD COMMAND NOP WRITE A WRITE B NOP NOP NOP DIN B1 DIN B2 DIN B3 NOP NOP NOP 1 Clk Interval I/O’s DIN A0 DIN B0 $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV :ULWH,QWHUUXSWHGE\D5HDG %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 WRITE A READ B T4 T5 T6 T7 T8 CLK COMMAND NOP CAS latency = 2 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s DIN A0 don’t care DIN A0 don’t care NOP NOP DOUT B0 don’t care NOP NOP NOP NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the I/O’s at least one clock cycle before the Read dataAPpears on the outputs to avoid data contention. %XUVW:ULWHZLWK$XWR3UHFKDUJH %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND BANK A ACTIVE NOP NOP WRITE A Auto-Precharge NOP NOP t WR I/O’s DIN A0 DIN A1 * NOP NOP * NOP tRP Begin Autoprecharge Bank can be reactivated after trp $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV %XUVW5HDGZLWK$XWR3UHFKDUJH %XUVW/HQJWK &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s READ A NOP NOP DOUT A0 NOP DOUT A1 DOUT A0 NOP * NOP NOP NOP tRP DOUT A2 * NOP DOUT A1 DOUT A3 tRP DOUT A2 DOUT A3 * Begin Autoprecharge Bank can be reactivated after tRP $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 7HUPLQDWLRQRID%XUVW5HDG2SHUDWLRQ &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS latency = 2 tCK2, I/O’s NOP NOP Burst Stop DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 CAS latency = 3 tCK3, I/O’s NOP NOP NOP NOP DOUT A3 7HUPLQDWLRQRID%XUVW:ULWH2SHUDWLRQ &$6ODWHQF\  T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2,3 I/O’s NOP WRITE A DIN A0 NOP NOP DIN A1 DIN A2 Burst Stop NOP NOP NOP NOP don’t care Input data for the Write is masked. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6  I/O DQM Addr AP BS WE CAS RAS CS CKE CLK Hi-Z tCH tIS tCKS 7 7 tCK2 tRCD tIH tIH tIS tIH tIS 7 Ax0 CAx 7 Ax1 7 Ax2 tRC RBx RBx 7 Ax3 7 Bx0 CBx 7 7 Bx1 Bx2 RAy RAy Bx3 tDS Begin Auto Precharge Bank A 7 Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B RAx RAx tCL 7 $&3DUDPHWHUVIRU:ULWH7LPLQJ 7 7 Ay1 tDH Ay2 Ay3 Begin Auto Precharge Bank B 7 Write Command Bank A Ay0 RAy 7 7 tDPL tRP 7 Precharge Command Bank A 7 RAz RAz 7 RBy RBy 7 Activate Command Bank B tCKH tRRD 7 Activate Command Bank A 7 7 Burst Length = 4, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O DQM Addr AP BS WE CAS RAS CS CKE CLK Hi-Z tCL tCKS tCH T0 tIS RAx RAx tIS tRCD tIH tIH tCK2 7 Activate Command Bank A 7 $&3DUDPHWHUVIRU5HDG7LPLQJ tRRD CAx 7 Read Command Bank A 7 tLZ tAC2 tAC2 Ax0 tOH tRAS RBx RBx 7 Activate Command Bank B 7 RBx 7 Read with Auto Precharge Command Bank B tHZ Ax1 tRC 7 7 Precharge Command Bank A Bx0 Begin Auto Precharge Bank B 7 tHZ Bx1 tRP tCKH RAy RAy 7 Activate Command Bank A 7 7 Burst Length = 2, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Mode Register Set Command Address Key Precharge Command All Banks 7 7 Addr AP BS WE CAS RAS CS CKE CLK 7  0RGH5HJLVWHU6HW 7 7 t RSC 7 2 Clock min. Any Command 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 \ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6  I/O DQM Addr AP BS WE CAS RAS CS CKE CLK tRP Precharge 1st Auto Refresh Command Command All Banks Inputs must be stable for 200us Hi-Z High level is required 2nd Auto Refresh Command Minimum of 2 Refresh Cycles are required  3RZHURQ6HTXHQFHDQG$XWR5HIUHVK&%5 tRC Mode Register Set Command Address Key Any Command 2 Clock min. AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Power Down Mode Exit tSB Power Down Mode Entry tCKS Any Command 7 7 7 7 7 7 RAx Addr Activate Command Bank A RAx AP 7 I/O DQM BS WE CAS RAS CS CKE CLK Hi-Z 7  3RZHU'RZQ0RGH 7 7 7 7 7 7 7 7 7 7 7 7 Precharge Command Bank A 7 7 7 Burst Length = 4, CAS Latency = 2 \ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 3ELF2EFRESH%XIT #OMMANDISSUED 3ELF2EFRESH %NTRY !LL"ANKS MUSTBEIDLE (I : )/ $1- !DDR !0 "3 7% #!3 2!3 #3 #+% #,+  6HOI5HIUHVK(QWU\DQG([LW T#+3 T832 "EGIN3ELF2EFRESH %XIT#OMMAND T2# 3ELF2EFRESH %XIT 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6  Hi-Z Precharge Command All Banks 7 tRC 7 0LQLPXP,QWHUYDO 7 7 7 Auto Refresh Command 7 7 tRC 7 7 7 7 I/O DQM Auto Refresh Command 7 Activate Command Bank A RAx 7 Addr 7 RAx tRP tCK2 7 AP BS WE CAS RAS CS CKE CLK 7  $XWR5HIUHVK&%5 7 Read Command Bank A CAx 7 7 Ax0 7 Ax1 7 Ax3 7 Ax2 7 Burst Length = 4, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A RAw Addr Hi-Z RAw DQM 7 tCK2 AP BS WE CAS RAS CS CKE CLK 7 7 Read Command Bank A CAw 7 7 Aw0 7 Aw2 CAx 7 Read Command Bank A Aw1 7 Ax0 CAy 7 Read Command Bank A Aw3 7 Ax1 Ay0 7 Ay2 7 Activate Command Bank A RAz RAz 7 Ay3 7 Precharge Command Bank A 7 Ay1 7 5DQGRP&ROXPQ5HDG3DJHZLWKLQVDPH%DQNRI 7 Read Command Bank A CAz 7 7 Az0 7 Az1 7 Az2 7 Az3 7 Burst Length = 4, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \) $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A RAw Addr Hi-Z RAw DQM 7 tCK3 AP BS WE CAS RAS CS CKE CLK 7 7 CAw 7 Read Command Bank A 7 7 7 Aw1 CAx 7 Read Command Bank A Aw0 7 Aw3 CAy 7 Ax1 7 Ax0 7 Read Command Bank A Aw2 7 5DQGRP&ROXPQ5HDG3DJHZLWKLQVDPH%DQNRI Ay0 7 Ay1 Ay2 7 Ay3 7 Precharge Command Bank A 7 7 Activate Command Bank A RAz RAz 7 7 7 Read Command Bank A CAz 7 7 Burst Length = 4, CAS Latency = 3 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \) $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank B RBz Addr Hi-Z RBz DQM 7 tCK2 AP BS WE CAS RAS CS CKE CLK 7 CBz 7 7 7 7 CBx 7 7 CBy 7 7 7 Write Command Bank B Write Command Bank B Write Command Bank B 7 Precharge Command Bank B 7 DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 7 5DQGRP&ROXPQ:ULWH3DJHZLWKLQVDPH%DQNRI 7 Activate Command Bank B RBz RAw RBz RAw 7 CBz CAx 7 7 7 7 Write Command Bank B DBz0 DBz1 DBz2 DBz3 7 7 7 Burst Length = 4, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \) $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank B RBz Addr Hi-Z RBz DQM 7 tCK3 AP BS WE CAS RAS CS CKE CLK 7 7 CBz 7 7 7 7 CBx 7 7 CBy 7 7 7 7 Write Command Bank B Write Command Bank B Write Command Bank B DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 7 5DQGRP&ROXPQ:ULWH3DJHZLWKLQVDPH%DQNRI 7 Precharge Command Bank B 7 7 7 Activate Command Bank B RBz RBz 7 7 7 7 Write Command Bank B DBz0 DBz1 CBz 7 Burst Length = 4, CAS Latency = 3 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \) $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O tRCD Activate Command Bank B Hi-Z RBx Addr DQM RBx High AP BS WE CAS RAS CS CKE CLK 7 tAC2 7 Read Command Bank B CBx tCK2 7 7 Bx0 7 Bx1 7 Bx2 7 Bx4 RAx RAx 7 Activate Command Bank A Bx3 7 7 Bx6 CAx Ax1 RBy RBy 7 Activate Command Bank B 7 Ax0 tRP 7 Bx7 7 Precharge Command Bank B Read Command Bank A Bx5 5DQGRP5RZ5HDG,QWHUOHDYLQJ%DQNVRI Ax2 7 Ax3 Ax5 7 Ax4 7 Ax6 7 7 Read Command Bank B Ax7 CBy 7 By0 7 By1 7 7 Burst Length = 8, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank B Hi-Z RBx Addr DQM RBx High AP BS WE CAS RAS CS CKE CLK 7 tRCD tCK3 7 CBx 7 Read Command Bank B 7 tAC3 7 7 Bx0 7 Bx2 RAx RAx 7 Activate Command Bank A Bx1 7 7 Bx3 5DQGRP5RZ5HDG,QWHUOHDYLQJ%DQNVRI Bx4 Bx7 tRP RBy RBy Activate Command Bank B Ax3 7 Ax2 7 Ax1 7 Ax0 7 Precharge Command Bank B 7 Bx6 7 Read Command Bank A Bx5 CAx 7 Ax4 7 Ax6 7 Read Command Bank B Ax5 CBy 7 By0 7 Precharge Command Bank A Ax7 7 7 Burst Length = 8, CAS Latency = 3 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK 7 7 7 7 7 7 RBx RBx 7 CBx tDPL 7 7 7 tRP 7 RAy RAy 7 7 7 7 tDPL CAy 7 7 7 7 7 7 Burst Length = 8, CAS Latency = 2 Activate Command Bank B Precharge Command Bank A Write Command Bank B Activate Command Bank A Precharge Command Bank B Write Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 7 Write Command Bank A tRCD CAX CAy tCK2 7 5DQGRP5RZ:ULWH,QWHUOHDYLQJ%DQNVRI AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK 7 tRCD tCK3 7 CAX 7 7 7 7 7 RBx RBx 7 7 7 tDPL CBx 7 7 7 tRP 7 7 RAy RAy 7 7 7 tDPL CAy 7 7 7 7 Burst Length = 8, CAS Latency = 3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 7 5DQGRP5RZ:ULWH,QWHUOHDYLQJ%DQNVRI AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK 7 7 7 7 7 7 Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. DAx0 DAx1 DAx2 DAx3 CAx tCK2 7 tRP RAy RAy 7 Activate Command Bank A 7 3UHFKDUJH7HUPLQDWLRQRID%XUVWRI CAy 7 Read Command Bank A 7 7 Ay1 7 Precharge Command Bank A Ay0 7 RAz RAz 7 Activate Command Bank A Ay2 tRP 7 7 7 Az1 7 Az2 tRP 7 Precharge Command Bank A Az0 7 Precharge Termination of a Read Burst. Read Command Bank A CAz 7 Burst Length = 8, CAS Latency = 2 7 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK 7 CAx 7 Write Command Bank A DAx0 7 Write Data is masked tCK3 7 7 tRP 7 RAy RAy 7 Activate Command Bank A 7 Precharge Termination of a Write Burst. Precharge Command Bank A 7 3UHFKDUJH7HUPLQDWLRQRID%XUVWRI 7 7 Read Command Bank A CAy 7 7 7 Ay1 7 Precharge Command Bank A Ay0 7 Ay2 tRP 7 7 7 7 7 Precharge Termination of a Read Burst. Activate Command Bank A RAz RAz 7 7 Burst Length = 4, 8, CAS Latency = 3 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK Read Command Bank A CAx tCK2 Ax+1 Activate Command Bank B Ax RBx RBx )XOO3DJH5HDG&\FOHRI Ax-2 Ax-1 Ax Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+6 Burst Stop Command Precharge Command Bank B Bx+5 Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Ax+1 Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval. Ax+2 CBx tRP Activate Command Bank B RBy RBy Burst Length = Full Page, CAS Latency = 2 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK tCK3 Read Command Bank A CAx Activate Command Bank B RBx RBx )XOO3DJH5HDG&\FOHRI  Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx +5 Full Page burst operation does notterminate when the length is Read satisfied; the burst counter Comman Precharge increments and continuesbursting B Command d Bank The burst counter wraps beginning with Bank B from the highest order the starting address. page address back to zero during this time interval. Burst Stop Command Ax Ax+1 Ax+2 Ax-2 Ax-1 CBx tRRD Activate Command Bank B RBy RBy Burst Length = Full Page, CAS Latency = 3 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV \ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O DQM Addr AP BS WE CAS RAS CS CKE CLK Activate Command Bank A Hi-Z DAx-1 DAx DAx+1 DBx CBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 Activate Command Bank B RBy RBy Burst Length = Full Page, CAS Latency = 2 Activate Write Command Precharge Command Data is ignored. Bank B Command Bank B Bank B The burst counter wraps Full Page burst operation does not from the highest order terminate when the burst length is satisfied; page address back to zero the burst counter increments and continues Burst Stop during this time interval. bursting beginning with the starting address. Command DAx+1 DAx+2 DAx+3 Write Command Bank A DAx RBx RAx CAx RBx RAx High tCK2 )XOO3DJH:ULWH&\FOHRI AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6  I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BS WE CAS RAS CS CKE CLK tCK3 RBx DAx-1 DAx DAx+1 DBx CBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 Data is ignored. Activate Command Bank B RBy RBy Burst Length = Full Page, CAS Latency = 3 Activate Write Command Precharge Command Full Page burst operation does not Bank B Command Bank B terminate when the length is Bank B satisfied; the burst counter The burst counter wraps increments and continues from the highest order bursting beginning with page address back to zero Burst Stop the starting address. during this time interval. Command DAx+1 DAx+2 DAx+3 Write Command Bank A DAx CAx RBx )XOO3DJH:ULWH&\FOHRI AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH 5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV &RPSOHWH/LVWRI2SHUDWLRQ&RPPDQGV 6'5$0)XQFWLRQ7UXWK7DEOH &855(17 67$7( &6 5$6 &$6 :( %6 $GGU $&7,21 Idle H L L L L L L L X H H H L L L L X H H L H H L L X H L X H L H L X X BS BS BS BS X Op- X X X X RA AP X Code NOP or Power Down NOP ILLEGAL2 ILLEGAL2 Row (&Bank) Active; Latch Row Address NOP4 Auto-Refresh or Self-Refresh5 Mode reg. Access5 Row Active H L L L L L L X H H H L L L X H L L H H L X X H L H L X X X BS BS BS BS X X X CA,AP CA,AP X AP X NOP NOP Begin Read; Latch CA; DetermineAP Begin Write; Latch CA; DetermineAP ILLEGAL2 Precharge ILLEGAL Read H L L L L L L L X H H H H L L L X H H L L H H L X H L H L H L X X X BS BS BS BS BS X X X X CA,AP CA,AP X AP X NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop Command > Row Active Term Burst, New Read, DetermineAP3 Term Burst, Start Write, DetermineAP3 ILLEGAL2 Term Burst, Precharge ILLEGAL Write H L L L L L L L X H H H H L L L X H H L L H H L X H L H L H L X X X BS BS BS BS BS X X X X CA,AP CA,AP X AP X NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop Command > Row Active Term Burst, Start Read, DetermineAP3 Term Burst, New Write, DetermineAP3 ILLEGAL2 Term Burst, Precharge3 ILLEGAL Read with Auto Precharge H L L L L L L L X H H H H L L L X H H L L H H L X H L H L H L X X X BS BS X BS BS X X X X X X X AP X NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 6'5$0)XQFWLRQ7UXWK7DEOHFRQWLQXHG &855(17 67$7( &6 5$6 &$6 :( %6 $GGU $&7,21 Write with Auto Precharge H L L L L L L L X H H H H L L L X H H L L H H L X H L H L H L X X X BS BS X BS BS X X X X X X X AP X NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL Precharging H L L L L L L X H H H L L L X H H L H H L X H L X H L X X X BS BS BS BS X X X X X X AP X NOP;> Idle after tRP NOP;> Idle after tRP ILLEGAL2 ILLEGAL2 ILLEGAL2 NOP4 ILLEGAL Row Activating H L L L L L L X H H H L L L X H H L H H L X H L X H L X X X BS BS BS BS X X X X X X AP X NOP;> Row Active after tRCD NOP;> Row Active after tRCD ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL Write Recovering H L L L L L L X H H H L L L X H H L H H L X H L X H L X X X BS BS BS BS X X X X X X AP X NOP NOP ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL Refreshing H L L L L L X H H H L L X H H L H L X H L X X X X X X X X X X X X X X X NOP;> Idle after tRC NOP;> Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL Mode Register H L L L L X H H H L X H H L X X H L X X X X X X X X X X X X NOP NOP ILLEGAL ILLEGAL ILLEGAL Accessing $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV &ORFN(QDEOH&.(7UXWK7DEOH &.( Q &.( Q &6 5$6 &$6 :( $GGU Self-Refresh6 H L L L L L L X H H H H H L X H L L L L X X X H H H L X X X H H L X X X X H L X X X X X X X X X X INVALID EXIT Self-Refresh, Idle after tRC EXIT Self-Refresh, Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) Power-Down H L L L L L L X H H H H H L X H L L L L X X X H H H L X X X H H L X X X X H L X X X X X X X X X X INVALID EXIT Power-Down, > Idle. EXIT Power-Down, > Idle. ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low-Power Mode) All. Banks Idle7 H H H H H H H H L H L L L L L L L L X H L L L L L L X X X H H H L L L X X X H H L H L L X X X H L X X H L X X X X X X X X X X Refer to the function truth table Enter Power- Down Enter Power- Down ILLEGAL ILLEGAL ILLEGAL Enter Self-Refresh ILLEGAL NOP 67$7(Q $&7,21 Abbreviations: RA = Row Address of Bank A CA = Column Address of Bank A BS = Bank Address RB = Row Address of Bank B CB = Column Address of Bank B AP = Auto Precharge RC = Row Address of Bank C CC = Column Address of Bank C RD = Row Address of Bank D CD = Column Address of Bank D 1RWHVIRU6'5$0IXQFWLRQWUXWKWDEOH 1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle. 2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP). 5. Illegal if any bank is not Idle. 6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 8. Must be legal command as defined in the SDRAM function truth table. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV Package Diagram 54-Pin Plastic TSOP-II (400 mil) 0.047 [1.20] MAX 0.400 ±0.005 [10.16 ±0.13] 0.04 ±0.002 [1 ±0.05] 0°–5° .004 [0.1] 0.031 [0.80] +0.002 0.016 -0.004 +0.05 0.40 -0.10 +0.004 0.006 -0.002 +0.01 0.15 -0.05 0.006 [0.15] MAX 0.463 ± 0.008 [11.76 ± 0.20] 0.024 ± 0.008 [0.60 ± .020] .008 [0.2] M 54x 54 28 Index Marking 27 1 0.881 -0.01 [22.38 -0.25] 1 1 Does not include plastic or metal protrusion of 0.15 max. per side Unit in inches [mm] $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV 3DFNDJH'LDJUDP %DOO)%*$[ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6 AS4C32M16SA 0ELW6LQJOH'DWD5DWH6'56'5$0 0[0[[%DQNV PART NUMBERING SYSTEM AS4C M6$  DRAM M=Mx 6$=6'5$0 $YHUVLRQ =MHz 7B 7 = 7623,, B = FBGA C/I C=Commercial (0¡ C
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5¡ C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH  5HY4Mar6