AS4C32M8D1-5TINTR

AS4C32M8D1-5TCN AS4C32M8D1-5TIN Revision History AS4C32M8D1 - 66pin TSOPII PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date Jun 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Features - - Description The AS4C32M8D1 is a four bank DDR DRAM organized as 4 banks x 8Mbit x 8. The AS4C32M8D1 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. High speed data transfer rates with system frequency up to 200 MHz Data Mask for Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2.5, 3, 4 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type Automatic and Controlled Precharge Command Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 8192 cycles/64 ms Available in 66-pin 400 mil TSOP SSTL-2 Compatible I/Os Double Data Rate (DDR) Bidirectional Data Strobe (DQS) for input and output data, active on both edges On-Chip DLL aligns DQ and DQs transitions with CK transitions Differential clock inputs CK and CK Power Supply 2.5V ± 0.2V for DDR333, 2.6V ± 0.1V for DDR400 tRAS lockout supported Concurrent auto precharge option is supported Table 1. Ordering Information Part Number Org All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are occurring on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Temperature MaxClock (MHz) Package AS4C32M8D1-5TCN 32Mx8 Commercial 0°C to 70°C 200 66-pin TSOPII AS4C32M8D1-5TIN 32Mx8 Industrial -40°C to 85°C 200 66-pin TSOPII Table 2. Speed Grade Information Speed Grade Clock Frequency DDR1-400 Confidential CAS Latency 3 200MHz - 2/57 - tRCD (ns) tRP (ns) 15 15 Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN 66 Pin Plastic TSOP-II VDD DQ0 VDDQ NC DQ1 1 66 VSS 2 3 4 5 65 64 63 62 DQ7 VSSQ VSSQ NC DQ2 VDDQ NC DQ3 6 7 8 9 10 61 60 59 58 57 DQ6 VDDQ NC DQ5 VSSQ NC 11 56 DQ4 VSSQ NC NC VDDQ NC NC VDD 12 55 VDDQ NC NC VSSQ DQS NC VREF NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 66 PIN TSOP (II) 13 (400mil x 875 mil) 14 15 Bank Address BA0-BA1 16 17 Row Address 18 A0-A12 19 20 Auto Precharge A10 21 54 53 52 51 50 49 48 47 NC VSS DM 46 45 44 CK CK CKE 24 25 26 27 28 29 43 42 NC A12 41 40 39 38 A11 A9 A8 A7 30 31 32 33 37 36 35 34 A6 A5 22 23 A4 VSS Pin Names CK, CK Differential Clock Input DQ’s Data Input/Output CKE Clock Enable DM Data Mask CS Chip Select VDD RAS Row Address Strobe Power (+2.5V and +2.6V for DDR400) CAS Column Address Strobe VSS Ground WE Write Enable VDDQ Power for I/O’s (+2.5V and +2.6V for DDR400) DQS (UDQS, LDQS) Data Strobe (Bidirectional) VSSQ Ground for I/O’s A0–A12 Address Inputs NC Not connected BA0, BA1 Bank Select VREF Reference Voltage for Inputs Confidential - 3/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Block Diagram 32M x 8 Row Addresses Column Addresses A0 - A9, AP, BA0, BA1 Row address buffer Column address buffer Refresh Counter Row decoder Row decoder Memory array Memory array Memory array Memory array Bank 0 8M x 8 Bank 1 8M x 8 Input buffer Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Column address counter A0 - A12, BA0, BA1 Bank 2 8M x 8 Bank 3 8M x 8 Control logic & timing generator Output buffer DQS Capacitance* Strobe Gen. Symbol Min Max Unit BA0, BA1, CKE, CS, RAS, (CAS, A0-A11, WE) CINI 2 3.0 pF Input Capacitance (CK, CK) CIN2 2 3.0 pF Data & DQS I/O Capacitance COUT 4 5 pF Input Capacitance (DM) CIN3 4 5.0 pF *Note: Capacitance is sampled and not 100% tested. Confidential WE DM CAS RAS CS Absolute Maximum Ratings* Data Strobe VCC = 2.5V ± 0.2V, f = 1 MHz Input Capacitance CKE DLL CK CK, CK CK DQ0-DQ7 Operating temperature range ......... 0 to 70 °C for normal -40 to 85 °C for Industrial Storage temperature range......................... -55 to 150 °C VDDSupply Voltage Relative to VSS ..............-1V to +3.6V VDDQ Supply Voltage Relative to VSS ...............................................................-1V to +3.6V VREF and Inputs Voltage Relative to VSS ...............................................................-1V to +3.6V I/O Pins Voltage Relative to VSS ...................................................-0.5V to VDDQ+0.5V Power dissipation.................................................... 1.6 W Data out current (short circuit) ............................... 50 mA *Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. - 4/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Signal Pin Description Pin Type Signal Polarity Function CK CK Input Pulse Positive Edge The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK. CKE Input Level Active High Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the Power Down mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. DQS Input/ Output Pulse Active High Active on both edges for data input and output. Center aligned to input data Edge aligned to output data A0 - A12 Input Level — During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends on the SDRAM organization: 32M x 8 DDR CAn = CA9 In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged simultaneously regardless of state of BA0 and BA1. BA0, BA1 Input Level — Selects which bank is to be active. DQx Input/ Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. DM, Input Pulse VDD, VSS Supply VDDQ VSSQ Supply — — Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Input Level — SSTL Reference Voltage for Inputs Confidential Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation . Power and ground for the input buffers and the core logic. - 5/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Functional Description - Power-Up Sequence The following sequence is required for POWER UP. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high. 4. Precharge all banks. 5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1) 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0) 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command to initialize device operation. Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. Power up Sequence & Auto Refresh(CBR) 0 CK, CK 1 2 4 5 6 7 8 9 10 •• •• 11 12 13 14 •• tRFC tRP 2 Clock min. 2 Clock min. Command 3 precharge ALL Banks EMRS MRS DLL Reset 4 5 6 200 μS Power up to 1st command precharge ALL Banks 1st Auto Refresh 16 17 18 19 •• tRFC •• •• 15 2nd Auto Refresh •• •• 2 Clock min. Mode Register Set Any Command min. 200 Cycle 7 8 8 Extended Mode Register Set (EMRS) The extended mode register stores the data for enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A12 and BA1 in the same cycle as CS, RAS, CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. A1 is used at EMRS to indicate I/O strength A1 = 0 full strength, A1 = 1 half strength. Refer to the table for specific codes. Confidential - 6/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock cycles are required to meet tMRD spec. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Alliance specific test mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. 1. MRS can be issued only at all banks precharge state. 2. Minimum tRP is required to issue MRS command. "! "!  -23  -23 TO !   ! 2&5 $,, 4- !  )/ $,, $,,2ESET !  .O   9ES !DDRESS"US %XTENDED-ODE2EGISTER -ODE2EGISTER "4 "URST,ENGTH MODE ! "URST4YPE ! .ORMAL  3EQUENTIAL  &ULL  %NABLE )NTERLEAVE  (ALF  $ISABLE #!3 ,ATENCY !  4EST )/3TRENGTH ! ! ! ,ATENCY ! ! ! $,,%NABLE ,ATENCY  %XISTING -23#YCLE    2ESERVE 3EQUENTIAL )NTERLEAVE  %XTENDED&UNTIONS%-23    2ESERVE    2ESERVE 2ESERVE    2ESERVE                           2ESERVE    2ESERVE 2ESERVE        2ESERVE 2ESERVE    2ESERVE    2ESERVE 2ESERVE    2ESERVE 2ESERVE 2&52ESERVEDFORFUTUREUSE SHOULDSTAYDURING-23 CYCLE ! "URST,ENGTH #!3 ,ATENCY ! N ^!   ! 2&5-USTBESET  "! ! -ODE2EGISTER3ET          #+ #+ W#+ Confidential  -ODE 2EGISTER3ET 0RECHARGE !LL"ANKS #OMMAND W20  !NY #OMMAND T-2$ - 7/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Mode Register Set Timing T0 T1 T2 T3 T4 tCK T5 T6 T7 T8 T9 tMRD tRP CK, CK Pre- All Command ANY MRS/EMRS Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state. If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command to allow time for the DLL to lock onto the clock. Burst Mode Operation Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and burst length. These parameters are programmable and are determined by address bits A0—A3 during the Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length and Sequence table below for programming information. Burst Length and Sequence Burst Length 2 4 8 Confidential Starting Length (A2, A1, A0) Sequential Mode Interleave Mode xx0 0, 1 0, 1 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 - 8/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from the Bank Activate command to the first Read or Write command must meet or exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activation Timing (CAS Latency = 2; Burst Length = Any) T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 tRC tRP(min) tRAS(min) tRRD(min) tRCD(min) CK, CK BA/Address Bank/Row Bank/Col Bank Bank/Row Bank/Row Command Activate/A Read/A Pre/A Activate/A Activate/B Begin Precharge Bank A Read Operation With the DLL enabled, all devices operating at the same frequency within a system are ensured to have the same timing relationship between DQ and DQS relative to the CK input regardless of device density, process variation, or technology generation. The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock frequency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and the system clock (CK) are all nominally aligned. Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed and used to latch the output data into the receiving device. The tolerance for skew between DQS and DQ (tDQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK). Confidential - 9/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK) During Read Cycles (CAS Latency = 2.5; Burst Length = 4) T0 T1 T2 T3 T4 CK, CK Command READ NOP NOP NOP NOP tDQSCK(max) tDQSCK(min) DQS tAC(max) tAC(min) D0 DQ D1 D2 D3 The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a memory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are derived from the minimum clock high/low time minus a margin for variation in data access and hold time due to DLL jitter and power supply noise. Read Preamble and Postamble Operation Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe signal(DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read preamble” (tRPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of valid data. Once the burst of read data is concluded and given that no subsequent burst read operations are initiated, the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data strobe “read postamble” (tRPST). This transition happens nominally one-half clock period after the last edge of valid data. Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no requirement for a data strobe “read” preamble or postamble in between the groups of burst data. The data strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles. Confidential - 10/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Data Strobe Preamble and Postamble Timings for DDR Read Cycles (CAS Latency = 2; Burst Length = 2) T0 T1 T2 T3 T4 CK, CK READ Command NOP NOP NOP tRPRE(max) tRPRE(min) tRPST(min) DQS tRPST(max) tDQSQ(min) D0 DQ D1 tDQSQ(max) Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble Burst Read Operation (CAS Latency = 2; Burst Length = 4) CK, CK Command ReadA NOP ReadB NOP NOP NOP NOP NOP NOP NOP NOP DQS D0A D1A D2A D3A D0B D1B D2B D3B DQ Burst Read Operation (CAS Latency = 2; Burst Length = 4) CK, CK Command ReadA NOP NOP ReadB NOP NOP NOP DQS DQ Confidential D0A D1A D2A D3A - 11/57 - D0B D1B D2B D3B Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Precharge Operation The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank (s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A Precharge command will be treated as NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. Auto Precharge Operation The Auto Precharge operation can be issued by having column address A10 high when a Read or Write command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the Read or Write cycle once tRAS(min) is satisfied. This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Read with Auto Precharge If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (tRP) has been satisfied. Read with Autoprecharge Timing (CAS Latency = 2; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRAS(min) T7 T8 T9 tRP(min) CK, CK Command ACT NOP R/w AP NOP NOP NOP NOP BA NOP DQS D0 DQ D1 D2 D3 Begin Autoprecharge Earliest Bank A reactivate Confidential - 12/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Read with Autoprecharge Timing as a Function of CAS Latency (CAS Latency = 2, 2.5 Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRAS(min) T7 T8 T9 NOP NOP tRP(min) CK, CK Command BA NOP NOP RD AP NOP NOP NOP BA DQS D0 DQ D1 D2 D3 CAS Latency=2 DQS D0 DQ D1 D2 D3 CAS Latency=2.5 Confidential - 13/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Precharge Timing During Read Operation For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time (tRP). A Precharge command can not be issued until tRAS(min) is satisfied. Read with Precharge Timing as a Function of CAS Latency (CAS Latency = 2, 2.5; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRAS(min) T7 T8 T9 NOP NOP tRP(min) CK, CK Command BA NOP NOP Read NOP PreA NOP BA DQS D0 DQ D1 D2 D3 CAS Latency=2 DQS D0 DQ D1 D2 D3 CAS Latency=2.5 Confidential - 14/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Burst Stop Command The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay (LBST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a burst Write cycle, the command will be treated as a NOP command. Read Terminated by Burst Stop Command Timing (CAS Latency = 2, 2.5; Burst Length = 2) T0 T1 T2 T3 T4 T5 T6 CK, CK Command Read BST NOP NOP NOP NOP LBST DQS CAS Latency = 2 D0 DQ D1 LBST DQS CAS Latency = 2.5 D0 DQ Confidential - 15/57 - D1 Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Read Interrupted by a Precharge A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to Output Disable latency is equivalent to the CAS latency. Read Interrupted by a Precharge Timing (CAS Latency = 2, 2.5; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRAS(min) T7 T8 T9 NOP NOP tRP(min) CK, CK Command BA NOP NOP Read NOP PreA NOP BA DQS D0 DQ D1 D2 D3 CAS Latency=2 DQS D0 DQ D1 D2 D3 CAS Latency=2.5 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. The memory controller is required to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be driven high nominally one clock after the write command has been registered. Timing parameters tDQSS(min) and tDQSS(max) define the allowable window when the data strobe must be driven high. Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is registered into the device (WL=1). The input data valid window is nominally centered around the midpoint of the data strobe signal. The data window is defined by DQ to DQS setup time (tQDQSS) and DQ to DQS hold time (tQDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Write Preamble and Postamble Operation Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe “write preamble”. This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write command has been registered by the device. The preamble is explicitly defined by a setup time (tWPRES(min)) and hold time (tWPREH(min)) referenced to the first falling edge of CK after the write command. Confidential - 16/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Burst Write Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 CK, CK WRITE Command NOP NOP NOP tWPST tWPRES tDS tDQSS DQS(nom) tDS tDH D0 DQ(nom) D1 tDH D2 D3 tWPRES(min) DQS(min) tDQSS(min) D0 DQ(min) D1 D2 D3 D0 D1 D2 tWPRES DQS(max) tDQSS(max) DQ(max) D3 Once the burst of write data is concluded and given that no subsequent burst write operations are initiated, Once the burst of write data is concluded and given that no subsequent burst write operations are initiated, the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the burst cycle is latched into the device. Confidential - 17/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Write Interrupted by a Precharge A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only restriction being that the interval that separates the commands be at least one clock cycle. Write Interrupted by a Precharge Timing (CAS Latency = 2; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP NOP T10 T12 T11 CK, CK WriteA Command NOP NOP PreA NOP tWR NOP NOP NOP NOP DQS D0 D1 D2 D3 D4 D5 D6 DQ DM Data is masked by DM input Data is masked by Precharge Command DQS input ignored Write with Auto Precharge If A10 is high when a Write command is issued, the Write with auto Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR (min.). Write with Auto Precharge Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP NOP T10 tRAS(min) CK, CK Command BA NOP NOP WAP NOP NOP NOP NOP BA DQS tRP(min) tWR(min) DQ D0 D1 D2 D3 Begin Autoprecharge Confidential - 18/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Precharge Timing During Write Operation Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery requirement. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe in the last valid write data. “Write recovery” is complete on the next 2nd rising clock edge that is used to strobe in the Precharge command. Write with Precharge Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 tRAS(min) T10 T9 tRP(min) CK, CK Command BA NOP NOP Write NOP NOP NOP NOP PreA NOP BA tWR DQS D0 DQ D1 D2 D3 tWR DQS DQ Confidential D0 D1 D2 - 19/57 - D3 Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Data Mask Function The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask to Data Latency = 0). When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe. Data Mask Timing (CAS Latency = Any; Burst Length = 8) T0 T1 T2 Write NOP T3 T4 T5 T6 T7 T8 T9 CK, CK Command NOP NOP NOP NOP tDS NOP NOP tDS DQS tDH D0 DQ D1 D2 D3 tDH D4 D5 D6 D7 DM Burst Interruption Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears on the bus. Read commands can be issued on each rising edge of the system clock. It is illegal to interrupt a Read with autoprecharge command with a Read command. Read Interrupted by a Read Command Timing (CAS Latency = 2; Burst Length = 4) T0 T1 T2 ReadA ReadB T3 T4 T5 T6 T7 T8 T9 CK, CK Command NOP NOP NOP NOP NOP NOP DQS DQ Confidential DA0 DA1 DB0 DB1 DB2 DB3 - 20/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Read Interrupted by a Write To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or latency (LBST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half clock cycles, the minimum delay (LBST) is rounded up to the next full clock cycle (i.e., if CL=2 then LBST=2, if CL=2.5 then LBST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command. Read Interrupted by Burst Stop Command Followed by a Write Command Timing (CAS Latency = 2; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write NOP NOP NOP NOP T9 CK, CK Read Command BST DQS D0 DQ D0 D1 D1 D2 D3 LBST Write Interrupted by a Write A Burst Write can be interrupted before completion by a new Write command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. The data from the first Write command continues to be input into the device until the Write Latency of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write command is input into the device. Write commands can be issued on each rising edge of the system clock. It is illegal to interrupt a Write with autoprecharge command with a Write command. Write Interrupted by a Write Command Timing (CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 WriteA WriteB NOP NOP NOP NOP NOP NOP T9 CK, CK Command DQS DQ DA0 DA1 DB0 DB1 DB2 DB3 DM DM0 DM1 DM0 DM1 DM2 DM3 Write Latency Confidential - 21/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Write Interrupted by a Read A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory array. Any data that is present on the DQ pins coincident with or following the Read command will be masked off by the Read command and will not be written to the array. The memory controller must give up control of both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in order to avoid contention. In order to avoid data contention within the device, a delay is required (tWTR) from the first positive CK edge after the last desired data in the pair tWTR before a Read command can be issued to the device. It is illegal to interrupt a Write with autoprecharge command with a Read command. Write Interrupted by a Read Command Timing (CAS Latency = 2; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 Read NOP NOP T7 T8 T9 NOP NOP T10 T11 T12 CK, CK Write Command NOP NOP tWTR NOP NOP NOP DQS D0 D1 D2 D3 D4 D5 DQ D0 D 1 D 2 D3 D4 D 5 D 6 D7 DM Data is masked by DM input Data is masked by Read command DQS input ignored Auto Refresh The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the rising edge of the clock. All banks must be precharged and idle for a tRP(min) before the Auto Refresh command is applied. No control of the address pins is required once this cycle has started because of the internal address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate command or subsequent Auto Refresh command must be greater than or equal to the tRFC(min). Commands may not be issued to the device once an Auto Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be registered on each rising edge of the CK input until the refresh period is satisfied. Auto Refresh Timing T0 T1 T2 tRP T3 T4 T5 T6 T7 tRFC T8 T9 T10 T11 CK, CK Pre All Command CKE Confidential NOP Auto Ref NOP NOP ANY High - 22/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Self Refresh A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tSREX for locking of DLL. The auto refresh is required before self refresh entry and after self refresh exit. •• CK, CK Command •• Self Refresh •• Stable Clock Auto Refresh •• NOP •• •• CKE •• tSREX Power Down Mode The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tck+tIS prior to row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (tREF) of the device. CK, CK Command •• Precharge Precharge power down Entry •• precharge •• power down Exit •• Active NOP Read CKE •• •• Active power down Entry Confidential - 23/57 - Active power down Exit Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN TRUTH TABLE 2 – CKE (Notes: 1-4) CKEn-1 CKEn L L H H L H L H CURRENT STATE COMMANDn ACTIONn NOTES Power-Down X Maintain Power-Down Self Refresh X Maintain Self Refresh Power-Down DESELECT or NOP Exit Power-Down Self Refresh DESELECT or NOP Exit Self Refresh All Banks Idle DESELECT or NOP Precharge Power-Down Entry Bank(s) Active DESELECT or NOP Active Power-Down Entry All Banks Idle AUTO REFRESH 5 Self Refresh Entry See Truth Table 3 NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200 clock cycles is needed before applying a read command, for the DLL to lock. Confidential - 24/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN DDR SDRAM SIMPLIFIED COMMAND TRUTH TABLE A10/ AP Command CKEn-1 CKEn CS RAS CAS WE Mode Register Set H X L L L L OP code 1,2 Extended Mode Register Set H X L L L L OP code 1,2 H X H X X X L H H H X 1 H X L L H H H X L H L H CA H X L H L L CA H X L L H L X Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Entry H L L L L H Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H 1 H X X X 1 L V V V Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh Precharge Power Down Mode Active Power Down Mode Exit L H Entry H L Exit L H ADDR RA BA V L H L H V V Note 1 1 1,3,6 1 1,4, 6 H X 1,5 L V 1 1 X 1 1 1 X 1 X 1 X 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. 6. This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). Confidential - 25/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN TRUTH TABLE 3 – Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) /CS /RAS /CAS /WE COMMAND/ACTION NOTES H X X X DESELECT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) L L H H ACTIVE (select and activate row) L L L H AUTO REFRESH 7 L L L L MODE REGISTER SET 7 L H L H READ (select column and start READ burst) 10 L H L L WRITE (select column and start WRITE burst) 10 L L H L PRECHARGE (deactivate row in bank or banks) 8 L H L H READ (select column and start new READ burst) 10 L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 8 L H H L BURST TERMINATE 9 L H L H READ (select column and start READ burst) L H L L WRITE (select column and start new WRITE burst) L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10, 11 10 8, 11 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Confidential - 26/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN NOTE: (continued) Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the “row active” state. Read w/Auto-Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRFC is met, the DDR SDRAM will be in the “all banks idle” state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the “all banks idle” state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle and no bursts are in progress. 8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. 10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 11. Requires appropriate DM masking. Confidential - 27/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN TRUTH TABLE 4 – Current State Bank n - Command to Bank m (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (Auto-Precharge Disabled) Write (Auto- Precharge Disabled) Read (With Auto-Precharge) Write (With Auto-Precharge) /CS /RAS /CAS /WE COMMAND/ACTION NOTES H X X X DESELECT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) X X X X Any Command Otherwise Allowed to Bank m L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) 7 L H L L WRITE (select column and start WRITE burst) 7 L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start new READ burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) L H L L WRITE (select column and start new WRITE burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start new READ burst) L H L L WRITE (select column and start WRITE burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) 3a, 7 L H L L WRITE (select column and start new WRITE burst) 3a, 7 L L H L PRECHARGE 7 7, 8 7 3a, 7 3a, 7, 9 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Confidential - 28/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN NOTE: (continued) Read with Auto Precharge Enabled: See following text Write with Auto Precharge Enabled: See following text 3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; All other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 3b. This device supports “concurrent auto precharge”. This feature allows a read with auto precharge enabled, or a write with auto precharge enabled, to be followed by any command to the other banks, as long as that command does not interrrupt the read or write data transfer, and all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided.) 3c. The minimum delay from a read or write command with auto precharge enable, to a command to a different bank, is sumarized below, for both cases of “concurrent auto precharge,” supported or not: From Command Write w/AP Read w/AP To Command (different bank) Minimum Delay without Concurrent Auto Precharge Support Minimum Delay with Concurrent Auto Precharge Support Units Read or Read w/AP 1+(BL/2)+(tWR/tCK) (rounded up) 1+(BL/2)+tWTR tCK Write or Write w/AP 1+(BL/2)+(tWR/tCK) (rounded up) BL/2 tCK Precharge or Activate 1 tCK Read or Read w/AP BL/2 tCK Write or Write w/AP CL(rounded up) + (BL/2) tCK Precharge or Activate 1 tCK 4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of data output. Confidential - 29/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Simplified State Diagram Power Applied Power On Precharge PREALL Self Refresh REFS REFSX MRS EMRS MRS Auto Refresh REFA Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Burst Stop Row Active Write Read Write Read Write A Write Read A Read Read Read A Write A Read A PRE Write A PRE PRE Read A Precharge PRE PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh Confidential CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge - 30/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN DC Operating Conditions & Specifications DC Operating Conditions Recommended operating conditions ( Voltage referenced to VSS = 0V ) Parameter Symbol Min Max Supply voltage (for device with a nominal VDD of 2.5V) VDD 2.3(DDR333) 2.5(DDR400) 2.7 I/O Supply voltage VDDQ 2.3(DDR333) 2.5(DDR400) 2.7 V I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1 VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V Input logic low voltage VIL(DC) -0.3 VREF-0.15 V Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current (VOUT = 1.95V) IOH -16.2 mA Output Low Current (VOUT = 0.35V) IOL 16.2 mA I/O Termination voltage(system) Input leakage current Unit Note 3 Notes: 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed 2% of the DC value 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. Confidential - 31/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN IDD Max Specifications and Conditions ( VDDQ = 2.5V+ 0.2V, VDD = 2.5 +0.2V ) Version Conditions Symbol -5 Unit Operating current - One bank Active-Precharge; tRC=tRCmin; tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B, 200MHz for DDR400, 220MHz for DDR440; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle IDD0 80 mA Operating current - One bank operation; One bank open, BL=4 IDD1 90 mA Precharge power-down standby current; All banks idle; power - down mode; CKE = =VIH(min);All banks idle; CKE > = VIH(min); tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B, 200MHz for DDR400, 220MHz for DDR440; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F 35 mA Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B, 200MHz for DDR400, 220MHz for DDR440; Address and other control inputs stable with keeping >= VIH(min) or == VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B, 200MHz for DDR400, 220MHz for DDR440; DQ, DQS and DM inIDD3N puts changing twice per clock cycle; address and other control inputs changing once per clock cycle 50 mA Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK = 100MHz for DDR200, CL=2 at tCK = 133MHz for DDR266A, CL=2.5 at tCK = 133MHz for DDR266B, CL=2.5 at tCK=166MHz for DDR333B, CL=2 at tCK = 200MHz for DDR400, CL=2.5 at tCK = 220MHz for DDR440; 50% of data changing at every burst; lout = 0 m A IDD4R 115 mA Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK = 100MHz for DDR200, CL=2 at tCK = 133MHz for DDR266A, CL=2.5 at tCK = 133MHz for DDR266B, IDD4W CL=2.5 at tCK=166MHz for DDR333B, CL=2 at tCK = 200MHz for DDR400, CL=2.5 at tCK = 220MHz for DDR440; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst 120 mA Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100MHz, 10*tCK for DDR266A & DDR266B at 133MHz, 12*tCK for DDR333B at 166MHz, 14*tCK for DDR400 at 200MHz, 16*tCK for DDR440 @220MHz; distributed refresh IDD5 120 mA IDD6 6 mA IDD7 200 mA Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100MHz for DDR200, tCK = 133MHz for DDR266A & DDR266B, tCK = 166MHz for DDR333B, tCK = 200MHz for DDR400, tCK = 220MHz for DDR440 Operating current - Four bank operation; Four bank interleaving with BL=4 Confidential - 32/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN AC Operating Conditions & Timing Specification AC Operating Conditions Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Max Unit Note V 1 VREF - 0.31 V 2 0.7 VDDQ+0.6 V 3 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 4 Note: 1. Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD. 2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS. 3. VID is the magnitude of the difference between the input level on CK and the input on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Electrical Characteristics & AC Timing - Absolute Specifications (Notes: 1-5, 14-17) ( VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V ) AC CHARACTERISTICS -5 PARAMETER Units Notes SYMBOL MIN MAX Access window of DQs from CK/CK tAC -0.7 0.7 ns CK high-level width t 0.45 0.55 tCK 30 CK low-level width t 0.45 0.55 t CK 30 6 12 ns 45 6 12 ns 45 ns 26,31 Clock cycle time CH CL CL = 2.5 CL = 3 tCK t (2.5) CK (3) DQ and DM input hold time relative to DQS t DH 0.40 DQ and DM input setup time relative to DQS tDS 0.40 ns 26,31 DAL - tCK 47 DIPW 1.75 ns 31 tDQSCK -0.6 t AUTO Precharge writerrecovery + precharge time DQ and DM input pulse width ( for each input ) Access window of DQS from CK/CK t ns 0.6 DQS input high pulse width tDQSH 0.35 tCK DQS input low pulse width t 0.35 t DQS-DQ skew, DQS to last DQ valid per group, per access tDQSQ Write command to first DQS latching transition tDQSS 0.72 DQS falling edge to CK rising - setup time tDSS 0.2 tCK DQS falling edge from CK rising - hold time t DSH 0.2 t Half clock period tHP tCH, tCL Data-out high-impedance window from CK/CK tHZ Data-out low-impedance window from CK/CK t Address and control input hold time ( fast slew rate ) tIH Address and control input setup time ( fast slew rate ) tIS Confidential DQSL LZ -0.7 CK 0.40 ns 1.25 tCK 25,26 CK ns 34 +0.7 ns 18 +0.7 ns 18 F 0.60 ns 14 F 0.60 ns 14 - 33/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN AC CHARACTERISTICS PARAMETER -5 SYMBOL MIN MAX Units Notes Address and control input hold time ( slow slew rate ) t IHS 0.70 ns 14 Address and control input setup time ( slow slew rate ) t ISS 0.70 ns 14 Control & Address input width ( for each input ) t IPW 2.2 ns 46 LOAD MODE REGISTER command cycle time tMRD 2 tCK DQ-DQS hold, DQS to first DQ to go non-valid per access tQH HP - QHS ns t t Data hold skew factor tQHS ACTIVE to PRECHARGE command t RAS 40 ACTIVE to READ with Auto precharge command tRAP ACTIVE to ACTIVE/AUTO REFRESH command period 0.50 ns 120,000 ns 35 15 ns 43 t RC 55 ns AUTO REFRESH command period t RFC 70 ns ACTIVE to READ or WRITE delay tRCD 15 ns RP 15 ns t PRECHARGE command period DQS read preamble t RPRE 0.9 1.1 t DQS read postamble tRPST 0.4 0.6 tCK t ACTIVE bank a to ACTIVE bank b command RRD DQS write postamble CK 10 ns 0.25 tCK WPRES 0 ns 20, 21 CK 19 t t WPST t Write recovery time t Internal WRITE to READ command delay Data valid output window 0.4 WR 0.6 t 15 WTR 2 na t ns t QH - tDQSQ CK ns Average periodic refresh interval tREFI Terminating voltage delay to VDD tVTD 0 ns Exit SELF REFRESH to non-READ command t XSNR 75 ns Exit SELF REFRESH to READ command t XSRD 200 Confidential 44 tWPRE DQS write preamble DQS write preamble setup time 25, 26 7.8 - 34/57 - 25 us t CK Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Slew Rate Derating Values ( Notes: 14 ) ( VDDQ= +2.5V ±0.2V, VDD = +2.5V ±0.2V ) ADDRESS / COMMAND SLEW RATE Δ tIS Δ tIH UNITS NOTES 0.500V / ns 0 0 ps 14 0.400V / ns +50 +50 ps 14 0.300V / ns +100 +100 ps 14 0.200V / ns +150 +150 ps 14 Slew Rate Derating Values ( Note: 31 ) ( VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V ) Date, DQS, DM SLEW RATE Δ tDS Δ tDH UNITS NOTES 0.500V / ns 0 0 ps 31 0.400V / ns +75 +75 ps 31 0.300V / ns +150 +150 ps 31 0.200V / ns +225 +225 ps 31 NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: VTT 50Ω Output (VOUT) Reference Point 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). Confidential - 35/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN NOTES: (continued) 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. IDD is dependent on output loading and cycle rates. 11. Enables on-chip refresh and address counters. 12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, T A = 25° C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 0.5V/ns. For -5 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS and tIH has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE •0.3 x VDDQ is recognized as LOW. 17. 18. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or be- gins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. Confidential - 36/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN NOTES: (continued) 23. The refresh period 64ms. This equates to an average refresh rate of 7.8µs. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP t QHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: x8 = DQS with DQ0-DQ7. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device.. 30. CK and CK input slew rate must be •1V/ns. 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4% if CKE is not active while any bank is active. 3.8 3.750 3.6 3.700 3.650 3.600 3.550 3.4 3.500 3.450 3.400 3.350 3.2 3.300 3.250 -7 @tCK = 10ns 3.0 ns -7 @tCK = 7.5ns 2.8 2.6 -7 @tCK = 7ns 2.500 2.463 2.425 2.388 2.4 2.350 2.313 2.275 2.238 2.200 2.2 2.163 2.125 2.0 1.8 50/50 Confidential 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 - 37/57 - 47/53 46.5/54.5 46/54 45.5/55.5 Rev.1.0 45/55 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN NOTES: (continued) 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. Applies to x16 only. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid. Initial JEDEC specifications suggested this to be same as tDQSQ. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V. 39. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width •3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width •3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. Confidential - 38/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN NOTES: (continued) 42. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 43. tRAP •t RCD. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 45. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 46. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 47. tDAL =(tWR/ tCK) + (tRP/ tCK) For each of the terms above, if not already an integer, round to the next highest integer. For example: For DDR266B at CL=2.5 and tCK=7.5ns t DAL=((15ns /7.5ns) + (20ns/ 7.5ns)) clocks=((2)+(3)) clocks=5 clocks 80 0 70 imum -20 igh Nominal h -40 Nominal low -60 Max Minimum 60 Nominal low 50 40 Nom 30 20 Confidential hig h Ma xim um -100 10 0 0.0 inal -80 Minimum -120 0.5 1.0 1.5 2.0 2.5 0.0 - 39/57 - 0.5 1.0 1.5 2.0 Rev.1.0 2.5 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN IBIS: I/V Characteristics for Input and Output Buffers Normal strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. Maximum 160 140 Typical High Iout(mA) 120 100 80 60 Typical Low 40 Minimum 20 0 0.0 0.5 1.0 1.5 2.0 2.5 Vout(V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure b. 0.0 0.5 1.0 1.5 2.0 2.5 Minumum 0 -20 Iout(mA) -40 Typical Low -60 -80 -100 -120 -140 -160 Typical High -180 -200 -220 Maximum VDDQ Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 Confidential - 40/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Low Typical High Minimum Maximum Typical Low Typical High Minimum Maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -41.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 Table 17. Pull down and pull up current values Temperature (Tambient) Typical Minimum Maximum 25°C 0°C for normal, -40°C for Industrial 70°C for normal, 85°C for Industrial Vdd/Vddq Typical Minimum Maximum 2.5V 2.3V 2.7V The above characteristics are specified under best, worst and normal process variation/conditions Confidential - 41/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Half strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. 90 Maximum 80 70 Typical High 50 Iout(mA) Iout(mA) 60 Typical Low Minimum 40 30 20 10 0 0.0 1.0 2.0 Vout(V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure b. 0.0 0.5 1.0 1.5 2.0 2.5 0 -10 Minumum Typical Low Iout(mA) -20 -30 -40 -50 -60 Typical High -70 Maximum -80 -90 VDDQ Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from 0 to VDDQ/2 Confidential - 42/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 26. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Low Typical High Minimum Maximum Typical Low Typical High Minimum Maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7 Table 18. Pull down and pull up current values Temperature (Tambient) Typical Minimum Maximum 25°C 0°C for normal, -40°C for Industrial 70°C for normal, 85°C for Industrial Vdd/Vddq Typical Minimum Maximum 2.5V 2.3V 2.7V The above characteristics are specified under best, worst and normal process variation/conditions Confidential - 43/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 36 - DATA INPUT (WRITE) TIMING tDSL tDSH DQS tDS DI n DQ tDH tDS DM tDH DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n Figure 37 - DATA OUTPUT (READ) TIMING tDQSQ max tDQSQ max t DQSQ nom DQS DQ tDQSQ min tDQSQ min 1. tDQSQ max occurs when DQS is the earliest among DQS and DQ signals to transition. 2. tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition. 3. tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions. DQS, DQ tDV Burst Length = 4 in the case shown Confidential - 44/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 38 - INITIALIZE AND MODE REGISTER SETS VDD VDDQ t VTD VTT (system*) VREF tCK tCH /CK (( )) (( )) CK CKE LVCMOS LOW LEVEL tCL t IH t IS (( )) tIS COMMAND (( )) (( )) DM (( )) (( )) A0-A9, A11 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tIH NOP PRE EMRS (( )) (( )) (( )) (( )) MRS (( )) (( )) tIS A10 (( )) (( )) tIH CODE ALL BANKS (( )) (( )) tIS tIH CODE tIS tIH tIS AR (( )) (( )) AR (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) CODE RA (( )) (( )) (( )) (( )) (( )) (( )) CODE RA (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA0=L, BA1=L BA CODE (( )) (( )) (( )) (( )) CODE (( )) (( )) ALL BANKS tIS tIH BA0, BA1 (( )) (( )) DQS (( )) High-Z (( )) (( )) (( )) (( )) (( )) DQ (( )) High-Z (( )) (( )) (( )) (( )) (( )) t MRD t MRD BA0=L, BA1=L ACT (( )) (( )) tIH BA0=H, BA1=L MRS (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) PRE T = 200μs Power-up: VDD and CLK stable Extended Mode Register Set t RP t RFC t RFC t MRD 200 cycles of CLK** Load Mode Register, Reset DLL (with A8 = H) Load Mode Register (with A8 = L) DON'T CARE * = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up. ** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied. The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command. Confidential - 45/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 39 - POWER-DOWN MODE tCK tCH /CK CK tIS tIH tIS CKE tIS COMMAND tIS ADDR (( )) (( )) tIS (( )) tIH VALID* tCL NOP tIH (( )) (( )) NOP (( )) (( )) VALID DQS (( )) (( )) DQ (( )) (( )) DM (( )) (( )) Enter Power-Down Mode VALID VALID Exit Power-Down Mode DON'T CARE No column accesses are allowed to be in progress at the time Power-Down is entered * = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is Active Power Down. Confidential - 46/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 40 - AUTO REFRESH MODE tCK tCH tCL /CK CK tIS tIH CKE VALID tIS COMMAND tIH NOP PRE NOP NOP AR (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) VALID (( )) (( )) NOP (( )) (( )) NOP AR NOP ACT A0-A8 (( )) (( )) (( )) (( )) RA A9, A11 (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) BA DQS (( )) (( )) (( )) (( )) DQ (( )) (( )) (( )) (( )) DM (( )) (( )) (( )) (( )) ALL BANKS A10 ONE BANK tIS BA0, BA1 tIH *Bank(s) t RP t RC t RC DON'T CARE * = "Don't Care", if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e. must precharge all active banks) PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other valid commands may be possible at these times DM, DQ and DQS signals are all "Don't Care"/High-Z for operations shown Confidential - 47/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 41 - SELF REFRESH MODE tCK tCH clock must be stable before exiting Self Refresh mode tCL /CK CK tIS tIH tIS tIS (( )) (( )) (( )) CKE tIS COMMAND (( )) (( )) (( )) tIH NOP AR (( )) (( )) NOP (( )) (( )) ADDR (( )) (( )) (( )) (( )) DQS (( )) (( )) (( )) (( )) DQ (( )) (( )) (( )) (( )) DM (( )) (( )) (( )) (( )) tRP* VALID tIS tIH VALID tXSNR/ tXSRD** Enter Self Refresh Mode Exit Self Refresh Mode DON'T CARE * = Device must be in the "All banks idle" state prior to entering Self Refresh mode ** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CLK) are required before a READ command can be applied. Confidential - 48/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 42 - READ - WITHOUT AUTO PRECHARGE tCH tCK tCL /CK CK tIS tIH tIS tIH tIH CKE COMMAND NOP Start!Autoprecharge READ tIS x8:A0-A8 NOP PRE NOP NOP ACT VALID VALID NOP NOP NOP tIH Col n RA x8:A9, A11 RA tIS tIH ALL BANKS A10 RA DIS AP tIS BA0, BA1 VALID ONE BANK tIH Bank x *Bank x Bank x tRP CL = 2 DM Case 1: tAC/tDQSCK = min t DQSCK min tRPST tRPRE DQS DQ tLZ min tHZ min DO n tLZ min tAC min Case 2: tAC/tDQSCK = max t DQSCK max tRPRE tRPST DQS DQ tLZ max tHZ max DO n tLZ max t AC max DON'T CARE DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Confidential - 49/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 43 - READ - WITH AUTO PRECHARGE tCH tCK tCL /CK CK tIS tIH tIS tIH tIH CKE COMMAND NOP READ tIS x8:A0-A8 NOP PRE NOP NOP ACT VALID VALID NOP NOP NOP tIH Col n RA x8:A9, A11 RA tIS tIH ALL BANKS A10 RA DIS AP tIS BA0, BA1 VALID ONE BANK tIH Bank x *Bank x Bank x tRP CL = 2 DM Case 1: tAC/tDQSCK = min t DQSCK min tRPST tRPRE DQS DQ tLZ min tHZ min DO n tLZ min tAC min Case 2: tAC/tDQSCK = max t DQSCK max tRPRE tRPST DQS DQ tLZ max tHZ max DO n tLZ max t AC max DON'T CARE DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Confidential - 50/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 44 - BANK READ ACCESS tCK tCH tCL /CK CK tIS tIH CKE tIS COMMAND tIH NOP ACT tIS x8:A0-A8 RA x8:A9, A11 RA NOP NOP NOP READ NOP NOP ACT RA RA tIH ALL BANKS RA RA tIS BA0, BA1 PRE Col n tIS A10 NOP tIH DIS AP ONE BANK Bank x *Bank x tIH Bank x Bank x tRC tRAS CL = 2 tRCD tRP DM Case 1: tAC/tDQSCK = min t DQSCK min tRPST tRPRE DQS tLZ min DQ tHZ min DO n tAC min tLZ min Case 2: tAC/tDQSCK = max t DQSCK max tRPRE tRPST DQS tLZ max DQ tHZ max DO n tLZ max t AC max DON'T CARE DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting) Confidential - 51/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 45 - WRITE - WITHOUT AUTO PRECHARGE tCH tCK tCL /CK CK tIS tIH tIS tIH tIH CKE COMMAND VALID NOP WRITE tIS x8:A0-A8 NOP NOP NOP NOP PRE NOP NOP ACT tIH Col n RA RA x8:A9, A11 tIS tIH ALL BANKS A10 RA DIS AP tIS BA0, BA1 ONE BANK tIH Bank x *Bank x BA tRP tDSH tDSH Case 1: tDQSS = min tDQSS tWR tDQSH tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM tDSS Case 2: tDQSS = max tDQSS tDQSH tDSS tWPST DQS tWPRES tDQSL tWPRE DQ DI n DM DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times Confidential - 52/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure 46 - WRITE - WITH AUTO PRECHARGE tCK tCH tCL /CK CK tIS tIH tIS tIH CKE COMMAND NOP WRITE tIS x8:A0-A8 NOP NOP NOP VALID VALID VALID NOP NOP NOP NOP ACT tIH Col n RA x8:A9, A11 RA EN AP A10 RA tIS BA0, BA1 tIH Bank x BA tDAL tDSH tDSH Case 1: tDQSS = min tDQSS tDQSH tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM tDSS Case 2: tDQSS = max tDQSS tDQSH tDSS tWPST DQS tWPRES tDQSL tWPRE DQ DI n DM DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times Confidential - 53/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Figure g 47 - BANK WRITE ACCESS tCH tCK tCL /CK CK tIS tIH CKE tIS COMMAND tIH NOP ACT tIS x8:A0-A8 RA x8:A9, A11 RA NOP NOP WRITE NOP NOP PRE tIH ALL BANKS RA tIS BA0, BA1 NOP Col n tIS A10 NOP tIH DIS AP ONE BANK Bank x *Bank x tIH Bank x tRAS tRCD tWR tDSH tDSH Case 1: tDQSS = min tDQSS tDQSH tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM tDSS Case 2: tDQSS = max tDQSS tDQSH tDSS tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM DON'T CARE DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n DIS AP = Disable Autoprecharge * = "Don't Care", if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times Confidential - 54/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN Package Diagram 66-Pin TSOP-II (400 mil) θ θ θ θ Confidential - 55/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN θ θ θ θ Confidential - 56/57 - Rev.1.0 June 2016 AS4C32M8D1-5TCN AS4C32M8D1-5TIN PART NUMBERING SYSTEM AS4C DRAM 32M8D1 32M8=32Mx8 D1=DDR1 T 5 5=200MHz T = TSOPII C / I C=Commercial (0° C~+75° C) I = Industrial (-40° C~+85° C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 57/57 - Rev.1.0 June 2016