AS4C4M16D1A-5TCNTR

4Mx16 DDR1-AS4C4M16D1A Revision History AS4C4M16D1A - 66-pin TSOPII PACKAGE Revision Rev 1.1 Details Preliminary datasheet Date July 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A Overview Features • Fast clock rate: 200 MHz • Differential Clock CK & CK • Bi-directional DQS • DLL enable/disable by EMRS • Fully synchronous operation • Internal pipeline architecture • Four internal banks, 1M x 16-bit for each bank • Programmable Mode and Extended Mode Registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved • Individual byte writes mask control • DM Write Latency = 0 • Auto Refresh and Self Refresh • 4096 refresh cycles / 64ms • Precharge & active power down • Power supplies: VDD & VDDQ = 2.5V ± 0.2V • Operating temperature: - Commercial (0°C~70°C) - Industrial (-40°C~85°C) • Interface: SSTL_2 I/O Interface • Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb free and Halogen free The AS4C4M16D1 DDR SDRAM is a highspeed CMOS double data rate synchronous DRAM containing 64 Mbits. It is internally configured as a quad 1M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C4M16D1 provides programmable Read or Write burst lengths of 2, 4, 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, AS4C4M16D1 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance. Table 1. Ordering Information Data Rate Product part No Clock AS4C4M16D1A-5TCN 200MHz Commercial 0°C to 70°C 400Mbps/pin 66pin TSOPII AS4C4M16D1A-5TIN 200MHz Industrial -40°C to 85°C 400Mbps/pin 66pin TSOPII Confidential Temperature - 2/54 - Package Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A Figure 1. Pin Assignment (Top View) VDD 1 66 VSS DQ0 2 65 DQ15 3 64 VSSQ DQ1 4 63 DQ14 DQ2 5 62 DQ13 6 61 VDDQ DQ3 7 60 DQ12 DQ4 8 59 DQ11 9 58 VSSQ DQ5 10 57 DQ10 DQ6 11 56 DQ9 12 55 VDDQ 13 54 DQ8 14 53 NC VDDQ 15 52 VSSQ LDQS 16 51 UDQS 17 50 NC 18 49 VREF 19 48 VSS LDM 20 47 UDM WE 21 46 CK CAS 22 45 CK RAS 23 44 CKE CS 24 43 NC NC 25 42 NC BA0 26 41 A11 BA1 27 40 A9 A10/AP 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 33 34 VSS VDDQ VSSQ VDDQ VSSQ DQ7 NC NC VDD NC VDD Confidential - 3/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A    Figure 2. Block Diagram CK CK DLL CLOCK BUFFER COMMAND DECODER COLUMN COUNTER A10/AP CONTROL SIGNAL GENERATOR MODE REGISTER 1M x 16 CELL ARRAY (BANK #0) Column Decoder Row Decoder CS RAS CAS WE Row Decoder CKE 1M x 16 CELL ARRAY (BANK #1) Column Decoder ~ A9 A11 BA0 BA1 REFRESH COUNTER LDQS UDQS DATA STROBE BUFFER DQ0 Row Decoder ADDRESS BUFFER A0 1M x 16 CELL ARRAY (BANK #2) Column Decoder DQ Buffer Row Decoder ~ DQ15 LDM UDM Confidential - 4/54 - 1M x 16 CELL ARRAY (BANK #3) Column Decoder Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A  Pin Descriptions Table 2. Pin Details Symbol Type Description CK, CK Input Differential Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK . Input and output data is referenced to the crossing of CK and CK (both directions of the crossing) CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0, BA1 Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge). CS Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS Input Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. CAS Input Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGH " or LOW"." WE Input Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. LDQS, Input / UDQS Output Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. LDM, Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. DQ0 - DQ15 Input / Output Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and negative edges of LDQS & UDQS. The I/Os are byte-maskable during Writes. VDD Supply Power Supply: +2.5V ±0.2V UDM Confidential - 5/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A VSS Supply Ground VDDQ Supply DQ Power: +2.5V ±0.2V. Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VREF Supply Reference Voltage for Inputs: +0.5*VDDQ NC - Confidential No Connect: No internal connection, these pins suggest to be left unconnected. - 6/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A    Operation Mode Table 3 shows the truth table for the operation commands. Table 3. Truth Table (Note (1), (2)) Command State CKEn-1 CKEn DM BA0,1 A10 A0-9,11 Idle(3) H X X V BankPrecharge Any H X X V L PrechargeAll Any H X X X Write Active(3) H X X Write and AutoPrecharge Active(3) H X Read Active(3) H Read and Autoprecharge Active(3) (Extended)Mode Register Set No-Operation BankActivate L L H H X L L H L H X L L H L V L L H L L X V H Column address (A0 ~ A7) L H L L X X V L L H L H H X X V H Column address (A0 ~ A7) L H L H Idle H X X L L L L Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V H X X X L H H H X X X X Data Input Mask Enable(5) Active H X H X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 2, 4, 8, burst operation. 5. LDM and UDM can be enabled respectively. X X X Confidential Rev.1.1 Burst Stop Row address CS RAS CAS WE OP code (SelfRefresh) Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit Idle Any H L L H X X X X X X X X (PowerDown) Active Any H L L H X X X X X X X X (PowerDown) Data Input Mask Disable Active H X - 7/54 - L X X X July 2015 4Mx16 DDR1-AS4C4M16D1A  Mode Register Set (MRS) The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A11 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies. Table 4. Mode Register Bitmap BA1 BA0 A11 0 A8 0 1 X 0 A10 A9 A8 0 A7 Test Mode 0 Normal mode 0 DLL Reset 1 Test mode BA0 Mode 0 MRS 1 EMRS A7 T.M. A6 A5 CAS Latency A6 A5 A4 CAS Latency Reserved 0 0 0 Reserved 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 A4 A3 BT A2 A1 A0 Burst Length A3 Burst Type 0 Sequential A2 A1 A0 0 0 0 Address Field Mode Register Burst Length Reserved 0 0 1 2 2 0 1 0 4 3 Reserved Reserved 2.5 Reserved 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 8 Reserved Reserved Reserved Reserved 1 Interleave • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, and 8. Table 5. Burst Length A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Confidential - 8/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A • Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4, and 8. Table 6. Addressing Mode • A3 Addressing Mode 0 Sequential 1 Interleave Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 7. Burst Address ordering Burst Length 2 4 8 Start Address A2 A1 A0 X X 0 X X 1 X 0 0 X 0 1 X 1 0 X 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sequential Interleave 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 • CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC (min) ≤ CAS Latency X tCK Table 8. CAS Latency Confidential A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 clocks 1 1 1 Reserved - 9/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A • Test Mode Field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table 9. Test Mode • A8 A7 Test Mode 0 0 Normal mode 1 0 DLL Reset X 1 Test mode (BA0, BA1) Table 10. MRS/EMRS Confidential BA1 BA0 A11 ~ A0 RFU 0 MRS Cycle RFU 1 Extended Functions (EMRS) - 10/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A     Extended Mode Register Set (EMRS) The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE . The state of A0 ~ A11, BA0 and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). A1 is used for setting driver strength to normal, or weak. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes. Table 11. Extended Mode Register Bitmap BA1 BA0 A11 0 BA0 0 1 1 A10 A9 A8 A7 RFU must be set to “0” A6 DS1 Mode MRS A6 0 A1 0 Drive Strength Full EMRS 0 1 Weak 1 0 1 1 Confidential A5 A4 A3 A2 A1 A0 Address Field RFU must be set to “0” DS0 DLL Extended Mode Register Comment A0 0 DLL Enable 1 Disable RFU Reserved For Future Matched impedance Output driver matches impedance - 11/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A  Table 12. Absolute Maximum Rating Symbol Rating Item VIN, VOUT I/O Pins Voltage VDD, VDDQ Power Supply Voltage TA Ambient Temperature TSTG Storage Temperature PD Unit Note -5 - 0.5~VDDQ + 0.5 V 1,2 - 1~3.6 V 1,2 Commercial 0~70 °C 1 Industrial - 40~85 °C 1 - 55~150 °C 1 1 W 1 Power Dissipation Short Circuit Output Current IOS 50 mA 1 Note1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of the devices Note2. All voltages are referenced to VSS. Table 13. Recommended D.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Symbol VDD Parameter Power Supply Voltage Min. Max. Unit VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.7 V 2.3 2.7 V VREF Input Reference Voltage 0.49* VDDQ 0.51* VDDQ V VTT Termination Voltage VREF - 0.04 VREF + 0.04 V VIH (DC) Input High Voltage (DC) VREF + 0.15 VDDQ + 0.3 V VIL (DC) Input Low Voltage (DC) -0.3 VREF – 0.15 V VIN (DC) Input Voltage Level, CK and CK inputs -0.3 VDDQ + 0.3 V VID (DC) Input Different Voltage, CK and CK inputs 0.36 VDDQ + 0.6 V IIL Input leakage current -2 2 µA IOZ Output leakage current -5 5 µA IOH Output High Current (VOH = 1.95V) -16.2 - mA IOL Output Low Current (VOL = 0.35V) 16.2 - mA Min. Max. Unit 2 3 pF Table 14. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 °C) Symbol CIN1 Parameter Input Capacitance (CK, CK ) CIN2 Input Capacitance (All other input-only pins) 2 3 pF CI/O DM, DQ, DQS Input/Output Capacitance 4 5 pF Note. These parameters are guaranteed by design, periodically sampled and are not 100% tested. Confidential - 12/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A  Table 15. D.C. Characteristics (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Parameter & Test Condition -5 Symbol OPERATING CURRENT : One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE=LOW IDLE STANDBY CURRENT : CKE = HIGH; CS =HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-down mode; CKE=LOW; tCK=tCK(min) ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READs; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITEs; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Self Refresh Mode ; CKE≦ 0.2V;tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputs change only during Active, READ , or WRITE command Max. Unit IDD0 55 mA IDD1 60 mA IDD2P 4 mA IDD2N 30 mA IDD3P 17 mA IDD3N 45 mA IDD4R 90 mA IDD4W 85 mA IDD5 65 mA IDD6 2 mA IDD7 110 mA Figure 3. Timing Waveform for IDD7 Measurement at 200 MHz CK Operation CK CK COMMAND tRCD ACT READ AP ACT READ AP ACT READ AP ACT READ AP ACT ...pattern repeats... ADDRESS Bank 0 Row d Bank 3 Col c Bank 1 Row e Bank 0 Col d Bank 2 Row f Bank 1 Col e Bank 3 Row g Bank 2 Col f Bank 0 Row h CL=3 DQS DQ Confidential D0 a D0 a D0 a D0 a D0 b D0 b D0 b D0 b D0 c D0 c D0 c D0 c D0 d D0 d D0 d D0 d D0 e D0 e D0 e D0 e D0 f D0 f - 13/54 - Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A    Table 16. Electrical AC Characteristics (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Symbol -5 Parameter CL = 2 CL = 2.5 CL = 3 Unit Min. 7.5 6 5 0.45 0.45 Max. 12 12 12 0.55 0.55 -0.6 0.6 ns -0.7 0.7 ns ns ns ns tCK tCK tCK Clock cycle time tCH tCL tDQSCK Clock high level width Clock low level width DQS-out access time from CK, CK tAC Output access time from CK, CK tDQSQ DQS-DQ Skew - 0.4 ns tHZ DQ & DQS high-impedance time from CK / CK - 0.7 ns tLZ DQ & DQS low-impedance time from CK / CK Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS write preamble DQS write postamble DQS in high level pulse width DQS in low level pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Address and Control input setup time Address and Control input hold time DQ & DM setup time to DQS DQ & DM hold time to DQS Data Hold Skew Factor Clock half period DQ/DQS output hold time from DQS Row cycle time Refresh row cycle time Row active time Active to Read or Write Delay Row precharge time Row active to Row active delay Write recovery time Internal Write to Read command Delay Mode register set cycle time Auto precharge write recovery + Precharge time Control and Address input pulse width DQ & DM input pulse width (for each input) Self refresh exit to read command delay Exit self refresh to non-read command Refresh interval time Active to Autoprecharge Delay -0.7 0.7 ns 0.9 0.4 0.72 0 0.25 0.4 0.35 0.35 0.2 0.2 0.7 0.7 0.4 0.4 (tCL, tCH)MIN tHP - tQHS 55 70 40 15 15 10 15 2 2 tWR + tRP 2.2 1.75 200 75 tRASMIN 1.1 0.6 1.25 0.6 0.5 70k - tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK ns ns tCK tCK tRPRE tRPST tDQSS tWPRES tWPRE tWPST tDQSH tDQSL tDSS tDSH tIS tIH tDS tDH tQHS tHP tQH tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tMRD tDAL tIPW tDIPW tXSRD tXSNR tREFI tRAP Confidential - 14/54 - 15.6 - Rev.1.1 µs ns July 2015 4Mx16 DDR1-AS4C4M16D1A  Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40~85 °C) Symbol Parameter Input High Voltage (AC) VIH (AC) VIL (AC) Input Low Voltage (AC) Min. Max. Unit VREF + 0.31 - V - VREF – 0.31 V 0.7 VDDQ + 0.6 V 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V VID (AC) Input Different Voltage, CK and CK inputs VIX (AC) Input Crossing Point Voltage, CK and CK inputs Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. Power-up sequence is described in Note 6. 5. A.C. Test Conditions Table 18. SSTL_2 Interface Reference Level of Output Signals (VREF) 0.5 * VDDQ Output Load Reference to the Test Load Input Signal Levels VREF+0.35 V / VREF-0.35 V Input Signals Slew Rate 1 V/ns Reference Level of Input Signals 0.5 * VDDQ Figure 4. SSTL_2 A.C. Test Load 0.5 * VDDQ 50Ω DQ, DQS Z0=50Ω Confidential - 15/54 - 30pF Rev.1.1 July 2015 4Mx16 DDR1-AS4C4M16D1A    6. Power up Sequence Power up must be performed in the following sequence. 1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held "NOP" state and maintain CKE “LOW”. 2) Start clock and maintain stable condition for minimum 200µs. 3) Issue a “NOP” command and keep CKE “HIGH” 4) Issue a “Precharge All” command. 5) Issue EMRS – enable DLL. 6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS – with A8 to low to initialize the mode register. 7. For command/address slew rate ≧0.5V/ns and