AS4C4M4E1Q

March 2001 ® AS4C4M4EOQ AS4C4M4E1Q 4M ✕ 4 CMOS QuadCAS DRAM (EDO) family Features • Organization: 4,194,304 words × 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption - Active: 495 mW max - Standby: 5.5 mW max, CMOS I/O • Extended data out • Refresh - 4096 refresh cycles, 64 ms refresh interval for 4C4M4EOQ - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1Q - RAS-only and hidden refresh or CAS-before-RAS refresh or self-refresh • TTL-compatible • 4 separate CAS pins allow for separate I/O operation • JEDEC standard package - 300 mil, 28-pin SOJ - 300 mil, 28-pin TSOP • 5V power supply • Latch-up current ≥ 200 mA • ESD protection ≥ 2000 mV Pin arrangement SOJ VCC I/O0 I/O1 WE RAS *NC/A11 CAS0 CAS1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I/O3 I/O2 CAS3 OE A9 CAS2 NC A8 A7 A6 A5 A4 GND VCC I/O0 I/O1 WE RAS *NC/A11 CAS0 CAS1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 Pin designation TSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I/O3 I/O2 CAS3 OE A9 CAS2 NC A8 A7 A6 A5 A4 GND Pin(s) A0 to A11 RAS CAS WE I/O0 to I/O3 OE VCC GND NC Description Address inputs Row address strobe Column address strobe Write enable Input/output Output enable Power Ground No Connection AS4C4M4E0 11 12 13 14 * NC on 2K refresh version; A11 on 4K refresh version Selection guide Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum hyper page mode cycle time Maximum operating current Maximum CMOS standby current 3/22/01; v.1.0 AS4C4M4E0 4C4M4EOQ/E1Q-50 50 25 12 13 85 20 110 1.0 4C4M4EOQ/E1-60 60 30 15 15 100 24 100 1.0 Unit ns ns ns ns ns ns mA mA P. 1 of 16 tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC5 Alliance Semiconductor Copyright © Alliance Semiconductor. All rights reserved. AS4C4M4EOQ AS4C4M4E1Q ® Functional description The 4C4M4EOQ, and AS4C4M4E1Q are high performance 16-megabit CMOS Quad CAS Dynamic Random Access Memories (DRAM) organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in PC, workstation, router and switch applications. These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion. Extended data out (EDO) read mode enables 50 MHz operation using 50 ns devices. Four individual CAS pins allow for separate I/O operation which enables the device to operate in parity mode. In contrast to 'fast page mode' devices, data remains active on outputs after CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and CAS going high. Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using: • RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence. • Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data. • CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). • Normal read or write cycles refresh the row being accessed. • Self-refresh cycles Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using: • RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence. • Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data. • CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). • Normal read or write cycles refresh the row being accessed. • Self-refresh cycles The 4C4M4EOQ and AS4C4M4E1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4EOQ and AS4C4M4E1Q operate with a single power supply of 5V ± 0.5V. All provide TTL compatible inputs and outputs. 3/22/01; v.1.0 Alliance Semiconductor P. 2 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Logic block diagram for 4K refresh VCC GND Refresh controller Column decoder Sense amp Data I/O buffers I/O0 to I/O3 RAS RAS clock generator CAS CAS clock generator WE WE clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 OE Address buffers Row decoder 4,194,304 × 4 Array (16,777,216) Logic block diagram for 2K refresh VCC GND Refresh controller Column decoder Sense amp Data I/O buffers I/O0 to I/O3 RAS RAS clock generator CAS CAS clock generator WE WE clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE Address buffers Row decoder 4,194,304 × 4 Array (16,777,216) Substrate bias generator Recommended operating conditions Parameter Supply voltage 4C4M4EOQ AS4C4M4E1Q 4C4M4EOQ AS4C4M4E1Q Symbol VCC GND Input voltage Ambient operating temperature † Min 4.5 0.0 2.4 –0.5† Nominal 5.0 0.0 – – Max 5.5 0.0 VCC 0.8 Unit V V V V °C VIH VIL TA 0 70 VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. 3/22/01; v.1.0 Alliance Semiconductor P. 3 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Absolute maximum ratings Parameter Input voltage Input voltage (DQs) Power supply voltage Storage temperature (plastic) Soldering temperature × time Power dissipation Short circuit output current Symbol Vin VDQ VCC TSTG TSOLDER PD Iout Min -1.0 -1.0 -1.0 -55 – – – Max +7.0 VCC + 0.5 +7.0 +150 260 × 10 1 50 Unit V V V °C o C × sec W mA DC electrical characteristics (AS4C4M4E0/E1) -50 Parameter Symbol Test conditions 0V ≤ Vin ≤ +5.5V, Pins not under test = 0V DOUT disabled, 0V ≤ Vout ≤ +5.5V RAS, UCAS, LCAS, Address cycling; tRC=min RAS = UCAS = LCAS ≥ VIH RAS cycling, UCAS = LCAS ≥ VIH, tRC = min of RAS low after XCAS low. RAS = VIL, UCAS or LCAS, address cycling: tHPC = min RAS = UCAS = LCAS = VCC - 0.2V IOUT = -5.0 mA IOUT = 4.2 mA RAS, UCAS or LCAS cycling, tRC = min RAS = UCAS = LCAS ≤ 0.2V, WE = OE ≥ VCC - 0.2V, all other inputs at 0.2V or VCC - 0.2V Min -5 -5 – – Max +5 +5 110 2.0 Min -5 -5 – – -60 Max +5 +5 100 2.0 Unit µA µA mA mA 1,2 Notes Input leakage current IIL Output leakage current IOL Operating power supply current TTL standby power supply current ICC1 ICC2 Average power supply current, RAS refresh ICC3 mode or CBR EDO page mode average power supply ICC4 current CMOS standby power ICC5 supply current Output voltage VOH VOL – 110 – 100 mA 1 – 90 – 80 mA 1, 2 – 2.4 – – 1.0 – 0.4 110 – 2.4 – – 1.0 – 0.4 100 mA V V mA CAS before RAS refresh ICC6 current Self refresh current ICC7 – 0.6 – 0.6 mA 3/22/01; v.1.0 Alliance Semiconductor P. 4 of 16 AS4C4M4EOQ AS4C4M4E1Q ® DC electrical characteristics (AS4LC4M4E0/E1) -50 Parameter Input leakage current Symbol Test conditions IIL 0V ≤ Vin ≤ VCC (max) Pins not under test = 0V DOUT disabled, 0V ≤ Vout ≤ VCC (max) RAS, UCAS, LCAS, Address cycling; tRC=min RAS = UCAS = LCAS ≥ VIH, all other inputs at VIH or VIL RAS cycling, UCAS = LCAS ≥ VIH, tRC = min of RAS low after XCAS low. RAS = VIL, UCAS or LCAS, address cycling: tHPC = min RAS = UCAS = LCAS = VCC - 0.2V, F=0 IOUT = -2.0 mA IOUT = 2 mA RAS, UCAS or LCAS cycling, tRC = min RAS = UCAS = LCAS ≤ 0.2V, WE = OE = VCC - 0.2V, all other inputs at 0.2V or VCC 0.2V Min -5 -5 – – Max +5 +5 85 2.0 Min -5 -5 – – -60 Max +5 +5 75 2.0 Unit µA µA Notes Output leakage current IOL Operating power supply current TTL standby power supply current Average power supply current, RAS refresh mode or CBR EDO page mode average power supply current CMOS standby power supply current Output voltage ICC1 ICC2 ICC3 mA mA 4,5 – 80 – 70 mA 4 ICC4 ICC5 VOH VOL – 85 – 75 mA 4, 5 – 2.4 – – 200 – 0.4 80 – 2.4 – – 200 – 0.4 70 µA V V mA CAS before RAS refresh ICC6 current Self refresh current ICC7 – 0.3 – 0.3 mA 3/22/01; v.1.0 Alliance Semiconductor P. 5 of 16 AS4C4M4EOQ AS4C4M4E1Q ® AC parameters common to all waveforms -50 Symbol Parameter tRC tRP tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tT tREF tCP tRAL tASC tCAH Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS hold time RAS to CAS hold time CAS to RAS precharge time Row address setup time Row address hold time Transition time (rise and fall) Refresh period CAS precharge time Column address to RAS lead time Column address setup time Column address hold time Min 80 30 50 8 15 12 10 40 5 0 8 1 – 8 25 0 8 Max – – 10K 10K 35 25 – – – – – 50 32/64 – – – Min 100 40 60 10 15 12 10 50 5 0 10 1 – 10 30 0 10 -60 Max – – 10K 10K 43 30 – – – – – 50 32/64 – – – – Unit ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 4,5 17/16 6 7 Notes Read cycle -50 Symbol Parameter tRAC tCAC tAA tRCS tRCH tRRH Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Min – – – 0 0 0 Max 50 12 25 – – – Min – – – 0 0 0 -60 Max 60 15 30 – – – Unit ns ns ns ns ns ns 9 9 Notes 6 6,13 7,13 3/22/01; v.1.0 Alliance Semiconductor P. 6 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Write cycle -50 Symbol Parameter tWCS tWCH tWP tRWL tCWL tDS tDH Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Min 0 10 10 10 8 0 8 Max – – – – – – – Min 0 10 10 10 10 0 10 -60 Max – – – – – – – Unit ns ns ns ns ns ns ns 12 12 Notes 11 11 Read-modify-write cycle -50 Symbol Parameter tRWC tRWD tCWD tAWD Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Min 113 67 32 42 Max – – – – Min 135 77 35 47 -60 Max – – – – Unit ns ns ns ns 11 11 11 Notes Refresh cycle -50 Symbol Parameter tCSR tCHR tRPC tCPT CAS setup time (CAS-before-RAS) CAS hold time (CAS-before-RAS) RAS precharge to CAS hold time CAS precharge time (CBR counter test) Min 5 8 0 10 Max – – – Min 5 10 0 10 -60 Max – – – – Unit ns ns ns ns Notes 3 3 3/22/01; v.1.0 Alliance Semiconductor P. 7 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Hyper page mode cycle -50 Symbol tCPWD tCPA tRASP tDOH tREZ tWEZ tOEZ tHPC tHPRWC tRHCP Parameter CAS precharge to WE delay time Access time from CAS precharge RAS pulse width Previous data hold time from CAS Output buffer turn off delay from RAS Output buffer turn off delay from WE Output buffer turn off delay from OE Hyper page mode cycle time Hyper page mode RMW cycle RAS hold time from CAS Min 45 – 50 5 0 0 0 20 47 30 Max – 28 100K – 13 13 13 – – – Min 52 – 60 5 0 0 0 25 56 35 -60 Max – 35 100K – 15 15 15 – – – Unit ns ns ns ns ns ns ns ns ns ns 13 Notes Output enable -50 Symbol tCLZ tROH tOEA tOED tOEZ tOEH tOLZ tOFF Parameter CAS to output in Low Z RAS hold time referenced to OE OE access time OE to data delay Output buffer turnoff delay from OE OE command hold time OE to output in Low Z Output buffer turn-off time Min 0 8 – 13 0 10 0 0 Max – – 13 – 13 – – 13 Min 0 10 – 15 0 10 0 0 -60 Max – – 15 – 15 – – 15 Unit ns ns ns ns ns ns ns ns 8,10 8 Notes 8 Self-refresh cycle Std Symbol tRASS tRPS tCHS -50 Parameter RAS pulse width (CBR self refresh) RAS precharge time (CBR self refresh) CAS hold time (CBR self refresh) -60 Max – – – Min 100 105 -50 Max – – – Unit µs ns ns Notes Min 100 90 -50 3/22/01; v.1.0 Alliance Semiconductor P. 8 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Notes 1 2 3 ICC1, ICC3, ICC4, and ICC6 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC ≥ tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. These characteristics apply to AS4C4M4EOQ 5V devices. These characteristics apply to AS4C4M4E1Q 5V devices. 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AC test conditions - Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.4V and VIL = 0.8V - Input rise and fall times: 2 ns +5V R1 = 828Ω Dout 100 pF* R2 = 295Ω *including scope and jig capacitance +3.3V R1 = 828Ω Dout 50 pF* R2 = 295Ω *including scope and jig capacitance GND Figure A: Equivalent output load (AS4C4M4E0/AS4C4M4E1) GND Figure B: Equivalent output load (AS4C4M4E0/AS4C4M4E1) Key to switching waveforms Rising input Falling input Undefined output/don’t care 3/22/01; v.1.0 Alliance Semiconductor P. 9 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Read waveform tRC tRAS tRCD tRSH tRP RAS tCSH tCRP tASC tRCS tCAH tCAS CAS tRAD tASR tRAH Column address tRRH tRCH tRAL Address Row address WE tROH tROH tWEZ OE tRAC tAA tOEA tCAC tCLZ tREZ Data out tOLZ tOEZ tOFF (see note 11) DQ Early write waveform tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tRAD tASC tASR tRAH tCAH Column address tCWL tRWL tWP tWCS tWCH tCAS tRAL CAS Address Row address WE OE tDS tDH Data in DQ 3/22/01; v.1.0 Alliance Semiconductor P. 10 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Write waveform tRC tRAS tRP OE controlled RAS tCSH tCRP tRCD tRSH tCAS tRAL tRAD tRAH tASC tCAH Column address tRWL tCWL tWP CAS tASR Address Row address WE tOEH OE tOED tDS tDH DQ Data in Read-modify-write waveform tRWC tRAS tRP tCAS tCRP tRCD tCSH tRSH RAS CAS tRAD tASR tRAH Row address tAR tRAL tASC tCAH Column address tRWD tAWD tRCS tCWD tOEA tOEZ tOED tCWL tWP tRWL Address WE OE tRAC tAA tCAC tCLZ tDS tDH Data in DQ tOLZ Data out 3/22/01; v.1.0 Alliance Semiconductor P. 11 of 16 AS4C4M4EOQ AS4C4M4E1Q ® EDO page mode read waveform tRASP tRP RAS tCSH tCRP tRCD tCAS tCP tRHCP tHPC tRSH CAS tAR tRAD tASR tRAH Row Col address tRCS tASC Col address tCAH Col address tRCH tOEA tOEA tCPA tOEZ tCPA Data out tOLZ Data out tCLZ Data out tCLZ tOEZ tOFF tRRH tRAL Address WE OE tRAC tCLZ tCAC tAA DQ EDO page mode early write waveform tRASP tRAH tRWL tPC tCSH tCAS tASC tWCS tCP tRAL Col address Col address Col address tCWL tWP tWCH tOEH tCAH tRSH RAS tCRP tRCD CAS tASR tRAD Row address tAR Address WE OE tHDR tDS tDH Data in Data In Data in tOED DQ 3/22/01; v.1.0 Alliance Semiconductor P. 12 of 16 AS4C4M4EOQ AS4C4M4E1Q ® EDO page mode read-modify-write waveform tRASP tRP RAS tHPRWC tCSH tRCD tCAS tRAD tASR tRAH tASC tCAH Col ad tRWD tRCS tCWD tAWD tASC Col ad tCWL tCWD tCAH Row ad tASC tCP tCRP CAS tRAL tCAH tCPWD tCWD tAWD tOEZ tDH tDS tCLZ tCAC Data in Data out Data in Data out tDS tCPA tCLZ tCAC Data in Data out tCLZ tCAC tOED tOEA tWP tRWL tCWL Address Col address WE tOEA OE tAA tRAC DQ CAS before RAS refresh waveform tRC tRP tRAS WE = A = VIH or VIL RAS tRPC tCP tCSR tCHR CAS DQ OPEN RAS only refresh waveform tRC tRAS tRP tRPC WE = OE = VIH or VIL RAS tCRP CAS tASR tRAH Row address Address 3/22/01; v.1.0 Alliance Semiconductor P. 13 of 16 AS4C4M4EOQ AS4C4M4E1Q ® Hidden refresh waveform (read) tRC tRAS tRP tCHR tRCD tRSH tCRP tRAS tRC tRP RAS tCRP CAS tRAD tRAH tASR tASC Row tRCS Col address tRRH tOEA tAR tCAH Address WE OE tRAC tAA tCAC tCLZ tOEZ Data out tOFF DQ Hidden refresh waveform (write) tRC tRAS tRP tCHR RAS tCRP tRCD tRSH CAS tAR tRAD tRAH tASR tASC Row address tWCR tWP tWCS tWCH Col address tRWL tRAL tCAH Address WE tDS tDHR tDH Data in DQ OE 3/22/01; v.1.0 Alliance Semiconductor P. 14 of 16 AS4C4M4EOQ AS4C4M4E1Q ® CAS before RAS refresh counter test waveform tRAS tRSH tRP RAS tCSR tCHR tCPT tCAS CAS tASC tCAH tRAL Address Col address tAA tCAC tCLZ tOFF tOEZ Data out tRCS tRRH tRCH DQ Read cycle WE tROH tOEA OE tRWL tCWL tWP tWCH tWCS Write cycle WE tDH tDS DQ OE Data in tRCS tCWD tAWD tRWL tWP tCWL WE Read-Write cycle tOEA tOED OE t AA tCLZ tCAC tOEZ tDS Data out Data in tDH DQ 3/22/01; v.1.0 Alliance Semiconductor P. 15 of 16 AS4C4M4EOQ AS4C4M4E1Q ® CAS-before-RAS self refresh cycle tRP tRASS tRPS RAS tRPC tCP tCSR tCHS tRPC UCAS, LCAS tCEZ DQ Capacitance 15 Parameter Input capacitance DQ capacitance Symbol CIN1 CIN2 CDQ Signals A0 to A9 RAS, UCAS, LCAS, WE, OE DQ0 to DQ15 ƒ = 1 MHz, Ta = Room temperature Test conditions Vin = 0V Vin = 0V Vin = Vout = 0V Max 5 7 7 Unit pF pF pF 4C4M4EOQ ordering information Package \ RAS access time Plastic SOJ, 300 mil, 24/26-pin Plastic TSOP, 300 mil, 24/26-pin 5V 5V 50 ns 4C4M4EOQ-50JC 4C4M4EOQ-50TC 60 ns 4C4M4EOQ-60JC 4C4M4EOQ-60TC AS4C4M4E1Q ordering information Package \ RAS access time Plastic SOJ, 300 mil, 24/26-pin Plastic TSOP, 300 mil, 24/26-pin 5V 5V 50 ns AS4C4M4E1Q-50JC AS4C4M4E1Q-50TC 60 ns AS4C4M4E1Q-60JC AS4C4M4E1Q-60TC 4C4M4EOQ family part numbering system AS4 DRAM prefix C 4M4 E0 E0=4K refresh E1=2K refresh –XX RAS access time X C C = 5V CMOS 4M×4 LC = 3.3V CMOS Package: Commercial temperature J = SOJ 300 mil, 24/26 range, 0°C to 70 °C T = TSOP 300 mil, 24/26 3/22/01; v.1.0 Alliance Semiconductor P. 16 of 16