AS4C64M16D2B-25BCN

AS4C64M16D2B-25BCN Revision History 1Gb AS4C64M16D2B-25BCN 84 ball FBGA PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date Apr. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Features Description - The AS4C64M16D2B-25BCN is an eight bank DDR DRAM organized as 8 banks x 8Mbit x 16 (168). The AS4C64M16D2B-25BCN achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is designed to comply with the following key DDR2 SDRAM features:(1) posted CAS with additive latency, (2) write latency = read latency-1, (3) On Die Termination. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchro-nized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. High speed data transfer rates with system frequency up to 400 MHz - 8 internal banks for concurrent operation - 4-bit prefetch architecture - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 - Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6 - Write Latency = Read Latency -1 - Programmable Wrap Sequence: Sequential or Interleave - Programmable Burst Length: 4 and 8 - Automatic and Controlled Precharge Command - Power Down Mode - Auto Refresh and Self Refresh - Refresh Interval: 7.8 us at 0oC ≤ Tcase ≤ 85oC, 3.9 us at 85oC < Tcase ≤ 105oC - ODT (On-Die Termination) - Weak Strength Data-Output Driver Option - Bidirectional differential Data Strobe (Single-ended datastrobe is an optional feature) - On-Chip DLL aligns DQ and DQs transitions with CK transitions - DQS can be disabled for single-ended data strobe - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V ± 0.1V - VDDQ =1.8V ± 0.1V - Available in 84-ball FBGA for x16 component - RoHS compliant PASR Partial Array Self Refresh tRAS lockout supported Table 1. Ordering Information Part Number AS4C64M16D2B-25BCN Org 64Mx16 Temperature MaxClock (MHz) Package Commercial 0°C to +95°C 400 MHz 84-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 Confidential 5 400 MHz - 2 of 69 - 12.5 12.5 Rev.1.0 April 2017 AS4C64M16D2B-25BCN 64Mx16 DDR2 PIN CONFIGURATION (Top view: see balls through package) 8 9 2 VD D NC VS S A VSS Q UD QS VD DQ DQ1 4 VSSQ UDM B UDQS VS SQ DQ1 5 VD DQ DQ9 VD DQ C VDD Q DQ8 VD DQ DQ1 2 VSSQ DQ1 1 D DQ10 VS SQ DQ1 3 VD D NC VS S E VSS Q LD QS VD DQ DQ6 VSSQ LD M F LD QS VS SQ DQ7 VD DQ DQ1 VD DQ G VDD Q DQ0 VD DQ DQ4 VSSQ DQ3 H DQ2 VS SQ DQ5 VD DL VRE F VS S J VSS DL CK VD D CKE WE K RA S CK ODT BA 0 BA1 L CAS CS A1 0/AP A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A1 2 NC R NC NC BA2 VS S VDD Confidential 7 3 1 - 3 of 69 - VD D VS S Rev.1.0 April 2017 AS4C64M16D2B-25BCN Signal Pin Description Pin Type Function CK, CK Input The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK. CKE Input Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the Power Down mode, or the Self Refresh mode. CS Input CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A12 Input During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge . During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends on the SDRAM organization: 64M x 16 DDR CAn = CA9 In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless of state of BA0 , BA1 and BA2. BA0-BA2 Input DQx Input/ Output Data Input/Output pins operate in the same manner as on conventional DRAMs. DQ0-DQ15. DQS, (DQS) LDQS, (LDQS) UDQS, (UDQS) RDQS, (RDQS) Input/ Output Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write data. For x16 device, LDQS corresponds to the data on DQ0-DQ7; UDQS coresponds to the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complimentary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. DM, LDM,UDM Input DM is an input mask signal for write data. Input data is masked when DM is sampled high along with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading is designed to match that of DQ and DQS pins. LDM is DM for lower byte DQ0-DQ7 and UDM is DM for upper byte DQ8-DQ15. VDD, VSS Supply Power and ground for the input buffers and the core logic. VDDQ, VSSQ Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Input VDDL, VSSDL Supply ODT Input Confidential Selects which bank is to be active. SSTL Reference Voltage for Inputs Isolated power supply and ground for the DLL to provide improved noise immunity. On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM and LDM signal. ODT will be ignored if EMRS disable the function. - 4 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Simplified State Diagram Initialization Sequence CKEL OCD calibration Self Refreshing SRF CKEH PR Setting MRS EMRS MRS Idle REF All banks precharged CKEL ACT CKEH Activating CKEL Refreshing CKEL Precharge Power Down CKEL CKEL Active Power Down Automatic Sequence Command Sequence CKEH CKEL Bank Active Write Write Read Read WRA Writing RDA Read Write Reading RDA WRA RDA Writing with Autoprecharge PR, PRA PR, PRA PR, PRA Precharging Reading with Autoprecharge CKEL = CKE low, enter Power Down CKEH = CKE high, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh Note: Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/exit - among other things - are not captured in full detail. Confidential - 5 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Power up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95V max, AND - Vref tracks VDDQ/2. or - Apply VDD before or at the same time as VDDL. - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200us after stable power and clock (CK, CK), then apply NOP or deselect & take CKE high. 4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.) 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and A12.) 8. Issue a Mode Register Set command for “DLL reset”. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL. 12. At least 200 clocks after step 8, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS. Confidential - 6 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN 13. The DDR2 SDRAM is now ready for normal operation. *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Initialization Sequence after Power Up tCH tCL CK /CK tIS CKE ODT Command PRE ALL NOP 400ns tRP PRE ALL MRS EMRS tMRD tMRD DLL ENABLE DLL RESET REF tRP MRS REF tRFC tRFC EMRS tMRD EMRS ANY CMD Enable OCD Defaults min. 200 Cycle OCD Default OCD EXIT Programming the Mode Register For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, single-ended strobe and ODT (On Die Termination) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers (EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. Confidential - 7 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ''56'5$00RGH5HJLVWHU6HW056  7KHPRGHUHJLVWHUVWRUHVWKHGDWDIRUFRQWUROOLQJWKHYDULRXVRSHUDWLQJPRGHVRI''56'5$0,WFRQWUROV &$6ODWHQF\EXUVWOHQJWKEXUVWVHTXHQFHWHVWPRGH'//UHVHWW:5DQGYDULRXVYHQGRUVSHFLILFRSWLRQVWR PDNH''56'5$0XVHIXOIRUYDULRXVDSSOLFDWLRQV7KHGHIDXOWYDOXHRIWKHPRGHUHJLVWHULVQRWGHILQHG WKHUHIRUHWKHPRGHUHJLVWHUPXVWEHZULWWHQDIWHUSRZHUXSIRUSURSHURSHUDWLRQ7KHPRGHUHJLVWHULVZULWWHQ E\DVVHUWLQJORZRQ&65$6&$6:(%$DQG%$ZKLOHFRQWUROOLQJWKHVWDWHRIDGGUHVVSLQV$a$ 7KH''56'5$0VKRXOGEHLQDOOEDQNSUHFKDUJHZLWK&.(DOUHDG\KLJKSULRUWRZULWLQJLQWRWKHPRGHUHJ LVWHU7KHPRGHUHJLVWHUVHWFRPPDQGF\FOHWLPHW05'LVUHTXLUHGWRFRPSOHWHWKHZULWHRSHUDWLRQWRWKH PRGH UHJLVWHU 7KH PRGH UHJLVWHU FRQWHQWV FDQ EH FKDQJHG XVLQJ WKH VDPH FRPPDQG DQG FORFN F\FOH UHTXLUHPHQWVGXULQJQRUPDORSHUDWLRQDVORQJDVDOOEDQNVDUHLQWKHSUHFKDUJHVWDWH7KHPRGHUHJLVWHULV GLYLGHGLQWRYDULRXVILHOGVGHSHQGLQJRQIXQFWLRQDOLW\%XUVWOHQJWKLVGHILQHGE\$a$ZLWKRSWLRQVRIDQG ELWEXUVWOHQJWKV7KHEXUVWOHQJWKGHFRGHVDUHFRPSDWLEOHZLWK''56'5$0%XUVWDGGUHVVVHTXHQFHW\SH LVGHILQHGE\$&$6ODWHQF\LVGHILQHGE\$a$7KH''5GRHVQ¶WVXSSRUWKDOIFORFNODWHQF\PRGH$ LVXVHGIRUWHVWPRGH$LVXVHGIRU'//UHVHW$PXVWEHVHWWRORZIRUQRUPDO056RSHUDWLRQ:ULWHUHFRY HU\WLPHW:5LVGHILQHGE\$a$5HIHUWRWKHWDEOHIRUVSHFLILFFRGHV %$ %$    %$ $ a$    $ $ 3' $ :5 $ $ $ '// 70 $ %7 $ $ $ %XUVW/HQJWK $GGUHVV)LHOG 0RGH5HJLVWHU %XUV W/H QJ WK '//5H VHW $ PRGH $ %XUVW7 \SH  1R  1RUPDO  6HTXHQWLDO $ $ $ %/  F\FOHV@ W:5QVW&.QV7KHPRGHUHJLVWHUPXVWEHSURJUDPPHGWRWKLVYDOXH7KLVLV DOVRXVHGZLWKW53WRGHWHUPLQHW'$/ Confidential - 8 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN DDR2 SDRAM Extended Mode Register Set EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. Extended mode register(1) is written by asserting low on CS, RAS, CAS, WE and high on BA0 and low on BA1, and control-ling rest of pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling reduced strength data-output drive. A3~A5 determines the additive latency. A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Confidential - 9 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN EMRS(1) Programming BA2 BA1 BA0 A15*1~A13 A12 0 0 0*1 1 A11 A10 A9 Qoff RDQS DQS A8 A7 A6 Rtt OCD program MRS mode A5 A4 A2 A1 A0 Additive latency Rtt D.I.C DLL A6 A2 Rtt (NOMINAL) 0 0 MRS 0 0 2'7'LVDEOH 0 1 EMRS(1) 0 1 75 ohm 1 0 EMRS(2) 1 0 1 1 (0565HVHUYHG 1 1 150 ohm 50 ohm BA1 BA0 Address Field A3 Extended Mode Register A0 DLL En able 0 Enable 1 Disable A9 A8 A7 2&'RSHUDWLRQ A5 A4 A3 0 0 0 O&'H[LW 0 0 0 0 0 0 1 5HVHUYHG 0 0 1 1 0 1 0 5HVHUYHG 0 1 0 2 1 0 0 5HVHUYHG 0 1 1 3 1 1 1 (QDEOH2&'GHIDXOWV 1 0 0 4 1 0 1  1 1 0  1 1 1 Reserved   $IWHU VHtting to default, OCD mode needs to be exited by setting A9-A7 WR A 12 Qoff (Optional) Additive Latency Outpu t Dri ver Impe denc e Control Driver Size 0 Output buffer enabled A1 1 Output buffer disabled 0 Normal 100% 1 Weak 60% 2XWSXWs disabled - DQs, DQSs, DQSs, 5'46 RDQS. This feature is used in conjunction with dimm IDD meaurements when IDDQ is not desired to be included. A10 0 DQS Enable 1 Disable A11 0 1 RDQS Enable Disable Enable ,I5'QS is enabled, the '0IXQFtion is disabled. RDQS is active for reads and don’t care for writes. Strob e Fun cti on M atrix A11 (RDQS Enable) A10 (DQS Enable) RDQS/DM RDQS DQS DQS 0 (Disable) 0 (Enable) DM Hi-z DQS DQS 0 (Disable) 1 (Disable) DM Hi-z DQS Hi-z 1 (Enable) 0 (Enable) RDQS RDQS DQS DQS 1 (Enable) 1 (Disable) RDQS Hi-z DQS Hi-z  A14 and A15 is reserved for future usage. Confidential - 10 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN 1 * EMRS(2) Programming: PASR BA2 BA1 BA0 A15 *2 ~ A13 1 0 0 A12 A11 A10 A9 0 *2 A8 A7 A6 A5 A4 A3 A2 0*1 A1 A0 Extended Mode Register(2) PASR A7 High Temperature Self Refresh rate enable 0 Commercial temperature default 1 Industrial temperature option: use if Tc exceeds 85 o C Address Field *1 : BA0 , BA1, and BA2 must be programmed to 0 when setting the mode register during initialization. *2 : A14 and A15 is reserved for future usage. O *3 : While Tc > 85 C, Double refresh rate (tREFI: 3.9us) is required, and to enter self refresh mode at this temperature range it must be required an EMRS command to change itself refresh rate. The PASR bits allows the user to dynamically customize the memory array size to the actual needs. This feature allows the device to reduce standby current by refreshing only the memory arrays that contain essential data.The refresh options are full array, one-half array, one-quarter array, three-fourth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. Please see the following table. P ASR[2] P ASR[1] P ASR[0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ACTIVE SECTION Full array 1/2 array (Banks 0,1, 2, 3) 1/4 array (Bank 0, 1) 1/8 array (Bank 0) 3/4 array (Banks 2,3,4,5,6,7) 1/2 array (Banks 4, 5, 6, 7) 1/4 array (Bank 6,7) 1/8 array (Bank 7) EMRS(3) Programming: Reserved*1 BA2 0 BA1 BA0 A15 *2 ~ A13 1 1 0 *2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field Extended Mode Register(3) 0*1 *1 : EMRS(3) is reserved for future use and all bits except BA0, BA1, BA2 must be programmed to 0 when setting the mode register during initialization. *2 : A14 and A15 is reserved for future usage. Confidential - 11 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ODT (on-die termination) On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS/DQS, RDQS/RDQS configurations via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes. ODT is turned off and not supported in SELF REFRESH mode. VDDQ sw1 Rval1 VDDQ VDDQ sw2 Rval2 sw3 Rval3 DRAM Input Buffer Input Pin Rval1 sw1 VSSQ Rval2 sw2 VSSQ Rval3 sw3 VSSQ Switch (sw1, sw2, sw3) is enabled by ODT pin. Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR. Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins. Functional representation of ODT Confidential - 12 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ODT Truth Table The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10and A11 in the EMRS. To activate termination of any ofthese pins, the ODT function has to be enabled in the EMRS by address bits A6 and A2. EMRS Adress Bit A10 EMRS Adress Bit A11 DQ0~DQ7 X X DQ8~DQ15 X X LDQS X X LDQS 0 X UDQS X X UDQS 0 X LDM X X UDM X X Input Pin X=Don’t Care 0=Signal Low 1=Signal High Confidential - 13 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN DC Electrical Characteristics and Operation Conditions : Parameter / Condition Symbol min. nom. max. Units Notes Rtt eff. impedance value for EMRS(A6,A2)= 0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1 Rtt eff. impedance value for EMRS(A6,A2)= 1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1 Rtt eff. impedance value for EMRS(A6,A2)= 1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1 Deviation of VM with respect to VDDQ/2 delta VM -6 +6 % 2 1) Measurement Definition for Rtt(eff) : Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac)) 2) Measurement Definition for VM : Measure voltage (VM) at test pin (midpoint) with no load: delta VM = (( 2* VM / VDDQ) - 1 ) x 100% AC Electrical Characteristics and Operation Conditions : For speed 800 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Mode) min. max. Units 2 2 tCK tAC(min) tAC(max) + 0.7 ns 1 tAC(min) + 2 2 tCK + tAC(max) + 1 ns 3 2.5 2.5 tCK tAC(min) tAC(max) + 0.6 ns 2 tAC(min) + 2 2.5 tCK + tAC(max) + 1 ns 3 X tCK 4 tCK 4 tANPD ODT to Power Down Mode Entry Latency 3 tAXPD ODT Power Down Exit Latency 8 Notes 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. is when the ODT resistance is fully on. Both are measured from tAOND. 2) ODT turn off time min. is when the device stars to turn-off ODT resistance. ODT turn off time max. is when the bus is in high impedance. Both are measured from tAOFD. 3) For Standard Active Power-down - with MRS A12 =”0” - the non power-down timings ( tAOND, tAON, tAOFD and tAOF ) apply 4) tANPD and tAXPD define the timing limit when either Power Down Mode Timings (tAONPD, tAOFPD) or Non-Power Down Mode timings (tAOND, tAOFD) have to be applied. Confidential - 14 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN ODT Timing for Active / Standby (Idle) Mode and Standard Acti ve Power-Do wn Mode T-n T-5 T-6 T-4 T-3 T-2 T-1 T0 CK, CK tIS CKE tIS tAXPD tIS tIS ODT tANPD tAOND tAOFD Rtt tAON(min) DQ tAOF(min) tAOF(max) tAON(max) ODT1 1) Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down Mode timings have to be applied. 2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND. 3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (t AOF,max) is when the bus is in high impedance. Both are measured from tAOFD. ODT Timing for Precha rge Power-Down and Lo w Power Power -Down Mode T-7 T-5 T-6 T-4 T-3 T-2 T-1 T0 T1 CK, CK CKE ODT tAXPD tIS tIS tANPD tAOFPD,min tAOFPD,max DQ tAONPD,min tAONPD,max Rtt ODT2 1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to be applied. Confidential - 15 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses of BA0 - BA2 are used to select the desired bank. The row addresses A0 through A12 are used to determine which row to activate in the selected bank . The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0,1,2,3,4,5 and 6 are supported. Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). B ank A c tivate C ommand C yc le: tR C D = 3, A L = 2, tR P = 3, tR R D = 2 T0 T1 T2 T3 T4 Tn Tn+1 T n+2 T n+3 CK, CK Internal R AS -C AS delay tR C Dmin. Addres s B ank A B ank A B ank B C ol. Addr. R ow Addr. R ow Addr. B ank A to B ank B delay tR R D. additive latency AL=2 R AS -R AS delay tR R D. C ommand B ank A Activate P os ted C AS R ead A B ank B Activate B ank B C ol. Addr. B ank A Addr. B ank B Addr. B ank A R ow Addr. B ank A P recharge B ank B P recharge B ank A Activate R ead A B egins P os ted C AS R ead B tR P R ow P recharge T ime (B ank A) tR AS R ow Active T ime (B ank A) tR C R ow C ycle T ime (B ank A) AC T Confidential - 16 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation ( WE high ) or a write operation ( WE low ). The DDR2 SDRAM provides a wide variety of fast access modes. The boundary of the burst cycle is restricted to specific segments of the page length. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. For 8 bit burst operation ( BL = 8 ) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. Burst interruption is allowed with 8 bit burst operation. For details see the “Burst Interrupt” - Section of this datasheet. Read Burst Timing Example : (CL = 3, AL = 0, RL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T12 CK, CK C MD R E AD A NOP tC C D R E AD B NOP R E AD C NOP NO P NO P NO P NO P tC C D DQS , DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B 0 Dout B 1 Dout B 2 Dout B 3 Dout C 0 Dout C 1 Dout C 2 Dout C 3 RB Confidential - 17 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMRS. The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL. Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 -1 2 0 1 Activate Bank A R ead B ank A 3 4 5 6 7 8 9 10 11 12 CK, CK C MD W rite B ank A AL = 2 DQS , DQS WL = R L -1 = 4 CL = 3 tR C D R L = AL + C L = 5 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tR AC " P os tC AS 1 Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8 2 0 1 Activate B ank A R ead Ba nk A 3 4 5 6 7 8 9 10 11 12 CK, CK C MD DQS , DQS W rite Bank A AL = 2 W L = R L -1 = 4 CL = 3 tR C D R L = AL + C L = 5 DQ Dout0 Dout1 Dout2 Dout3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tR AC " P os tC AS 3 Confidential - 18 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN R ead followed by a write to the s a me bank , A c tiv ate to R ea d delay > tR C Dmin: A L = 1, C L = 3, R L = 4, W L = 3, B L = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK C MD R ead Bank A Activate B ank A W rite Bank A tR C D>tR C Dmin. WL = 3 DQS , DQS RL = 4 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 "tR AC " P ostC AS 5 Confidential - 19 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations ( write cycle ), or from memory locations ( read cycle ). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burstmode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the “Burst Interruption” section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length 4 8 Starting Address ( A2 A1 A0 ) Sequential Addressing (decimal) Interleave Addressing (decimal) x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 Note: 1) Page length is a function of I/O organization and column addressing. 2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR components. Confidential - 20 of 69 - Rev.1.0 April 2017 AS4C64M16D2B-25BCN Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS). Basic Burst Read Timing tC H tC L CK CK, CK CK DQS DQS , DQS DQS tR PST tR PR E DQ DO DO DO DO t DQS Qmax tQH tDQS Qmax don’t care tQ H Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK C MD P os t C A S R EAD A NO P NOP NO P NO P NO P NO P NO P NOP