AS4C64M16MD1-5BCN

AS4C64M16MD1 Revision History AS4C64M16MD1- 60-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Add -5 speed grade part number Date Darch 2014 August 2017 $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH Confidential -1- Rev.2.0 Aug 2017 AS4C64M16MD1 1 Gb (64M x 16 bit) 1.8v High Performance Mobile DDR SDRAM Features Description 4 banks x 16M x 16 organization - Data Mask for Write Control (DM) - Four Banks controlled by BA0 & BA1 - Programmable CAS Latency: 2, 3 - Programmable Wrap Sequence: Sequential or Interleave - Programmable Burst Length: 2, 4, 8 or 16 for Sequential Type 2, 4, 8 or 16 for Interleave Type - Automatic and Controlled Precharge Command - Power Down Mode - Auto Refresh and Self Refresh - Refresh Interval: 8192 cycles/64ms - Double Data Rate (DDR) - Bidirectional Data Strobe (DQS) for input and output data, active on both edges - Differential clock inputs CLK and /CLK - Power Supply 1.7V - 1.95V - Drive Strength (DS) Option: Full, 1/2, 1/4, 1/8 - Auto Temperature-Compensated Self Refresh (Auto TCSR) - Partial-Array Self Refresh (PASR) Option: Full, 1/2, 1/4, 1/8, 1/16 - Deep Power Down (DPD) mode - Operating Temperature Range • Extended -25°C to 85°C • Industrial -40°C to 85°C - 60 ball FPBGA package ALL PRODUCTS ROHS COMPLIANT The AS4C64M16MD1 is a four bank mobile DDR DRAM organized as 4 banks x 16M x 16. It achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. - All of the control, address, circuits is synchronized with the positive edge of an externally sup- plied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Additionally, the device supports low power saving features like PASR, Auto-TCSR, DPD as well as options for different drive strength. It’s ideally suitable for mobile application. -6 -5 System Frequency (fCK) 200 MHz 166 MHz Unit MHz Clock Cycle Time (tCK3) 5 6 ns Output data access Time 5 5 ns Table 1. Speed Grade Information Speed Grade – Data rate Clock Frequency 400Mbps (max) 333Mbps (max) CAS Latency tRCD (ns) tRP (ns) 3 3 15 18 15 18 200 MHz (max) 166 MHz (max) Table 2 – Ordering Information for ROHS Compliant Products Product part No Org Temperature Max Clock (MHz) Package AS4C64M16MD1-5BCN 64M x 16 Commercial - 25°C to 85°C 200 MHz 60-ball FBGA AS4C64M16MD1-5BIN 64M x 16 Industrial -40°C to 85°C 200 MHz 60-ball FBGA AS4C64M16MD1-6BCN 64M x 16 Commercial - 25°C to 85°C 166 MHz 60-ball FBGA AS4C64M16MD1-6BIN 64M x 16 Industrial -40°C to 85°C 166 MHz 60-ball FBGA Confidential -2- Rev.2.0 Aug 2017 AS4C64M16MD1 Block Diagram Row Addresses Column Addresses A0 - A9, AP, BA0, BA1 Row address buffer Column address buffer Refresh Counter Row decoder Row decoder Memory array Memory array Memory array Memory array Bank A 16384 x 1024 x16 bits Bank B 16384 x 1024 x16 bits Input buffer Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Column address counter A0 - A13, BA0, BA1 Bank C 16384 x 1024 x16 bits Output buffer Bank D 16384 x 1024 x16 bits Control logic & timing generator Confidential Strobe Gen. WE CAS RAS CS CKE UDM, LDM UDQS, LDQS CLK CLK, CLK CLK DQ0-DQ15 Data Strobe -3- Rev.2.0 Aug 2017 AS4C64M16MD1 60 BALL BGA CONFIGURATION 9 8 7 3 Top View 2 60Ball(6x10) CSP 1 A B C D 1 2 3 7 8 A VSS B VDDQ C 9 DQ15 VSSQ VDDQ DQ0 VDD DQ13 DQ14 DQ1 DQ2 VSSQ VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ DQ9 DQ10 DQ5 DQ6 VSSQ D VDDQ E E VSSQ UDQS DQ8 DQ7 LDQS VDDQ F F VSS UDM N.C. A13 LDM VDD G G CKE CK CK WE CAS RAS H H A9 A11 A12 CS BA0 BA1 J J A6 A7 A8 A10/AP A0 A1 K K VSS A4 A5 A2 A3 VDD Pin Names CLK, CLK Differential Clock Input DQ0–DQ15 Data Input/Output CKE Clock Enable LDM, UDM Data Mask CS Chip Select VDD Power (1.7V - 1.95V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for I/O’s (1.7V - 1.95V) WE Write Enable VSSQ Ground for I/O’s LDQS, UDQS Data Strobe (Bidirectional) A0–A13 Address Inputs BA0, BA1 Bank Select Confidential -4- Rev.2.0 Aug 2017 AS4C64M16MD1 Signal Pin Description Pin Type Signal Polarity Function CLK CLK Input Pulse Positive Edge The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CLK. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A13 Input Level — During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, A10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged simultaneously regardless of state of BA0 and BA1. DQx Input/ Output Level BA0, BA1 Input Level — Selects which bank is to be active. LDQS, UDQS Input/ Output Level — Data Input/Output are synchronous edges of the DQS. LDQS for DQ0-DQ7, UDQS for DQ8-DQ15. Active on both edges for data input/output. Center aligned to input data and Edge aligned to output data. UDM, LDM Input Pulse VDD, VSS Supply VDDQ VSSQ Supply Confidential Data Input/Output pins operate in the same manner as conventional DRAMs. Active High In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high. If it’s high, LDM corresponds to DQ0-DQ7, and UDM corresponds to data on DQ8-DQ15. Power and ground for the input buffers and the core logic. — — Isolated power supply and ground for the output buffers to provide improved noise immunity. -5- Rev.2.0 Aug 2017 AS4C64M16MD1 Mode Register Set The mode register stores the data for controlling the various operating modes of the mobile DDR, includes CAS latency, addressing mode, burst length, test mode, and various vendor specific options. The default value of the mode register is not defined. Therefore the mode register must be written after power up to operate the mobile DDR. The device should be activated with the CKE already high prior to writing into the Mode Register. The Mode Register is written by using the MRS command. The state of the address signals registered in the same cycle as MRS command is written in the mode register. The value can be changed as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS latency (read latency from column address) uses A6.. A4. BA0 must be set to low for normal operation. A9.. A13 is reserved for future use. BA1 selects Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. Mode Register Bitmap BA1 BA0 A13-A10(A/P) A9 A8 0 0 0 0 0 A7 A6 0 A5 A4 A3 CAS Latency BT Mode Register Access BA1 A2 A1 A0 Address Bus Mode Register Burst Length Burst Type Accessed Register A3 Type 0 Mode Register 0 Sequential 1 Extend. Mode Reg. 1 Interleaved CAS Latency A6 A5 A4 Latency 0 1 0 2 0 1 1 3 Burst Length Length A2 A1 A0 Sequential Interleave 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 All other Reserved Confidential -6- Rev.2.0 Aug 2017 AS4C64M16MD1 EMRS The Extended Mode Register is responsible for setting the Drive strength options and Partial array Self Refresh. The EMRS can be programmed by performing a normal Mode Register Setup operation and setting the BA1=1 and BA0=0. In order to save power consumption, the mobile DDR Sdram has five (PASR) options: Full array, 1/2, 1/4 ,1/8, 1/16 of Full Array. Additionally, the device has internal temperature sensor to control self refresh cycle atuomatically according to the two temperature range; Max. 40 deg C, and Max. 85 deg C. This is the device internal Temperature Compensated Self Refresh(TCSR). The device has four drive strength options: Full, 1/2, 1/4 or 1/8. Extended Mode Register Set BA1 BA0 1 0 A13-A10(A/P) A9 A8 A7 A6 0 A5 DS A4 A3 0 0 A2 A1 Address Bus A0 Mode Register PASR Extended Mode Register Access BA1 BA0 Accessed Register 0 0 Mode Register 1 0 Extend. Mode Reg. Drive Strength All other Reserved A6 A5 0 0 0 1 1/2 1 0 1/4 1 1 1/8 Internal TCSR Drive Strength Self Refresh cycle is controlled automatically by inter nal temperature sensor and control circuit according to the two temperature; Full Partial Array Self Refresh Confidential -7- Size of Refreshed Area A2 A1 A0 0 0 0 0 0 1 1/2 of Full Array (Banks 0, 1) 1/4 of Full Array (Bank 0) 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Full Array Reserved Reserved 1/8 of Full Array (BA1=BA0=A11=0) 1/16 of Full Array (BA1=BA0=A11=A10=0) Reserved Rev.2.0 Aug 2017 AS4C64M16MD1 Signal and Timing Description General Description The 1G bit mobile DDR is a 128M byte mobile DDR SDRAM. It consists of four banks. Each bank is organized as 16384 rows x 1024 columns x 16 bits. Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address bits registered coincident with the Activate command are used to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A13.. A0 select the row. Address bits A9.. A0 registered coincident with the Read or Write command are used to select the starting column location for the burst access. The regular Single Data Rate SDRAM read and write cycles only use the rising edge of the external clock input. For the mobile SDRAM the special signals DQSx (Data Strobe) are used to mark the data valid window. During read bursts, the data valid window coincides with the high or low level of the DQSx signals. During write bursts, the DQSx signal marks the center of the valid data window. Data is available at every rising and falling edge of DQSx, therefore the data transfer rate is doubled. For Read accesses, the DQSx signals are aligned to the clock signal CLK. Special Signal Description Clock Signal The mobile DDR operates with a differential clock (CLK and CLK) input. CLK is used to latch the address and command signals. Data input and DMx signals are latched with DQSx. The minimum and maximum clock cycle time is defined by tCK. The minimum and maximum clock duty cycle are specified using the minimum clock high time tCH and the minimum clock low time tCL respectively. Command Inputs and Addresses Like single data rate SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a rising edge of the clock determines a mobile DDR command. Command and Address Signal Timing VIH CLK, CLK# VIL t IS Address, CS#, RAS#, CAS#, WE#, CKE Confidential Valid Valid VIH VTT VIL t IH -8- Rev.2.0 Aug 2017 AS4C64M16MD1 Data Strobe and Data Mask Operation at Burst Reads The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The data strobe signal goes 1 clock cycle low before data is driven by the mobile DDR and then toggles low to high and high to low till the end of the burst. CAS latency is specified to the first low to high transition. The edges of the Output Data signals and the edges of the data strobe signals during a read are nominally coincident with edges of the input clock. The tolerance of these edges is specified by the parameters tAC and tDQSCK and is referenced to the crossing point of the CLK and /CLK signal. The tDQSQ timing parameter describes the skew between the data strobe edge and the output data edge. The following table summarizes the mapping of LDQS, UDQS, LDM and UDM signals to the data bus. Mapping of LDQS, UDQS, LDM and UDM Data strobe signal Data mask signal Controlled data bus LDQS LDM DQ7 .. DQ0 UDQS UDM DQ8 .. DQ15 The minimum time during which the output data is valid is critical for the receiving device. This also applies to the Data Strobe DQS during a read since it is tightly coupled to the output data. The parameters tQH and tDQSQ define the minimum output data valid window. Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble” tRPRE. This transition happens one clock prior to the first edge of valid data. Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe signals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble” tRPST. Confidential -9- Rev.2.0 Aug 2017 AS4C64M16MD1 Data Output Timing - tAC and tDQSCK T0 T1 T2 T3 T2n T3n T4 T4n T5 T5n T6 CK# CK Command 1 READ NOP NOP 1 NOP 1 NOP 1 NOP 1 NOP 1 CL = 3 tHZ tDQSCK tDQSCK tLZ tRPRE tRPST 2 DQS or LDQS/UDQS tLZ 3 T2 All DQ values, collectively tAC 4 T2n T3 tAC 4 T3n T4 T4n T5 T5n tHZ Don’t Care Notes: Confidential 1. 2. 3. 4. Commands other than NOP can be valid during this cycle. DQ transitioning after DQS transitions define tDQSQ window. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK and is the long-term component of DQ skew. -10- Rev.2.0 Aug 2017 AS4C64M16MD1 Operation at Burst Write During a write burst, control of the data strobe is driven by the memory controller. The LDQS, UDQS signals are centered with respect to data and data mask. The tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the setup and hold time parameters of data (tQDQSS & tQDQSH) and data mask (tDMDQSS & tDMDQSH). The input data is masked in the same cycle when the corresponding LDM, UDM signal is high (i.e. the LDM,UDM mask to write latency is zero.) LDQS, UDQS, LDM, and UDM Timing at Write VIH VTT VIL LDQS, UDQS tDMDQSS LDM, UDM tDMDQSS tDMDQSH tDMDQSH tQDQSH DQx Q VIH VTT VIL tQDQSH Q+1 tQDQSS Q+3 Q+2 tQDQSS Q+4 VIH VTT VIL Input Data masked Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal LDQS, UDQS changes from Hi-Z to a valid logic low. This is referred to as the data strobe Write Preamble. Once the burst of write data is concluded, given no subsequent burst write operation is initiated, the data strobe signal LDQS,UDQS transits from a valid logic low to Hi-Z. This is referred the data strobe W rite Postamble, tWPST. For mobile DRR data is written with a delay which is defined by the parameter t DQSS, write latency). This is different than the single data rate SDRAM where data is written in the same cycle as the Write command is issued. DQS Pre/Postamble at Write VIH CLK, /CLK VIL WR tDQSS tWPST tWPREH LDQS, UDQS VIH VTT VIL "Preamble" tWPRES DQx Confidential "Postamble" Q Q+1 -11- Q+2 Q+3 VIH VTT VIL Rev.2.0 Aug 2017 AS4C64M16MD1 Power-Up Sequence The following sequence is highly recommended for Power-Up : 1. Apply power and start clock. Maintain CKE and the other pins are in NOP conditions at the input 2. Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF, VTT 3. Start clock, maintain stable conditions for 200 us 4. Apply NOP and set CKE to high 5. Apply All Bank Precharge command 6. Issue Auto Refresh command twice and must satisfy minimum tRFC 7. Issue MRS (Mode Register Set command) 8. Issue a EMRS (Extended Mode Register Set command), not necessary Power Up Sequence Clock Command NOP NOP PREA AREF tRP 200 us MRS AREF tRFC EMRS tMRD tRFC ACT tMRD Mode Register Set Timing The mobile DDR should be act ivated wit h CK E already high prior to writing into the mode register. Two c loc k c ycles are required complete the w rite operation in the mode register. The mo de register contents can be changed using the sam e com mand and clock cycle requirements during operat ion as l ong as all banks are in t he idle st ate. Mode Register Set Timing Clk Command NOP PREA NOP MRS any Comm. NOP tMRD tRP Confidential NOP -12- Rev.2.0 Aug 2017 AS4C64M16MD1 Bank Activation Command (ACT) The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The mobile DDR has 4 independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank Activation command must be applied before any Read or Write operation can be executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCDRD min. for read commands and tRCDWR min. for write commands). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank activation delay time (tRRD min). Activate to Read or Write Command Timing (one bank) Clk Command ACT READ or WRITE PRE NOP ACT tRCDRD for read tRCDWR for write Bank A Row Add. Addresses Bank A Col. Add. Bank A Row Add. Bank A tRC Activate Bank A to Activate Bank B Timing Clk Command ACT Addresses Bank A Row Add. NOP ACT Bank B Row Add. tRRD Confidential -13- Rev.2.0 Aug 2017 AS4C64M16MD1 Precharge Command This command is used to precharge or close a bank that has been activated. Precharge is initiated by issuing a Precharge command at the rising edge of the clock. The Precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank addresses BA0 and BA1 select the bank to be precharged. After a Precharge command, the analog delay tRP has to be met until a new Activate command can be initiated to the same bank. Table Precharge Control A10/ AP BA1 BA0 Precharged 0 0 0 Bank A Only 0 0 1 Bank B Only 0 1 0 Bank C Only 0 1 1 Bank D Only 1 X X All Banks Precharge Command Timing Clk Command ACT Addresses Bank A Row Add PRE NOP NOP Bank A Row Add Bank A tRAS ACT tRP tRC Confidential -14- Rev.2.0 Aug 2017 AS4C64M16MD1 Self Refresh The Self Refresh mode can be used to retain the data in the mobile DDR if the chip is powered down. To set the mobile DDR into a Self Refreshing mode, a Self Refresh command must be issued and CKE held low at the rising edge of the clock. Once the Self Refresh command is initiated, CKE must stay low to keep the device in Self Refresh mode. During the Self Refresh mode, all of the external control signals are disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. An internal timing generator guarantees the self refreshing of the memory content. Self Refresh timing Clk Command NOP REFS REFX Any Comm. NOP DESEL NOP DESEL CKE Confidential -15- Rev.2.0 Aug 2017 AS4C64M16MD1 Auto Refresh The auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks must be precharged and idle before the Auto Refresh command is applied. No control of the external address pins is required once this cycle has started. All necessary addresses are generated in the device itself. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the t RFC(min). Autorefresh timing Clk Command PRECHARGE NOP AUTO REFRESH Command NOP CKE Command is AUTOREFRESH or ACT tRP tRFC Power Down Mode The Power Down Mode is entered when CKE is set low and exited when CKE is set high. The CKE signal is sampled at the rising edge of the clock. Once the Power Down Mode is initiated, all of the receiver circuits except CLK and the CKE circuits are gated off to reduce power consumption. All banks can be set to idle state or stay activate during Power Down Mode, but burst activity may not be performed. After exiting from Power Down Mode, at least one clock cycle of command delay must be inserted before starting a new command. During Power Down Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer than the refresh period (t REF) of the device. Power Down Mode timing Clk Command PRE NOP NOP Any Command NOP DESEL NOP DESEL CKE Power Down Mode entry Confidential Power Down Mode exit -16- Rev.2.0 Aug 2017 AS4C64M16MD1 Deep Power Down Mode The Deep Power Down mode is an unique function with very low standby currents. All internal volatge generators inside the mobile DDR are stopped and all memory data is lost in this mode. To enter the Deep Power Down mode all banks must be precharged. 20.1 Deep Power Down Mode Entry CLK CKE CS WE CAS RAS Addr. DQM DQ input DQ output High-Z t RP Precharge Command Deep Power Down Entry Deep Power Down Mode Normal Mode DP1.vsd The deep power down mode has to be maintained for a minimum of 100µs. Confidential -17- Rev.2.0 Aug 2017 AS4C64M16MD1 Deep Power Down Exit The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command : 1. Maintain NOP input conditions for a minimum of 200 us 2. Issue precharge commands for all banks of the device 3. Issue two or more auto refresh commands and satisfy minimum tRFC 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extende mode register CLK CK E CS RAS CAS WE 200 Deep Power Do wn exi t Confidential s tRP All banks prec harge tRC Au to refresh Auto refresh -18- Mode Register Set Exte nded Mode Regis ter Set New Com mand Acce pted Here Rev.2.0 Aug 2017 AS4C64M16MD1 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory (read cycle). The burst length is programmable and set by address bits A0 - A3 during the Mode Register Setup command. The burst length controls the number of words that will be output after a read command or the number of words to be input after a write command. One word is 32 bits wide. The sequential burst length can be set to 2, 4, 8 or 16 data words. Burst Mode and Sequence Starting Column Address Order of Access within a Burst Burst Length A3 A2 A1 A0 Type = Sequential Type = Interleaved 0 0-1 0-1 1 1-0 1-0 2 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 0 0 0 0 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0 0 0 1 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 0 0 1 0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 0 0 1 1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 0 1 0 0 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 0 1 0 1 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 0 1 1 0 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 0 1 1 1 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 1 0 0 0 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 1 0 0 1 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 1 0 1 0 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 1 0 1 1 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 1 1 0 0 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 1 1 0 1 D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 1 1 1 0 E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 1 1 1 1 F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 4 8 16 Confidential -19- Rev.2.0 Aug 2017 AS4C64M16MD1 Burst Read Operation: (READ) The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after tRCD from the bank activation. The address inputs (A8.. A0) determine the starting address for the burst. The burst length (2, 4 or 8) must be defined in the Mode Register. The first data after the READ command is available depending on the CAS latency. The subsequent data is clocked out on the rising and falling edge of LDQS, UDQS until the burst is completed. The LDQS, UDQS signals are generated by the mobile DDR during the Burst Read Operation. Burst Read Operation /CLK CLK Command Read NOP NOP NOP NOP NOP CL = 2 NOP NOP Burst length = 4 Read Postamble LDQS, UDQS Read Preamble CAS latency = 2 D-out 0 DQx D-out 1 D-out 2 D-out 3 CL = 3 LDQS, UDQS Read Postamble Read Preamble CAS latency = 3 D-out 0 DQx Confidential -20- D-out 1 D-out 2 D-out 3 Rev.2.0 Aug 2017 AS4C64M16MD1 Burst Write Operation (WRITE) The Burst Write is initiated by issuing a WRITE command at the rising edge of the clock. The address inputs (A8 .. A0) determine starting column address. Data for the first burst write cycle must be applied on the DQ pins on the first rise edge of LDQS, UDQS follow WRITE command. The time between the WRITE command and the first corresponding edge of the data strobe is tDQSS. The remaining data inputs must be supplied on each subsequent rising and falling edge of the data strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation /CLK CLK COMMAND WRITE NOP NOP tDQSS NOP tWPST LDQS, UDQS tWPRES DQx tWPREH Data-in 0 Data-in 1 Data-in 2 Data-in 3 Burst length = 4 Confidential -21- Rev.2.0 Aug 2017 AS4C64M16MD1 Burst Stop Command (BST) A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop Command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has been completed. When the Burst Stop Command is issued during a burst read cycle, read data and LDQS, UDQS go to a high-Z state after a delay which is equal to the CAS latency set in the Mode Register. The Burst Stop latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation. Burst Stop is also illegal during Read with Auto-Precharge. Burst Stop for Read /CLK CLK Command READ BST NOP NOP NOP NOP NOP NOP CL = 2 Burst St op Latency = 2 LDQS, UDQS CAS latency = 2 D-out 0 DQx D-out 1 2 CL = 3 Burst Stop Latency = 3 LDQS, UDQS CAS latency = 3 DQx Confidential D-out 0 -22- D-out 1 Rev.2.0 Aug 2017 AS4C64M16MD1 Data Mask (LDM, UDM) Function The mobile DDR has a Data Mask function that can be used only during write cycles. When the Data Mask is activated, active high during burst write, the write operation is masked immediately. The LDM, UDM to data-mask latency zero. LDM and UDM can be issued at the rising or negative edge of Data Strobe. Data Mask Timing /CLK CLK Command WRITE NOP NOP NOP NOP NOP NOP NOP LDQS, UDQS DQx D-in 0 D-in 1 D-in 2 D-in 3 D-in 4 D-in 5 D-in 6 D-in 7 LDM, UDM Data is masked out Confidential -23- Burst length = 8 Rev.2.0 Aug 2017 AS4C64M16MD1 Read Concurrent Auto Precharge Burst length = 4 T0 CAS latency = 3 T1 T2 NOP NOP T3 T4 T5 T6 READ A + AP NOP NOP T7 T8 /CLK CLK Command BANK A ACTIVATE NOP NOP NOP t RCD(min) t RAS(min) t RP BL / 2 LDQS, UDQS Begin of Auto Precharge CL = 3 D-out 0 DQx D-out 1 D-out 2 D-out 3 Concurrent Read Auto Precharge Support Asserted Command For same Bank T4 For different Bank T5 T6 T4 T5 T6 READ NO NO NO NO YES YES READ+AP YES YES NO NO YES YES ACTIVATE NO NO NO YES YES YES PRECHARGE YES YES NO YES YES YES Note: This table is for the case of Burst Length = 4, CAS Latency =3 and tWR=2 clocks When READ with Auto Precharge is asserted, new commands can be asserted at T4,T5 and T6 as shown in Table An Interrupt of a running READ burst with Auto Precharge i.e. at T4 and T5 to the same bank with another READ+AP command is allowed, it will extend the begin of the internal Precharge operation to the last READ+AP command. Interrupts of a running READ burst with Auto Precharge i.e. at T4 are not allowed when doing concurrent command to another active bank. ACTIVATE or PRECHARGE commands to another bank are always possible while a READ with Auto Precharge operation is in progress. Confidential -24- Rev.2.0 Aug 2017 AS4C64M16MD1 Write with Autoprecharge (WRITEA) If A8 is high when a Write command is issued, the Write with Auto-Precharge function is performed. The internal precharge begins after the write recovery time tWR and tRAS(min) are satisfied. If a Write with Auto Precharge command is initiated, the mobile DDR automatically enters the precharge operation at the first rising edge of CLK after the last valid edge of DQS (completion of the burst) plus the write recovery time tWR. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (tRP) has been satisfied. If tRAS(min) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied. Write Burst with Auto Precharge Burst length = 4 T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP T7 T8 /CLK CLK Command BANK A ACTIVATE NOP WRITE A + AP NOP NOP NOP t RAS(min) t WR t RP BL / 2 Begin of Auto Precharge LDQS, UDQS D-in 0 DQx D-in 1 D-in 2 D-in 3 Note: tWR starts at the first rising edge of clock after the last valid edge of the 4 DQSx. Table Concurrent Write Auto Precharge Support For same Bank For different Bank Asserted Command T3 T4 T5 T6 T7 T8 T3 T4 T5 T6 T7 WRITE NO NO NO NO NO NO NO YES YES YES YES WRITE+AP YES NO NO NO NO NO NO YES YES YES YES READ NO NO NO NO NO NO NO NO NO NO YES READ+AP NO NO NO NO NO NO NO NO NO NO YES ACTIVATE NO NO NO NO NO NO YES YES YES YES YES PRECHARGE NO NO NO NO NO NO YES YES YES YES YES When Write with Auto Precharge is asserted, new commands can be asserted at T3.. T8 as shown in Table . An Interrupt of a running WRITE burst with Auto Precharge i.e. at T3 to the same bank with another WRITE+AP command is allowed as long as the burst is running, it will extend the begin of the internal Precharge operation to the last WRITE+AP command. Interrupts of a running WRITE burst with Auto Precharge i.e. at T3 are not allowed when doing concurrent WRITE s to another active bank. Consecutive WRITE or WRITE+AP bursts (T4.. T7) to other open banks are possible. ACTIVATE or PRECHARGE commands to another bank are always possible while a WRITE with Auto Precharge operation is in progress. Confidential -25- Rev.2.0 Aug 2017 AS4C64M16MD1 Write interrupted by Read /CLK CLK Command Write NOP tDQSS(min) NOP Last valid data Read tWTR NOP NOP NOP CL = 3 LDQS UDQS DQx D-in 0 D-in 1 D-in 2 D-in 3 D-in 4 D-in 5 D-out 0 D-out 1 LDM UDM Data is masked by Read Data must be masked Confidential -26- Burst length = 8 CL = 3 Rev.2.0 Aug 2017 AS4C64M16MD1 Write Interrupted by a Precharge A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank. Random column access is allowed. A Write Recovery time (t WR) is required from the last data to Precharge command. When Precharge command is asserted, any residual data from the burst write cycle must be masked by LDM,. UDM. Write interrupted by Precharge /CLK CLK Command Write bank A tDQSSmin NOP NOP NOP PRE Write bank B NOP tDQSSmin tWR Last valid data NOP LDQS UDQS DQx D-in 0 D-in 1 D-in 2 D-in 3 D-in 4 D-in 5 D-in 0 D-in 1 LDM UDM Data must be masked Confidential -27- Data is masked by Precharge Burst length = 8 Rev.2.0 Aug 2017 AS4C64M16MD1 Command Table Table Command Overview Operation Code DESEL CKE n-1 CKE n CS# RAS# CAS# WE# BA0 BA1 A10 A0-9 A11,12 H X H X X X X X X X X Device Deselect No operation NOP H X L H H H X X X Mode Register Setup MRS H X L L L L 0 0 OPCODE Extended Mode Register Setup EMRS H X L L L L 0 1 OPCODE Bank Activate ACT H X L L H H BA BA Row Address Read READ H X L H L H BA BA L Read with Auto Precharge READA H X L H L H BA BA H Col. Write Command WRITE H X L H L L BA BA L Col. H X L H L L BA BA H Col. Write Command with Auto Precharge WRITEA Col. Burst Stop BST H X L H H L X X X X Precharge Single Bank PRE H X L L H L BA BA L X X Precharge All Banks PREAL H X L L H L X X H Autorefresh REF H H L L L H X X X X Self Refresh Entry REFX H L L L L H X X X X Self Refresh Exit SREFEX L L H H H L X H X H X H X X X X X X X X Power Down Mode Entry (Note 1) PWDNEN H H L L H L X H X H X H X X X X X X X X Power Down Mode Exit PWDNEX L H H L X valid X valid X valid X X X X Deep Power Down Mode Entry Idle H L L H H L X X X X Deep Power Down Mode Exit Deep power down L H X X X X X X X X Note: 1: The Power Down Mode Entry command is illegal during Burst Read or Burst Write operations. Confidential -28- Rev.2.0 Aug 2017 AS4C64M16MD1 Function Truth Table I Current State IDLE ROW ACTIVE READ READ with Auto Precharge Confidential Command Address Action Notes DESEL X NOP 3 NOP X NOP 3 BST X NOP 3 READ / READA BA,CA,A10 ILLEGAL 1 WRITE / WRITEA BA,CA,A10 ILLEGAL 1 ACT BA, RA Bank Active PRE / PREAL BA, A10 NOP AREF / SREF X AUTO-Refresh or Self-Refresh MRS / EMRS Op-Code Mode Register Set or Extended Mode Register Set DESEL X NOP NOP X NOP BST X NOP READ / READA BA, CA, A10 Begin Read, Determine Auto Precharge 9 WRITE / WRITEA BA, CA, A10 Begin Write, Determine Auto Precharge 9 ACT BA, RA ILLEGAL PRE / PREAL BA, A10 Precharge / Precharge All AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X Continue burst to end NOP X Continue burst to end BST X Terminate Burst READ / READA BA, CA, A10 Terminate burst, Begin New Read, Determine AutoPrechgarge WRITE / WRITEA BA, CA, A10 ILLEGAL 2, 7 ACT BA, RA ILLEGAL 1 PRE / PREAL BA ,A10 Terminate Burst / Precharge AREF / SREF X ILLEGAL MRS / EMRS Op-Code ILLEGAL DESEL X Continue burst to end, Precharge NOP X Continue burst to end, Precharge BST X ILLEGAL READ / READA BA, CA, A10 ILLEGAL WRITE / WRITEA BA, CA, A10 ILLEGAL ACT BA, RA ILLEGAL 1 PRE / PREAL BA ,A10 ILLEGAL 1 AREF / SREF X ILLEGAL MRS / EMRS Op-Code ILLEGAL -29- 4 1, 5 6 7 Rev.2.0 Aug 2017 AS4C64M16MD1 Function Truth Table I Current State WRITE WRITE with Auto Precharge Command Action Notes DESEL X Continue burst to end NOP X Continue burst to end BST X ILLEGAL READ / READA BA, CA, A10 Terminate Burst, Begin Read, Determine AutoPrecharge. 7, 8 WRITE / WRITEA BA, CA, A10 Terminate Burst, Begin new Write, Determine AutoPrecharge 2, 7 ACT BA, RA ILLEGAL 1 PRE / PREAL BA , A10 Terminate Burst , Precharge 8 AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X Continue burst to end, Precharge NOP X Continue burst to end, Precharge BST X ILLEGAL READ / READA BA, CA, A10 ILLEGAL WRITE / WRITEA BA, CA, A10 ILLEGAL ACT BA, RA ILLEGAL 1 PRE / PREAL BA , A10 ILLEGAL 1 AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X NOP ( Row Active after tRCD) NOP X NOP ( Row Active after tRCD) BST X NOP ( Row Active after tRCD) BA, CA, A10 ILLEGAL 1, 9 BA, CA, A10 ILLEGAL 1, 9 BA, RA ILLEGAL 1, 5 PRE / PREAL BA , A10 ILLEGAL 1, 6 AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X NOP ( Row Idle after tRP) NOP X NOP ( Row Idle after tRP) BST X NOP ( Row Idle after tRP) READ / READA BA, CA, A10 ILLEGAL 1 BA, CA, A10 ILLEGAL 1 ACT BA, RA ILLEGAL 1 PRE / PREAL BA , A10 NOP ( Row Idle after tRP) AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL READ / READA ROW WRITE / WRITEA ACTIVATING ACT PRECHARGE WRITE / WRITEA Confidential Address -30- 1 Rev.2.0 Aug 2017 AS4C64M16MD1 Function Truth Table I Current State Command Notes X NOP (Row Active after tWR) NOP X NOP (Row Active after tWR) BST X NOP (Row Active after tWR) BA, CA, A10 Begin Read, Determine Auto-Prechgarge BA, CA, A10 Begin Write, Determine Auto-Prechgarge BA, RA ILLEGAL 2 PRE / PREAL BA ,A10 ILLEGAL 1, 10 AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X NOP (Precharge after tWR) NOP X NOP (Precharge after tWR) BST X NOP (Precharge after tWR) BA, CA, A10 ILLEGAL 1, 2 BA, CA, A10 ILLEGAL 1 BA, RA ILLEGAL 1 PRE / PREAL BA ,A10 ILLEGAL 1 AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X NOP (Idle after t RC) NOP X NOP (Idle after tRC) BST X NOP (Idle after tRC) READ / READA BA, CA, A10 ILLEGAL WRITE / WRITEA BA, CA, A10 ILLEGAL ACT BA, RA ILLEGAL PRE / PREAL BA ,A10 ILLEGAL AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL DESEL X NOP (Idle after two clocks) NOP X NOP (Idle after two clocks) BST X NOP (Idle after two clocks) BA, CA, A10 ILLEGAL BA, CA, A10 ILLEGAL BA, RA ILLEGAL PRE / PREAL BA ,A10 ILLEGAL AREF / SREF X ILLEGAL MRS / EMRS OP-Code ILLEGAL READ / READA WRITE RECOVERING WRITE / WRITEA with AUTOPRECHARGE ACT (EXTENDED) READ / READA MODE WRITE / WRITEA REGISTER SET ACT Confidential Action DESEL READ / READA WRITE WRITE / WRITEA RECOVERING ACT REFRESH Address -31- 2 11 Rev.2.0 Aug 2017 AS4C64M16MD1 Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: Note: All entries assume the CKE was High during the preceding clock cycle 1. Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank 2. Must satisfy bus contention, bus turn around, write recovery requirements. 3. If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and CLK# will be disabled. 4. If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter SelfRefresh Mode. All input buffers except CKE will be disabled. 5. Illegal, if tRRD is not satisfied. 6. Illegal, if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must mask two preceding data bits with the DM pin. 9. Illegal, if tRCD is not satisfied. 10. Illegal, if tWR is not satisfied. 11. Illegal, if tRC is not satisfied. Abbreviations: H High Level L Low Level X Don tCare V Valid Data Input RA Row Address BA Bank Address PA Precharge All NOP No Operation CA Column Address Ax Address Line x Confidential -32- Rev.2.0 Aug 2017 AS4C64M16MD1 FUNCTION TRUTH TABLE for CKE Current State SELF REFRESH POWER DOWN ALL BANKS IDLE All other states CKE n-1 CKE n CS# H L L L L H H L H L RAS# CAS# WE# Address Action Notes L H X Self Refresh Entry 1 X X X X Exit Self-Refresh 1 L H H H X Exit Self-Refresh 1 H L H H L X ILLEGAL 1 L H L H H X X ILLEGAL 1 L H L L L X X ILLEGAL 1 L L X X X X X NOP ( Maintain Self Refresh) 1 H X X X X X X INVALID L H X X X X X Exit Power Down ( Idle after tPDEX) L L X X X X X NOP ( Maintain Power Down) H H X X X X X Refer to Function Truth Table 2 H L L L L H X Enter Self Refresh 3 H L H X X X X Enter Power-Down 2 H L L H H H X Enter Power-Down 2 H L L H H L ILLEGAL 2 H L L H L X ILLEGAL 2 H L L L X X ILLEGAL 2 L X X X X X X Refer to Power Down in this table H H X X X X X Refer to Funtion Truth Table 1 Note: 1. CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any commands other than EXIT are executed. Note: 2. Power Down can be entered when all banks are idle (banks can be active or precharged) Note: 3. Self Refresh can be entered only from the Precharge / Idle state. Abbreviations: H High Level L Low Level X Don't Care V Valid Data Input RA Row Address BA Bank Address PA Precharge All NOP No Operation CA Column Address Confidential -33- Rev.2.0 Aug 2017 AS4C64M16MD1 Mobile DDR SDRAM operation State Diagram Power applied DEEP POWER DOWN DPDSX POWER ON ACT : Active BST : Burst PCG. ALL BANKS CKEL : Enter PowerDown DPDS CKEH : Exit Power-Down (E)MRS SET SELF REFRESH MRS, EMRS REFS CKEL DPDSX : Exit Deep PowerDownEMRS REFSX IDLE ALL BANK PCG. EMRS : Ext. Mode Reg. Set REFA CKEH PCG. POWER DOWN AUTO REFRESH ACT ACTIVE POWER DOWN CKEH ROW ACTIVE PREALL : Precharge All Banks BST REFA : Auto Refresh READ WRITE MRS : Mode Register Set PRE : Precharge BURST STOP CKEL DPDS : Enter Deep Power-Down REFS : Enter Self Refresh WRITE READ WRITE WRITEA READ : Read w/o Auto Precharge READA WRITEA WRITE A REFSX : Exit Self Refresh READ READ READA PRE READA : Read with Auto Precharge READ A PRE PRE WRITE : Write w/o Auto Precharge Precharge ALL COMMAND Input WRITEA : Write with Auto Precharge AUTOMATIC Sequence Confidential -34- Rev.2.0 Aug 2017 AS4C64M16MD1 IDD Max Specifications and Conditions Version Conditions Symbol -5 -6 Unit Operating current - One bank Active-Precharge; tRC = tRC (min); tCK = tCK (min); CKE = High; CS = High between valid command; Address inputs are switching every 2 clock cycles; Data bus inputs are stable IDD0 60 55 mA Precharge power-down standby current; All banks idle; CKE = Low; CS = High; tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable IDD2P 2 2 mA Precharge power-down standby current; Clock stopped; All banks idle; CKE = Low; CS = High; CK = Low; CK = High; Address and control inputs are switching; Data bus inputs are stable IDD2PS 2 2 mA Precharge nonpower-down standby current; All banks idle; CKE = High; CS = High; tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable IDD2N 25 25 mA Precharge nonpower-down standby current; Clock stopped; All banks idle; CKE = High; CS = High; CK = Low; CK = High; Address and control inputs are switching; Data bus inputs are stable IDD2NS 18 18 mA Active power-down standby current; One bank active; CKE = Low; CS = High; tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable IDD3P 2 2 mA Active power-down standby current; Clock stopped; One bank active; CKE =Low; CS = High; CK = Low; CK = High; Address and control inputs are switching; Data bus inputs are stable IDD3PS 2 2 mA Active nonpower-down standby current; One bank active; CKE = High; CS = High; tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable IDD3N 25 25 mA IDD3NS 18 18 mA Operating current - burst read; One bank active; Burst length = 4; tCK = tCK (min); Continuous Read burst; Address inputs are switching every 2 clock cycles; 50% of data changing at every burst; lout = 0 m A IDD4R 90 85 mA Operating current - burst write; One bank active; Burst length = 4; tCK = tCK (min); Continuous Write burst; Address inputs are switching every 2 clock cycles; 50% of data changing at every burst IDD4W 90 85 mA Auto refresh current; Burst refresh; CKE = High; Address and control inputs are switching; Data bus inputs are stable IDD5 90 90 mA Deep Power Down Current; Address and control inputs are stable; Data bus inputs are stable IDD8 5 5 uA Active nonpower-down standby current; Clock stopped; One bank active; CKE = High; CS = High; CK = Low; CK = High; Address and control inputs are switching; Data bus inputs are stable Confidential -35- Rev.2.0 Aug 2017 AS4C64M16MD1 Partial Array Self Refresh Current (PASR) Parameter & Test Condition Extended Mode Register A[2:0] Tcase [oC] Symb. max. Unit Self Refresh Current Self Refresh Mode CKE = 0.2V, tck = infinity, full array activations, all banks 85oC max. ICC6 2.0 mA Self Refresh Current Self Refresh Mode CKE = 0.2V, tck = infinity, 1/2 array activations 85oC max. ICC6 1.6 mA Self Refresh Current Self Refresh Mode CKE = 0.2V, tck = infinity, 1/4 array activation 85oC max. ICC6 1.4 mA Self Refresh Current Self Refresh Mode CKE = 0.2V, tck = infinity, 1/8 array activation 85oC max. ICC6 1.2 mA Self Refresh Current Self Refresh Mode CKE = 0.2V, tck = infinity, 1/16 array activation 85oC max. ICC6 1.2 mA Confidential -36- Note Rev.2.0 Aug 2017 AS4C64M16MD1 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply relative to VSS VDD, VDDQ -0.5 ~ 2.7 V TSTG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Storage temperature Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Capacitance ( VDD = 1.8V, TA = 25°C, f = 1MHz ) Parameter Symbol Min Max Unit Input capacitance ( A0~A13, BA0~BA1,CKE, CS, RAS, CAS, WE ) CIN1 1.5 3.0 pF Input capacitance ( CK, CK ) CIN2 1.5 3.0 pF Data & DQS input/output capacitance ( DQ0~DQ15 ) COUT 3.0 5.0 pF Input capacitance ( DMs ) CIN3 3.0 5.0 pF Confidential -37- Rev.2.0 Aug 2017 AS4C64M16MD1 Power & DC Operating Conditions (LVCMOS In/Out) Recommended operating conditions ( Voltage referenced to VSS = 0V ) Parameter Symbol Min Typ Max Unit Device Supply voltage VDD 1.7 1.8 1.95 V Output Supply voltage VDDQ 1.7 1.8 1.95 V Input logic high voltage VIH 0.7*VDDQ - VDDQ+0.30 V Input logic low voltage VIL -0.3 - 0.3*VDDQ V Input Leakage current II -2 - 2 uA IOZ -5 - 5 uA Output Leakage current AC Input Operating Conditions Recommended operating conditions ( Voltage referenced to VSS = 0V, VDD = 1.7V ~1.95V ) Parameter Symbol Min Typ Max Unit Input High (Logic 1) Voltage; DQ VIH VCCQ*0.8 - VCCQ+0.3 V Input Low (Logic 0) Voltage; DQ VIL -0.3 - 0.2* VDDQ V Clock Input Crossing Point Voltage; CK and CK VIX 0.4*VDDQ - 0.6*VDDQ V AC Operating Test Conditions Recommended operating conditions ( Voltage referenced to VSS = 0V, VDD = 1.7V ~1.95V ) Parameter AC input levels (Vih/Vil) Value Unit 0.8*VDDQ / 0.2*VDDQ V 0.5*VDDQ V 1.0 V/ns 0.5*VDDQ V Input timing measurement reference level Input signal minimum slew rate Output timing measurement reference level Output load condition See below figures 1.8V Vtt=0.5 x VDDQ 13.9K VOH (DC) = 0.9 x VDDQ, IOH = -0.1mA VOL (DC) = 0.1 x VDDQ, IOL = 0.1mA Output 10.6K 30pF Output 50 Z0=50 30pF DC Output Load Circuit AC Output Load Circuit Confidential -38- Rev.2.0 Aug 2017 AS4C64M16MD1 AC Timing Parameters & Specification AC CHARACTERISTICS -5 PARAMETER SYMBOL -6 MIN MAX Output data access time from CK/CK t AC 2 5 CK high-level width tCH 0.45 0.55 CK low-level width tCL 0.45 CK (3) 5 DQ and DM input hold time relative to DQS tDH 0.4 DQ and DM input setup time relative to DQS tDS Clock cycle time CL = 3 DQ and DM input pulse width (for each input) t t ns 0.45 0.55 tCK 0.55 0.45 0.55 tCK - 6 - ns 1 0.6 ns 5,6 0.4 0.6 ns 5,6 1.6 ns DIPW 1.4 2 5 DQS input high pulse width tDQSH 0.4 0.6 DQS input low pulse width t 0.4 0.6 DQS-DQ skew, DQS to last DQ valid, per group, per access t Write command to first DQS latching transition tDQSS DQSL DQSQ Half clock period tHP MAX UNITS NOTES 5 tDQSCK Access window of DQS from CK/CK MIN 5 ns 0.4 0.6 tCK 0.4 0.6 t 0.4 0.75 1.25 0.75 tCH, tCH, t t CL 3 CK 0.5 ns 1.25 tCK 1 ns CL Data-out high-impedance window from CK/CK t HZ 0.4 Data-out low-impedance window from CK/CK tLZ 1 1 ns Address and control input hold time tIH 0.9 1.1 ns 1 Address and control input setup time t IS 0.9 1.1 ns 1 MRD 2 2 HP - QHS HP - QHS LOAD MODE REGISTER command cycle time t DQ-DQS hold, DQS to first DQ to go non-valid, per access 0.6 t t QH 0.4 0.6 t t CK CK t t ns t Data hold skew factor t ACTIVE to PRECHARGE command t RAS 40 ACTIVE to READ with Auto precharge command t RAP 15 15 ns t RC 55 60 ns RFC 72 72 ns RCD 15 18 ns t 15 18 ns QHS ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period t ACTIVE to READ or WRITE delay t PRECHARGE command period Confidential RP 0.5 -39- 70K 42 0.65 ns 70K ns Rev.2.0 Aug 2017 AS4C64M16MD1 AC CHARACTERISTICS PARAMETER -5 -6 SYMBOL MIN MAX MIN DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble t RPST 0.4 0.6 0.4 0.6 t t RRD 10 12 ns tWPRE 0.25 0.25 tCK WPRES 0 0 ACTIVE bank A to ACTIVE bank B command DQS write preamble DQS write preamble setup time DQS write postamble t t WPST 0.4 tWR 15 15 WTR 2 2 Write recovery time Internal WRITE to READ command delay t Average periodic refresh interval tREFI Power down exit time Confidential tPDEX 0.6 0.4 7.8 1*t CK +tIS -40- MAX UNITS NOTES CK ns 0.6 t 4 CK ns t 7.8 CK us 1*t CK +tIS ns Rev.2.0 Aug 2017 AS4C64M16MD1 1. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS tIH (V/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns. 2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP. 3. tAC(mi n) value is measured at the high Vdd(1.95V) and cold temperature(-25 C). tAC (max) value is measured at the low Vdd(1.7V) and hot temperature(85 C). tAC is measured in the device with half driver strength and under the AC output load condition. 4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 5. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate tDS tDH (V/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns. 6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate tDS (ns/V) (ps) 0 tDH (ps) 0 0 0.25 +50 +50 0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V. Confidential -41- Rev.2.0 Aug 2017 AS4C64M16MD1 Package Diagram 60-BALL 0.8mm pitch BGA Confidential -42- Rev.2.0 Aug 2017 AS4C64M16MD1 PART NUMBERING SYSTEM AS4C DRAM 64M16MD1 64M16=64Mx16 MD1=MobileDD R1 5/6 5=200MHz 6=166MHz B B = FBGA C/I C=Commercial (-25¡ C
85¡ C) I=Industrial (-40¡ C
85¡ C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential -43- Rev.2.0 Aug 2017