AS4C64M16MD1A-5BIN
Revision History
1G (64M x 16) Low Power DDR SDRAM 60ball FBGA Package
AS4C64M16MD1A-5BIN
Revision
Rev 1.0
Details
Preliminary datasheet
Date
Jan 2018
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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DDR Sync DRAM Features
• Functionality
- Double-data-rate architecture ; two data transfers
per CLK cycle.
- Bidirectional data strobe per byte data (DQS).
- No DLL ; CLK to DQS is not Synchronized.
- Differential CLK inputs( CLK and /CLK ).
- Commands entered on each positive CLK edge.
- DQS edge-aligned with data for Reads;
center-aligned with data for Writes.
- Four internal banks for concurrent operation.
- Data masks (DM) for masking write data-one mask
per byte.
- Programmable burst lengths : 2, 4, 8, 16.
- Programmable CAS Latency : 2, 3.
- Concurrent auto pre-charge option is supported.
- Auto refresh and self refresh modes.
- Status read register (SRR)
- LVCMOS-compatible inputs.
• Low Power Features
- Low voltage power supply.
- Auto TCSR (Temperature Compensated Self Refresh).
- Partial Array Self Refresh power-saving mode.
- Deep Power Down Mode.
- Driver Strength Control.
• Operating Temperature Ranges
- Industrial (-40℃ to +85℃).
• Package
- 60-Ball FBGA ( 8 X 9 X 0.8mm )
• Functional Description
The AS4C64M16MD1A Family is high-performance
CMOS Dynamic RAMs (DRAM) organized as 64M x 16.
These devices feature advanced circuit design to provide
low active current and extremely low standby current. The
device is compatible with the JEDEC standard Low
Power DDR SDRAM specifications.
• Configuration
- 64 Meg X 16 (16 Meg X 16 X 4Bank ).
Table 1. Ordering Information
Product part No
AS4C64M16MD1A-5BIN
Org
64M x 16
Temperature
Max Clock (MHz)
200 Hz
Industrial -40°C to 85°C
Package
60-ball FBGA
Table 2. Speed Grade Information
Speed Grade
DDR1-400
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Clock Frequency CAS Latency
200 Hz
3
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tRCD (ns)
15
tRP (ns)
15
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Logic Block Diagram
Refresh
Self
Refresh
Counter
Row Active
Row
Pre_
Decoder
Column Active
Row decoders
Row decoders
Row decoders
Row decoders
State Machine
/ CLK
CLK
CKE
/CS
/WE
/CAS
/RAS
Column
Pre_
Decoder
Bank Select
BA0, BA1
Address Buffers
A0-A13
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Bank3
Bank2
Bank1
Bank0
16M x 16
Memory
Array
Column decoders
Sense amp
Write Drivers
DM Mask
Column
Add
Counter
Address
Register
Input
Data
Controller
Logic
Data Strobe
Receiver
Data
Input
Register
DM0 –
DM1
DQS0 –
DQS1
DQ0 –
DQ15
Data
Output
Register
Burst
Length
Mode Register
CAS
Latency
Data Out Control
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Data Strobe
Transmitter
DQS0 –
DQS1
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Pin Configuration
60 ball 0.8mm pitch FBGA(8mm x 9mm)
Top View
1
2
3
A
VSS
DQ15
7
8
9
VSSQ
VDDQ
DQ0
VDD
B
VDDQ DQ13 DQ14
DQ1
DQ2
VSSQ
C
VSSQ DQ11 DQ12
DQ3
DQ4
VDDQ
D
VDDQ
DQ10
DQ5
DQ6
VSSQ
E
VSSQ DQS1
DQ8
DQ7
DQS0
VDDQ
F
VSS
DM1
NC
A13
DM0
VDD
G
CKE
CLK
/CLK
/WE
/CAS
/RAS
H
A9
A11
A12
/CS
BA0
BA1
J
A6
A7
A8
A10/AP
A0
A1
K
VSS
A4
A5
A2
A3
VDD
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DQ9
4
5
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General Description
The 1Gb Low Power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing
1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the 268,435,456-bit banks is
organized as 16,384 rows by 1,024 columns by 16 bits.
The 1Gb Low Power DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to
transfer four data words per clock cycle at the I/O balls. A single read or write access for the 1Gb DDR
SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the Low Power DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for
WRITEs. The x16 offering has two data strobes.
The 1Gb Low Power DDR SDRAM operates from a differential clock (CLK and /CLK); the crossing of CLK
going HIGH and /CLK going LOW will be referred to as the positive edge of CLK. Commands (address and
control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the Low Power DDR SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select
the bank and the starting column location for the burst access.
The Low Power DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,4,8 or 16. An
auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of Low Power DDR SDRAMs allows
for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
time.
An auto-refresh mode is provided, along with a power saving power-down mode. Self refresh mode offers
temperature compensation through an on-chip temperature sensor and partial array self refresh, which allow
users to achieve additional power saving. The temperature sensor is enabled by default and the partial array
self refresh can be programmed through the extended mode register.
Notes :
1. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is
divided into two bytes. For the first byte (DQ0–DQ7) DM refers to DM0 and DQS refers to DQS0. For the
second byte (DQ8–DQ15) DM refers to DM1 and DQS refers to DQS1.
2. Complete functionality is described throughout the document and any page or diagram may have been
simplified to convey a topic and may not be inclusive of all requirements.
3. Any specific requirement takes precedence over a general statement.
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Pin Description
Symbol
CLK, /CLK
CKE
/CS
/RAS, /CAS,
/WE
Type
Description
Clock: CLK is the system clock input. CLK and /CLK are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge of CLK and negative edge of
Input
/CLK. Input and output data is referenced to the crossing of CLK and /CLK (both directions of the
crossing).
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, input
buffers, and output drivers. Taking CKE LOW allows PRECHARGE power-down and SELF
Input REFRESH operations (all banks idle), or ACTIVE power-down (row active in any bank). CKE is
synchronous for all functions expect SELF REFRESH exit. All input buffers (except CKE) are
disabled during power-down and self refresh modes.
Chip select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder.
Input All commands are masked when /CS is registered HIGH. /CS provides for external bank selection
on systems with multiple banks. /CS is considered part of the command code.
Input
Command inputs: /RAS, /CAS, and /WE (along with /CS) define the command being entered.
DM0–DM1
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of
Input
DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS
balls. For the x16, DM0 corresponds to DQ0 – DQ7, DM1 corresponds to DQ8–DQ15.
BA0, BA1
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or
PRECHARGE command is applied. BA0 and BA1 also determine which mode register
Input
(standard mode register or extended mode register) is loaded during a LOAD MODE REGISTER
command.
A0-A13
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto
pre-charge bit (A10) for READ or WRITE commands, to select one location out of the memory array
in the respective bank. During a PRECHARGE command, A10 determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH).
Input
The address inputs also provide the op-code during a LOAD MODE REGISTER command. BA0
and BA1 define which mode register (mode register or extended mode register) is loaded during
the LOAD MODE REGISTER command.
For 1Gb(X16), Row Address : A0 ~ A13, Column Address: A0 ~ A9.
DQ0-DQ15
I/O
Data input/output: Data bus for x16.
DQS0DQS1
I/O
Data strobe: Output with read data, input with write data. DQS is edge aligned with read data,
centered in write data. It is used to capture data. For the x16, DQS0 corresponds to DQ0 – DQ7,
DQS1 corresponds to DQ8–DQ15.
TQ
Output
Temperature sensor output : TQ High when LPDDR Tj exceeds 85℃.
When TQ is ‘High’, self refresh is not supported.
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
Supply Power Supply: Voltage dependant on option.
VSS
Supply Ground.
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Functional Description
The 1Gb Low Power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing
1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the 268,435,456-bit banks is
organized as 16,384 rows by 1,024 columns by 16 bits.
The 1Gb Low Power DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to
transfer four data words per clock cycle at the I/O balls. single read or write access for the 1Gb Low Power
DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
Read and write accesses to the Low Power DDR SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0–A13 select the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting column location for the burst access.
It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the
Low Power DDR SDRAM. It has been omitted to save power.
Prior to normal operation, the Low Power DDR SDRAM must be initialized. The following sections provide
detailed information covering device initialization, register definition, command descriptions and device
operation.
Initialization
Low Power DDR SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation.
If there is an interruption to the device power, the initialization routine should be followed to ensure proper
functionality of the Low Power DDR SDRAM. The clock stop feature is not available until the device has been
properly initialized.
To properly initialize the Low Power DDR SDRAM, this sequence must be followed:
1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the
same power source and brought up simultaneously. If separate power sources are used, VDD must lead
VDDQ.
2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.
3. Once the clock is stable, a 200μs (minimum) delay is required by the Low Power DDR SDRAM prior to
applying an executable command. During this time, NOP or DESELECT commands must be issued on
the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time.
Issue a second AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC
time. As part of the individualization sequence, two AUTO REFRESH commands must be issued.
Typically, both of these commands are issued at this stage as described above. Alternately, the second
AUTO-REFRESH command and NOP or DESELECT sequence can be issued between steps 10 and 11.
7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating
modes. Note that the sequence in which the standard and extended mode registers are programmed is
not critical.
10.Issue NOP or DESELECT commands for at least tMRD time.
11.The Low Power DDR SDRAM has been properly initialized and is ready to receive any valid command.
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Figure 1. Initialize and Load Mode Register[1.2.3.]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
/CLK
CLK
CKE
/CS
/RAS
/CAS
Key
ADDR
Key
RA
BA0
BA
BA1
BA
A10/AP
RA
HiZ
DQs / DQS
HiZ
/WE
DM0-DM1
tRP
Precharge
(All Bank)
tRFC
Auto
Refresh
tRFC
Auto
Refresh
Normal
MRS
Extended
MRS
Row Active
a Bank
Note :
1. The two AUTO REFRESH commands at T3 and T9 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command,
ACT = ACTIVE command, RA = Row Address, BA = Bank Address
3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order; However, all must occur prior
to an Active command.
4. NOP or DESELECT commands are required for at least 200μs.
5. Other valid commands are possible.
6. NOPs or DESELECTs are required during this time.
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Register Definition
Mode Registers
The mode registers are used to define the specific mode of operation of the Low Power DDR SDRAM. There
are two mode registers used to specify the operational characteristics of the device. The standard mode
register, which exists for all Low Power DDR SDRAM devices, and the extended mode register, which exists
on all Low Power DDR SDRAM devices.
Standard Mode Register
The standard mode register definition includes the selection of a burst length, a burst type, a CAS latency and
an operating mode, as shown in Table 1 on page 10. The standard mode register is programmed via the
LOAD MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information
until it is programmed again. Reprogramming the standard mode register will not alter the contents of the
memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),
A4–A6 specify the CAS latency, and A7–A13 specify the operating mode.
Note: Standard refers to meeting JEDEC-standard mode register definitions.
Burst Length
Read and write accesses to the Low Power DDR SDRAM are burst oriented, with the burst length being
programmable, as shown in Table 1 on page 10. The burst length determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2,4,8 or 16
are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this block, meaning that the burst will wrap until a
boundary is reached. The block is uniquely selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, by A3–Ai
when BL = 8, by A4–Ai when BL=16(where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block.
The programmed burst length applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting
column address. See Table 2 on page 11 for more information.
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READ Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first bit of output data. The latency can be set to 2 or 3 clocks, as shown in Table 1 on page 10.
For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at
(2 clocks + tAC). For CL = 2, if the READ command is registered at clock edge n, then the data will be
nominally be available at (1 clock + tAC).
Reserved states should not be used as unknown operation or incompatibility with future versions
may result.
Table 1: Standard Mode Register Definition
M15BA1
M14BA0
0
0
M13A13
M12A12
M11A11
M10M9-A9 M8-A8 M7-A7 M6-A6 M5-A5 M4-A4 M3-A3 M2-A2 M1-A1 M0-A0
A10
Operation Mode
M15 M14 Mode Register Definition
0
0 Standard Mode Register
0
1 Status Read Register
1
0 Extended Mode Register
1
1 Reserved
M13 M12 M11 M10
0
0
0
0
-
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M9
0
-
M8
0
-
M6
0
0
0
0
1
1
1
1
CAS Latency
M5 M4 CAS Latency
0
0
Reserved
0
1
Reserved
1
0
2
1
1
3
0
0
Reserved
0
1
Reserved
1
0
Reserved
1
1
Reserved
M7
Operating Mode
0 Valid Normal Operation
- All other states reserved
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M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M3
0
1
BT
M0
0
1
0
1
0
1
0
1
Burst Length
Burst Length
Reserved
2
4
8
16
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
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Table 2: Burst Definition
Burst
Length
2
4
8
16
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Starting
Column
Address
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A1 A0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
A1 A0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7
9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8
10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9
11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10
12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11
13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14
2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13
3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12
4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11
5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10
6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9
7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8
8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7
9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6
10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5
11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4
12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3
13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2
14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1
15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0
Notes:
1. For BL = 2, A1–Ai select the two-data-element block; A0 selects the first access within the block.
2. For BL = 4, A2–Ai select the four-data-element block; A0–A1 select the first access within the block.
3. For BL = 8, A3–Ai select the eight-data-element block; A0–A2 select the first access within the block.
4. For BL=16, A4–Ai select the sixteen-data-element block; A0–A3 select the first access within the block.
5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
6. Ai = the most significant column address bit for a given configuration.
Table 3: CAS Latency
Speed
-5
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Allowable Operating Clock Frequency (MHz)
CL = 2
CL = 3
f ≤83
f ≤200
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Figure 2: CAS Latency
/CLK
T0
T1
READ
NOP
T1n
T2
T2n
T3n
T3
CLK
Command
1 clock
NOP
NOP
tAC
CAS Latency=2
DQS
Dout
n
DQ
/CLK
T0
T1
READ
NOP
T1n
Dout
Dout
n+1
n+1
T2
T2n
Dout
nn+2
+2
Dout
Dout
n+3
n+3
T3
T3n
CLK
Command
NOP
2 clock
NOP
tAC
CAS Latency=3
DQS
Dout
n
DQ
Dout
n+1
Don’t Care
Notes:
1. BL = 4 in the cases shown.
2. Shown with nominal tAC and nominal tDQSCLK.
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE REGISTER SET command with bits A7–
A13 each set to zero, and bits A0–A6 set to the desired values. All other combinations of values for A7–A13
are reserved for future use and/or test modes. Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions specific to low power operation. These additional functions
include drive strength, temperature compensated self refresh, and partial array self refresh. This device has
default values for the extended mode register (if not programmed, the device will operate with the default
values – PASR = Full Array, DS = Full Drive).
Temperature Compensated Self Refresh
A temperature sensor is implemented for automatic control of the self refresh oscillator on the device.
Programming of the temperature compensated self refresh (TCSR) bits will have no effect on the device.The
self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature.
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Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the mount
of memory that will be refreshed during SELF REFRESH. The refresh options are as follows:
• Full array: banks 0, 1, 2, and 3
• Half array: banks 0 & 1
• Quarter array: bank 0
• One Eighth array: Half of Bank0
• One Sixteenth array: Quarter of Bank0
WRITE and READ commands can still occur during standard operation, but only the selected banks will be
refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
Output Driver Strength
Because the Low Power DDR SDRAM is designed for use in smaller systems that are mostly point to point,
an option to control the drive strength of the output buffers is available. Drive strength should be selected
based on the expected loading of the memory bus. Bits A5 ~ A7 of the extended mode register can be used
to select the driver strength of the DQ outputs. There are five allowable settings for the output drivers.
Table 4: Extended Mode Register Table[1.2.].
EM15- EM14- EM13- EM12- EM11- EM10- EM9- EM8- EM7- EM6- EM5- EM4- EM3- EM2- EM1- EM0BA1 BA0 A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
All must be set to ‘0’
Driver Strength
0
0
PASR
EM15
0
0
1
1
EM14
0
1
0
1
Mode Register Definition
Standard Mode Register
Status Read Register
Extended Mode Register
Reserved
A2
A1
A0
Self Refresh Coverage
A7
A6
A5
Driver Strength
0
0
0
All Banks
0
0
0
100%
0
0
1
Half of Total Bank(BA1=0)
0
0
1
50%
0
1
0
25%
0
1
0
Quarter of Total Bank(BA1=BA0=0)
0
1
1
RFU
0
1
1
12.5%
1
0
0
1
0
0
75%
1
0
1
1
0
1
Reserved
1
1
0
1
1
0
Reserved
1
1
1
Reserved
1
1
1
RFU
One Eighth of Total Bank
(BA1=BA0=Row Address MSB=0 )
One Sixteenth of Total Bank
(BA1=BA0=Row Address2 MSBs=0)
RFU
Note :
1. EM15 and EM14 (BA1 and BA0) must be “1, 0” to select the Extended Mode Register(vs. the base Mode Register).
2. RFU: Reserved for Future Use
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Status Read Registers
The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and
density of the device, as shown in Table 5 (page 14). The SRR is read via the LOAD MODE REGISTER command with
BA0 = 1 and BA1 = 0. The sequence to perform an SRR command is as follows:
•
The device must be properly initialized and in the idle or all banks precharged state.
•
Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins set to 0.
•
Wait tSRR; only NOP or DESELECT commands are supported during the tSRR time.
•
Issue a READ command.
•
Subsequent commands to the device must be issued tSRC after the SRR READ command is issued; only
NOP or DESELECT commands are supported during tSRC.
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first
bit of the burst, with the output being “Don’t Care” on the second bit of the burst.
Table 5: Status Register Table.
S31~S161
S15
S14
Reserved
Density
S13
S12
S11
S10
Type Width
S9
S8
S7
Refresh Rate
S6
S5
S4
Revision ID
S3
S2
S1
S0
Manufacturer ID
S15
S14
S13
Density
S12
Device Type
S11
Device Width
0
0
0
128Mb
0
0
1
256Mb
0
1
LPDDR
Reserve
0
1
16 bits
32 bits
0
1
0
512Mb
S3
S2
S1
S0
Manufacturer ID
0
1
1
Reserved
0
0
Reserved
0
0
0
0
0
0
0
1
Alliance Memory
1
1
0
1
Reserved
0
0
1
0
Reserved
0
0
0
1
1
0
1
0
Reserved
Reserved
0
0
1
1
0
1
1
0
Reserved
Reserved
0
1
1
1
Reserved
1
1
0
0
0
0
0
1
Reserved
Reserved
1
1
0
0
1
1
0
1
Reserved
Reserved
1
1
0
0
Reserved
1
1
0
1
1
0
Reserved
Reserved
1
1
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
S10
S9
S8
Refresh Multiplier2
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
2X
1
0
0
1X
1
0
1
Reserved
1
1
0
0.25X
1
1
1
1
1
Reserved
1
S7
S6
0
0
S5
S4
0
0
1
1
~
1
1
Reserved
Revision ID
The manufacturer’s revision number starts at ‘0000’ and increments by ‘0001’ each time a
change in the specification (AC timings or feature set), IBIS (pull-up or pull-down
characteristics), or process occurs.
Note : 1. Reserved bits should be set to 0 for future compatibility.
2. Refresh multiplier is based on the device on-board temperature sensor.
Requited periodic refresh interval = tREFI X multiplier.
Self refresh is not supported for automotive device at high temperature. (85℃ to 105℃)
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Figure 3: Status Read Register Timing
/CLK
T0
T1
T2
T3
T4
T5
PRE1
NOP
LMR
NOP2
READ
NOP
T6
T7
T8
CLK
COMMAND
NOP
NOP
Valid
Bank 1
ADDRESS
Add 0
CL = 33
DQS
Note 5
SRR
out4
DQ
Don’t Care
Note : 1. All banks must be idle prior to status register read.
2. NOP or DESELECT commands are required between the LMR and READ commands(tSRR), and
between the READ and the next VALID command (tSRC).
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown as an example only.
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.
5. The second bit of the data-out burst is a “Don’t Care.”
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Stopping the External Clock
One method of controlling the power efficiency in applications is to throttle the clock which controls the
Low Power DDR SDRAM. There are two basic ways to control the clock:
1. Change the clock frequency, when the data transfers require a different rate of speed.
2. Stopping the clock altogether.
Both of these are specific to the application and its requirements and both allow power savings due to
possible less transitions on the clock path.
The Low Power DDR SDRAM allows the clock to change frequency during operation, only if all the timing
parameters are met with respect to that change and all refresh requirements are satisfied.
The clock can also be stopped all together, if there are no data accesses in progress, either WRITEs or
READs that would be effected by this change; i.e., if a WRITE or a READ is in progress the entire data burst
must be through the pipeline prior to stopping the clock. CKE must be held HIGH with CLK = LOW and /CLK
= HIGH for the full duration of the clock stop mode. One clock cycle and at least one NOP is required after
the clock is restarted before a valid command can be issued. Figure 4 on page 16 illustrates the clock stop
mode.
It is recommended that the Low Power DDR SDRAM should be in a precharged state if any changes to the
clock frequency are expected. This will eliminate timing violations that may otherwise occur during normal
operational accesses.
Figure 4: Clock Stop Mode
/CLK
Ta1
Ta2
Tb3
Tb4
NOP1
CMD
22
CMD
CMD2
NOP
2
Valid
CMD
Valid
CLK
CKE
COMMAND
Address
DQ, DQS
NOP
NOP
High-Z
All DRAM activities must be complete3
Exit clock stop mode
Enter clock stop mode4
Don’t Care
Notes:
1. Prior to Ta1 the device is in clock stop mode. To exit, at least one NOP is required before any valid command.
2. Any valid command is allowed, device is not in clock suspend mode.
3. Any DRAM operation already in process must be completed before entering clock stop mode. This includes tRCD, tRP, tRFC,
tMRD, tWR, all data-out for READ bursts. This means the DRAM must be either in the idle or precharge state before clock
suspend mode can be entered.
4. To enter and maintain a clock stop mode: CLK = LOW, /CLK = HIGH, CKE = HIGH.
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Commands
Table 6 and Table 7 provide quick references of available commands. This is followed by a written description
of each command. Three additional Truth Tables (Table 13 on page 46, Table 14 on page 47, and Table 15
on page 49) provide CKE commands and current/ next state information.
Table 6: Truth Table – Commands
Notes : 1 and 11 apply to all commands
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank) or
SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER (standard or extended mode registers)
Deep Power Down( Enter DPD Mode )
/CS /RAS /CAS /WE
H
X
X
X
L
H
H
H
L
L
H
H
L
H
L
H
L
H
L
L
L
H
H
L
L
L
H
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
Notes
9
9
3
4
4
8, 10
5
L
L
L
H
X
6, 7
L
L
L
H
L
H
L
L
Op-Code2
Op-Code2
2
11
Notes:
1. CKE is HIGH for all commands shown except SELF REFRESH and Deep Power Down.
2. BA0–BA1 select either the standard mode register or the extended mode register (BA0 = 0, BA1 = 0 select the standard mode
register; BA0 = 0, BA1 = 1 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A13 provide the
op- code to be written to the selected mode register.
3. BA0–BA1 provide bank address and A0–A13 provide row address.
4. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto precharge feature ( nonpersistent ),
and A10 LOW disables the auto precharge feature.
5. A10 LOW : BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts
with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. This command is a BURST TERMINATE if CKE is HIGH.
11. This command is a Deep Power Down if CKE is Low.
12. All states and sequences not shown are reserved and/or illegal.
Table 7: Truth Table – DM Operation
Name (Function)
Write enable
Write inhibit
DM
L
H
DQ
Valid
X
Note: Used to mask write data; provided coincident with corresponding data.
DESELECT
The DESELECT function (/CS HIGH) prevents new commands from being executed by the Low Power DDR
SDRAM. The Low Power DDR SDRAM is effectively deselected. Operations already in progress are not
affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (/CS
= LOW, /RAS = /CAS = /WE = HIGH). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
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LOAD MODE REGISTER
The mode registers are loaded via inputs A0–A13. See mode register descriptions in “Register Definition” on
page 9. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A13 selects the row.
This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0–A9 selects the starting column location. The
value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0–A9 selects the starting column location. The
value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array
subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge
command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to
a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not
violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and
in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1
are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the
process of precharging.
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Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above,
but without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in
conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with
the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE
command. This device supports concurrent auto precharge if the command to the other bank does not
interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest
valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest possible time,
without violating tRAS (MIN), as described for each burst type in “Operations” on page 24. The user must not
issue another command to the same bank until the precharge time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The
most recently registered READ command prior to the BURST TERMINATE command will be truncated, as
shown in “Operations” on page 24. The open page which the READ burst was terminated from remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the Low Power DDR SDRAM and is analogous to /CASBEFORE-/RAS (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued
each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 512Mb Low Power DDR SDRAM requires AUTO REFRESH
cycles at an average interval of 7.8125μs (maximum).To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute refresh interval is provided.
Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH)
during the auto refresh period. The auto refresh period begins when the AUTO REFRESH command is
registered and ends tRFC later.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the Low Power DDR SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the Low Power DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). All command and address input signals except CKE are “Don’t Care” during
SELF REFRESH.
During SELF REFRESH, the device is refreshed as identified in the external mode register (see PASR
setting). For a the full array refresh, all four banks are refreshed simultaneously with the refresh frequency set
by an internal self refresh oscillator. This oscillator changes due to the temperature sensors input. As the
case temperature of the Low Power DDR SDRAM increases, the oscillation frequency will change to
accommodate the change of temperature. This happens because the DRAM capacitors lose charge faster at
higher temperatures. To ensure efficient power dissipation during self refresh, the oscillator will change to
refresh at the slowest rate possible to maintain the devices data.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CLK must be stable
prior to CKE going back HIGH. Once CKE is HIGH, the Low Power DDR SDRAM must have NOP
commands issued for tXSR is required for the completion of any internal refresh in progress.
Self refresh is not supported for automotive device at high temperature.(85℃ to 105℃)
DEEP POWER DOWN
Deep Power Down Mode is an operating mode to achieve extreme power reduction by cutting the power of
the whole memory array of the device. Data will not be retained once the device enters DPD Mode. Full
initialization is required when the device exits from DPD Mode. [Figure 38,39]
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Maximum Ratings
Voltage on VDD/VDDQ Supply
Relative to VSS …….…….………………………...-0.5V to + 2.3V
Voltage on Inputs, NC or I/O Pins
Relative to VSS …….…….…………………….…. –0.5V to +2.3V
Storage Temperature (plastic) ………….………. -55℃ to + 150℃
Power Dissipation ………………………….….………………1W
*Stresses greater than those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Operating Range
Device
Range
Ambient Temperature
VDD
VDDQ
AS4C64M16MD1A-5BIN
Industrial
-40℃ to +85℃
1.7V ~ 1.95V
1.7V ~ VDD
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS [1,2]
Parameter / Condition
Supply Voltage
I/O Supply Voltage
Clock Input Voltage : CK, CK#
[7]
Clock Input Differential Voltage : CK, CK#
[7,8]
Input High Voltage : Logic 1 Address, Command and Data Input
Input Low Voltage : Logic 0 Address, Command and Data Inputs
[3]
Symbol
Min
Max
Units
VDD
1.7
1.95
V
VDDQ
1.7
VDD
V
VIN
-0.3
VDDQ +0.3
V
VID
0.4 * VDDQ VDDQ +0.6
V
VIH
0.7 * VDDQ VDDQ +0.3
V
VIL
-0.3
Data Output High Voltage : Logic 1 : All Inputs(-0.1mA)
VOH
0.9 * VDDQ
Data Output Low Voltage : Logic 0 : All Inputs(0.1mA)
Input Leakage Current :
Any Input 0V=VIN=VDD (All other pins not under test=0V)
VOL
II
Output Leakage Current : DQs are disabled ; 0V= VOUT=VDDQ
lOZ
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0.3*VDDQ
V
V
0.1 * VDDQ
V
-5
5
㎂
-5
5
㎂
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Table 8. AC Operating Conditions[1,2,3,4,5,6]
Parameter / Condition
Value
Units
0.8 * VDDQ / 0.2 * VDDQ
V
0.6 * VDDQ ~ VDDQ +0.6
V
0.4 * VDDQ ~ 0.6 * VDDQ
V
0.5 * VDDQ
V
1.0
V/ns
0.5 * VDDQ
V
AC Output Load Circuit on page 20
V
AC Address, Command and Data Input levels (Vih / Vil)
Clock Input Differential Level(VID) : CK, CK#
[7,8]
Clock Differential Crossing Level(VIX) : CK, CK#
[7,9]
Input Timing Measurement Reference Level
Input Signal Minimum Slew Rate
Output Timing Measurement Reference Level
Output Load Condition
Note :
1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range
(-40°C ≤ TA ≤ +85°C for IT parts) is ensured.
2.
An initial pause of 200µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation
is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
3.
3. All states and sequences not shown are illegal or reserved.
4.
In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
5.
tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data
element will meet tOH before going High-Z.
6.
AC timing and IDD tests have VIL and VIH, with timing referenced to VIH//2 = crossover point. If the input transition time is longer than
tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
7.
CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
8.
VID is the magnitude of the difference between the input level on CK and the input level on CK#.
9.
The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
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Table 9: IDD Specifications and Conditions
Parameter/Condition
Max
Symbol
Operating one bank active precharge current: tRC = tRC(MIN); tCLK = tCLK(MIN);
CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every two CLK
cycles; Data bus inputs are stable.
-5
Units Notes
IDD0
95
mA
1, 6
Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH;
tCLK = tCLK(MIN); Address and control inputs are switching every two CLK cycles; Data bus inputs
are stable.
IDD2P
600
μA
2, 4
Precharge power-down standby current with CLK stopped: All banks idle; CKE is LOW, CS is HIGH;
CLK = LOW, /CLK = HIGH; Address and control inputs are switching every two CLK cycles; Data
bus inputs are stable.
IDD2PS
600
μA
2, 4
Precharge non power-down standby current: All banks idle; CKE = HIGH; CS = HIGH; tCLK =tCLK(MIN);
IDD2N
Address and control inputs are switching every two CLK cycles; Data bus inputs are stable.
18
mA
5
Precharge non power-down standby current: CLK stopped; All banks idle;
CKE = HIGH; CS = HIGH; CLK = LOW; /CLK = HIGH Address and control inputs are switching
every two CLK cycles; Data bus inputs are stable.
IDD2NS
14
mA
5
IDD3P
3.6
mA
2, 4
IDD3PS
3.6
mA
2, 4
IDD3N
20
mA
1
Active non-power-down standby: CLK stopped; One bank active;
CKE = HIGH; CS = HIGH; CLK = LOW; /CLK = HIGH; Address and control inputs are switching
every two CLK cycles; Data bus inputs are stable.
IDD3NS
14
mA
1
Operating burst read : One bank active; BL = 4; tCLK = tCLK(MIN);
Continuous READ bursts; Address inputs are switching; 50 percent data changing each burst.
IDD4R
135
mA
1, 6
Operating burst write: One bank active; BL = 4; tCLK = tCLK(MIN);
Continuous WRITE bursts; Address inputs are switching; 50 percent data changing each burst.
IDD4W
135
mA
1, 6
tRC = tRFC(138ns)
IDD5
100
mA
7
tRC = 7.8125μs
IDD5a
15
mA
3, 7
Full Array, 85°C
IDD6a
1300
μA
8, 9
Full Array, 45°C
IDD6a
450
μA
8, 9
Half Array, 85°C
IDD6b
1000
μA
8, 9
¼ Array, 85°C
IDD6c
900
μA
8, 9
IDD7
15
μA
10
Active power-down standby current: One bank active; CKE = LOW; CS = HIGH;
tCLK = tCLK(MIN); Address and control inputs are switching every two CLK cycles; Data bus inputs
are stable.
Active power-down standby current: CLK stopped; One bank active; CKE = LOW;
CS = HIGH; CLK = LOW; /CLK = HIGH; Address and control inputs are switching every two CLK
cycles; Data bus inputs are stable.
Active non power-down standby: One bank active; CKE = HIGH; CS = HIGH;
tCLK = tCLK(MIN); Address and control inputs are switching every two cycles; Data bus inputs are
stable.
Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are
switching; Data bus inputs are stable.
Self refresh: CKE = LOW; tCLK = tCLK(MIN);
Address and control inputs are stable; Data bus inputs are Stable.
Deep Power Down Current ; Address, control and data bus inputs are STABLE
Notes :
1. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCLK that meets the minimum absolute value for the respective
parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCLK that meets the maximum absolute value for tRAS.
2. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125μs.
3. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN])
else CKE is LOW (i.e., during standby).
4. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps (pending) must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds
4V/ns, functionality is uncertain.
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5. IDD2N specifies DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
6. Switching is defined as :
- address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
7. CKE must be active (HIGH) during the entire time a REFRESH command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising CLK edge, until tRFC later.
8. With the inclusion of the temperature sensor on the low-power DDR device, these numbers are shown as examples only, and will
change due to the junction temperature that the device is sensing. They are expected to be maximum values at this time.
9. Enables on-chip refresh and address counters.
10. Device must be in the all banks idle state prior to entering Deep Power Down.
Table 10: Capacitance
Parameter
Input capacitance
(A0-A13, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE)
Input capacitance (CLK, /CLK)
Data & DQS input / output capacitance
Input capacitance(DM)
Symbol
Min
Max
Units
CIN1
1.5
3.0
pF
CIN2
COUT
CIN3
1.5
3.0
3.0
3.0
5.0
5.0
pF
pF
pF
AC Output Load Circuit
VDDQ/2
50W
Z0=50W
Output
20pF
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Table 11: Electrical Characteristics and Recommended AC Operating Conditions
AC Characteristics
Symbol
Parameter
-5
Min
Max
Units
CL=3
tAC(3)
2.0
5.0
CL=2
tAC(2)
2.0
6.5
CLK high-level width
tCH
0.45
0.55
tCLK
CLK low-level width
tCL
0.45
0.55
tCLK
Access window of DQ from CLK & /CLK
Notes
ns
CL=3
tCLK(3)
5
-
ns
CL=2
tCLK(2)
12
-
ns
tDAL
tDH
0.48
-
tCLK
ns
16
9, 13, 15
DQ and DM input setup time relative to DQS
tDS
0.48
-
ns
17
DQ and DM input pulse width (for each input)
tDIPW
1.6
-
ns
tDQSCLK
2.0
5.0
ns
DQS input high-pulse width
tDQSH
0.4
0.6
tCLK
DQS input low-pulse width
tDQSL
0.4
0.6
tCLK
Data strobe edge to Dout edge
tDQSQ
-
0.4
ns
WRITE command to first DQS latching transition
tDQSS
0.75
1.25
tCLK
DQS falling edge to CLK rising – setup time
tDSS
0.2
-
tCLK
DQS falling edge from CLK rising – hold time
tDSH
0.2
-
tCLK
Half-CLK period
tHP
tCH, tCL
-
ns
12
Data-out High-Z window from CLK & /CLK
tHZ
-
5.0
ns
3, 11
Data-out Low-Z window from CLK & /CLK
tLZ
1.0
-
ns
3, 11
Transition Time
tT
0.5
1.2
ns
Address and control input hold time
tIH
0.9
-
ns
2, 15
Address and control input setup time
tIS
0.9
-
ns
2, 15
Address and control input pulse width
tIPW
2.2
-
ns
17
LOAD MODE REGISTER command cycle time
tMRD
2
-
tCLK
tQH
tHP –tQHS
-
ns
Data hold skew factor
tQHS
-
0.5
ns
ACTIVE-to-PRECHARGE command
tRAS
42
70,000
ns
ACTIVE-to-ACTIVE command period
tRC
55
-
ns
AUTO REFRESH command period
tRFC
80
-
ns
ACTIVE-to-READ or WRITE delay
tRCD
15
-
ns
System Clock cycle time
Auto precharge write recovery + precharge time
DQ and DM input hold time relative to DQS
Access window of DQS from CLK & /CLK
DQ–DQS hold, DQS to first DQ to go non-valid, per access
PRECHARGE command period
1
8, 9
8, 9
10
14
tRP
15
-
ns
CL=3
tRPRE(3)
0.9
1.1
tCLK
11
CL=2
tRPRE(2)
0.5
1.1
tCLK
11
DQS read postamble
tRPST
0.4
0.6
tCLK
Read of SRR to next valid command
tSRC
CL+1
-
tCLK
SRR to Read
tSRR
2
-
tCLK
tTQ
2
-
ms
tRRD
10
-
ns
DQS read preamble
Internal temperature sensor valid temperature output enable
ACTIVE bank a to ACTIVE bank b Delay
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions (continued)
AC Characteristics
Parameter
Symbol
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Average periodic refresh interval
Exit SELF REFRESH to first valid command
Exit power-down mode to first valid command
Minimum tCKE HIGH/LOW time
-5
tWPRE
tWPRES
tWPST
tWR
tWTR
Min
0.25
0
0.4
15
2
Max
0.6
-
tREFI
tXSR
tPDX
tCKE
120
25
1
7.8
-
Units
tCLK
ns
tCLK
ns
tCLK
μs
ns
ns
tCLK
Notes
5, 6
4
7
18
19
Notes
1. CAS latency definition: for CL = 2, the first data element is valid at (tCLK + tAC) after the CLK at which the READ command was
registered; for CL = 3, the first data element is valid at (2 × tCLK + tAC) after the first CLK at which the READ command was
registered.
2. Fast command/address input slew rate ≥ 1V/ns. Slow command/address input slew rate ≥ 0.5V/ns. If the slew rate is less than
0.5V/ns, timing must be derated: tIS has an additional 50ps (pending) per each 100mV/ns reduction in slew rate from the 0.5V/ns.
tIH has 0ps added (pending); that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are not referenced to a
specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
5. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus
turnaround.
6. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
7. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125μs.
8. The valid data window is derived by achieving other specifications: tHP (tCLK/2), tDQSQ, and tQH (tHP - tQHS). The data valid window
derates directly proportional with the CLK duty cycle and a practical data valid window can be derived. The CLK is allowed a
maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio.
9. Referenced to each output group: DQS0 with DQ0–DQ7; and DQ1 with DQ8–DQ1
10. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) can be satisfied prior to the internal
PRECHARGE command being issued.
11. tHZ (MAX) will prevail over tDQSCLK (MAX) + tRPST (MAX) condition.
12. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CLK and /CLK inputs, collectively.
13. Random addressing changing 50 percent of data changing at every transfer.
14. CKE must be active (HIGH) during the entire time a REFRESH command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising CLK edge, until tRFC later.
15. The transition time for input signals (/CAS, CKE, /CS, DM, DQ, DQS, /RAS, /WE, and addresses) are measured between VIL(DC) to
VIH(AC) for rising input signals and VIH(DC) to VIL(AC) for falling input signals.
16. tDAL = (tWR/tCLK) + (tRP/tCLK) + 1tCLK : for each term, if not already an integer, round to the next higher integer.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. CLK must be toggled a minimum of two times during this period.
19. CLK must be toggled a minimum of one time during this period.
20. This device can support 45/55 of duty rate for tDQSCLK in case of 50/50 of CLK input.
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Operations
Bank/row Activation
Before any READ or WRITE commands can be issued to a bank within the Low Power DDR SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the
bank and the row to be activated, as shown in Figure 5.
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge after the ACTIVE command on which a
READ or WRITE command can be entered. For example, a tRCD specification of 18ns with a 133 MHz clock
(7.5ns period) results in 2.4 clocks rounded to 3.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE
commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE
commands to different banks is defined by tRRD.
Figure 5: Activating a Specific Row in a Specific Bank
/CLK
CLK
CKE
High
/CS
/RAS
/CAS
/WE
A0-A13
RA
BA0, BA1
BA
RA = Row Address
BA = Bank Address
Don’t Care
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READ
READ bursts are initiated with a READ command, as shown in Figure 6 on page 26.
The starting column and bank addresses are provided with the READ command and auto precharge is either
enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged
at the completion of the burst. For the READ commands used in the following illustrations, auto
precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will be available following
the CAS latency after the READ command. Each subsequent data out element will be valid nominally at the
next positive or negative clock edge (i.e., at the next crossing of CLK and /CLK). Figure 7 on page 27 shows
general timing for each possible CAS latency setting. DQS is driven by the Low Power DDR SDRAM along
with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A
detailed explanation of tDQSCLK (DQS transition skew to CLK) and tAC (data-out transition skew to CLK) is
depicted in Figure 28 on page 52.
Data from any READ burst may be concatenated with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data can be maintained. The first data element from the new
burst follows either the last element of a completed burst or the last desired data element of a longer burst
which is being truncated. The new READ command should be issued x cycles after the first READ command,
where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 8 on page 28.
A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive
read data is shown for illustration in Figure 9 on page 29. Full speed random read accesses within a page (or
pages) can be performed as shown in Figure 10 on page 30.
Figure 6: READ Command
/CLK
CLK
CKE
High
/CS
/RAS
/CAS
/WE
A0- A9
A10
BA0, BA1
CA
EN AP
DIS AP
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
Don’t Care
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Figure 7: READ Operation
/CLK
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
CLK
COMMAND
ADDRESS
NOP
NOP
Bank a
Col m
CL = 2
tDQSCLK
DQS
tDQSCLK
tRPST
tRPRE
tAC
DQ
tLZ
tDQSQ max
tHZ
Dout Dout Dout
m
m+1 m +2
Dout
m+3
tQH
tQH
Don’t Care
Notes :
1. Dout m = data-out from column m.
2. BL = 4.
3. Shown with nominal tAC, tDQSCLK, and tDQSQ.
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Figure 8: Consecutive Read Bursts
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
READ
NOP
READ
Bank
Bank
Col m
Col n
NOP
NOP
NOP
Dout Dout
n
n+1
Dout
n+2
CL = 2
DQS
Dout
m
DQ
/CLK
T0
T1
T1n
T2
Dout Dout
m+1 m +2
T2n
T3
Dout
m+3
T3n
T4
T4n
Dout
n+3
T5
CLK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank
Bank
Col n
Col m
CL = 3
DQS
DQ
Dout Dout Dout
m
m+1 m+2
Dout
m+3
Dout Dout
n
n+1
Don’t Care
Notes :
1. Dout m (or n) = data-out from column m (or column n).
2. BL = 4 in the cases shown.
3. Shown with nominal tAC, tDQSCLK, and tDQSQ.
4. This example represents consecutive READ commands issued to the device.
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Figure 9: Read-to-Read Operation
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CLK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank
Bank
Col n
Col m
CL = 2
CL = 2
DQS
Dout
m
DQ
/CLK
T0
T1
READ
NOP
T1n
T2
Dout Dout
m+1 m +2
T2n
T3
Dout
m+3
T3n
Dout
n
`
T4
T4n
T5
Dout
n+1
T5n
Dout
n+2
T6
CLK
COMMAND
ADDRESS
NOP
Bank
READ
NOP
NOP
NOP
Bank
Col m
Col n
CL = 3
CL = 3
DQS
DQ
Dout Dout Dout Dout
m
m+1 m+2 m+3
Dout
n
Don’t Care
Notes :
1. Dout m (or n) = data-out from column m (or column n).
2. BL = 4 in the cases shown
3. Shown with nominal tAC, tDQSCLK, and tDQSQ.
4. This example represents nonconsecutive READ commands issued to the device.
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Figure 10: Random READ Accesses
/CLK
T0
T1
READ
READ
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CLK
COMMAND
ADDRESS
READ
READ
Bank
Bank
Bank
Bank
Col m
Col n
CL = 2
Col o
Col p
NOP
NOP
DQS
DQ
/CLK
T0
T1
READ
READ
T1n
Dout
m
Dout
m+1
Dout
n
Dout
n+1
T2
T2n
T3
T3n
Dout
o
Dout
o+1
Dout
p
T4
T4n
T5
Dout
p+1
T5n
CLK
COMMAND
ADDRESS
READ
READ
Bank
Bank
Bank
Bank
Col m
Col n
CL = 3
Col o
Col p
NOP
NOP
DQS
DQ
Dout
m
Dout Dout
m+1
n
Dout
n+1
Dout
o
Dout
o+1
Don’t Care
Notes :
1. Dout m (or n, o, p) = data-out from column m (or column n, column o, column p).
2. BL = 4 in the cases shown.
3. READs are to an active row in any bank.
4. Shown with nominal tAC, tDQSCLK, and tDQSQ.
Truncated READs
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11
on page 31. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST
TERMINATE command should be issued x cycles after the READ command, where x equals the number of
desired data element pairs (pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be
issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 12
on page 32. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS
[MIN] and tDQSS [MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided
that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the
READ command, where x equals the number of desired data element pairs (pairs are required by the nprefetch architecture). This is shown in Figure 13 on page 33. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until tRP is met.
Note: Part of the row precharge time is hidden during the access of the last data elements
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Figure 11: READ Burst Terminated
/CLK
T0
T1
READ
BST4
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a
Col n
CL = 2
DQS
Dout
n
DQ
/CLK
T0
T1
T1n
T2
Dout
n+1
T2n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
READ
BST4
NOP
NOP
NOP
NOP
Bank a.
Col n
CL = 3
DQS
DQ
Dout
n
Dout
n+1
Don’t Care
Notes :
1. Dout n = data-out from column n.
2. Only valid for BL = 4 and BL = 8.
3. Shown with nominal tAC, tDQSCLK, and tDQSQ.
4. BST = BURST TERMINATE command; page remains open.
5. CKE = HIGH.
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Figure 12: READ-to-WRITE Operation
/CLK
T0
T1
READ
BST5
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
NOP
WRITE
Bank
Bank
Col m
Col n
NOP
NOP
tDQSS (NOM)
CL = 2
DQS
DQ
Dout
m
Dout
m+1
T2
T2n
Din
n
Din
n+1
Din
n+2
Din
n+3
DM
/CLK
T0
T1
T1n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
READ
BST5
NOP
NOP
WRITE
NOP
Bank
Bank
Col m
Col n
tDQSS (NOM)
CL = 3
DQS
DQ
Dout
m
Dout
m+1
Din
n
Din
n+1
DM
Don’t Care
Notes :
1. Dout m = data-out from column m.
2. Din n = data-in from column n.
3. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown can be a NOP).
4. Shown with nominal tAC, tDQSCLK, and tDQSQ.
5. BST = BURST TERMINATE command; page remains open.
6. CKE = HIGH.
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Figure 13: READ-to-PRECHARGE Operation
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
READ
NOP
PRE
Bank a.
NOP
NOP
ACT
Bank a
Col m
Bank a
(a or all)
Row
CL = 2
tRP
DQS
Dout
m
DQ
/CLK
T0
T1
T1n
Dout Dout
m+1 m+2
T2
T2n
T3
Dout
m+3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
Bank a
Bank a
Bank a
Col m
(a or all)
Row
`
`
tRP
CL = 3
DQS
DQ
Dout
m
Dout Dout
m+1 m+2
Dout
m+3
Don’t Care
Notes :
1. Dout m = data-out from column m.
2. BL = 4 or an interrupted burst of 8.
3. Shown with nominal tAC, tDQSCLK, and tDQSQ.
4. READ-to-PRECHARGE equals 2 clocks, which allows 2 data pairs of data-out.
5. A READ command with auto precharge enabled, provided tRAS (MIN) is met, would cause a precharge to be performed at x
number of clock cycles after the READ command, where x = BL / 2.
6. PRE = PRECHARGE command; ACT = ACTIVE command.
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WRITE
WRITE bursts are initiated with a WRITE command, as shown in Figure 14 on page 35. The starting column
and bank addresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the
completion of the burst. For the WRITE commands used in the following illustrations, auto precharge is
disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS
following the WRITE command, and subsequent data elements will be registered on successive edges of
DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write
preamble; the LOW state on DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the WRITE
diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX])
might not be intuitive, they have also been included. Figure 15 on page 36 shows the nominal case and the
extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been
initiated, the DQs will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In
either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on
any positive edge of clock following the previous WRITE command. The first data element from the new
burst is applied after either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles after the first WRITE
command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture).
Figure 16 on page 37 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in
Figure 17 on page 37. Full-speed random write accesses within a page or pages can be performed, as
shown in Figure 18 on page 38. Data for any WRITE burst may be followed by a subsequent READ
command. To follow a WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure
19 on page 39.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 20 on
page 40. Note that only the data-in pairs that are registered prior to the tWTR period are written to the
internal array, and any subsequent data-in should be masked with DM, as shown in Figure 21 on page 41.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst, tWR should be met, as shown in Figure 22 on page 42.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure
23 on page 43 and Figure 24 on page 44. Note that only the data-in pairs that are registered prior to the tWR
period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in
Figure 23 on page 43 and Figure 24 on page 44. After the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
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Figure 14: WRITE Command
CLK
/CLK
CKE
High
/CS
/RAS
/CAS
/WE
A0- A9
CA
EN AP
A10
BA0, BA1
DIS AP
BA
Don’t Care
Note :
1. DIS AP = Disable Auto Precharge
2. EN AP = Enable Auto Precharge
3. BA = Bank Address
4. CA = Column Address
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Figure 15: WRITE Operation
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank a
Col m
/CLK
T1n
T2
T2n
T3
T3n
CLK
tDQSS
tDQSS (NOM)
NOP
NOP
tDSH
tDQSH
tWPST
DQS
tWPRES tWPRE
tDS tDH
Din
m
DQ
Din
m+1
Din
m+2
Din
m+3
DQM
tDSH
tDQSS
tDQSS (MIN)
tDSH
tDQSH
tWPST
DQS
tWPRES tWPRE
tDS tDH
Din
m
DQ
Din
m+1
Din
m+2
Din
m+3
DQM
tDQSS
tDQSS (MAX)
tDSS
tDQSH tDSS
tWPST
DQS
tWPRES
DQ
tWPRE tDS tDH
Din
m
tDQSL
Din
m+1
Din
m+2
Din
m+3
DQM
Don’t Care
Notes :
1. Din m = data-in for column m.
2. An uninterrupted burst of 4 is shown.
3. A10 is LOW with the WRITE command (auto precharge is disabled).
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Figure 16: Consecutive WRITE-to-WRITE
/CLK
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CLK
COMMAND
ADDRESS
NOP
WRITE
Bank
Bank
Col m
Col n
NOP
NOP
tDQSS
DQS
Din
m
DQ
Din
m+1
Din
m+2
Din Din
m+3
n
Din
n+1
Din
n+2
Din
n+3
T4
T4n
DM
Notes :
1. Din m (n) = data-in for column m (n).
2. An uninterrupted burst of 4 is shown.
3. Each WRITE command may be to any bank.
Figure 17: WRITE-to-WRITE Operation
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T5
CLK
COMMAND
ADDRESS
WRITE
NOP
WRITE
NOP
Bank
Bank
Col m
Col n
NOP
NOP
tDQSS
DQS
DQ
Din
m
Din
m+1
Din
m+2
Din
m+3
Din
n
Din
n+1
Din
n+2
Din
n+3
DM
Don’t Care
Notes :
1. Din m (n) = data-in for column m (n).
2. An uninterrupted burst of 4 is shown.
3. Each WRITE command may be to any bank.
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Figure 18: Random WRITE Cycles
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CLK
COMMAND
ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
Bank
Bank
Bank
Bank
Bank
Col m
Col n
Col o
Col p
Col q
NOP
tDQSS
DQS
DQ
Din
m
Din
m’
Din
n
Din
n’
Din
o
Din
o’
Din
p
Din
p’
Din
q
Din
q’
DM
Notes :
1. Din m (or n, o, p, q) = data-in for column m (or n, o, p, q)
2. m' (or n, o, p, q) = the next data-in following Din m (or n, o, p, q), according to the programmed burst order.
3. Programmed BL = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
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Figure 19: WRITE-to-READ – Uninterrupting
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CLK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
NOP
tWTR
ADDRESS
tDQSS (NOM)
Bank a .
Bank a.
Col m
Col n
tDQSS
CL = 2
DQS
Din
m
DQ
Din
m+1
Din
m+2
Dout
n
Din
m+3
Dout
n+1
DM
tDQSS (MIN)
CL = 2
tDQSS
DQS
DQ
Din
m
Din
m+1
Din
m+2
Din
m+3
Dout Dout
n+1
n
DM
tDQSS (MAX)
CL = 2
tDQSS
DQS
DQ
Din
m
Din
m+1
Din
m+2
Din
m+3
Dout
n
Dout
n+1
DM
Don’t Care
Notes :
1. Din m = data-in for column m; Dout n = data-out for column n.
2. An uninterrupted burst of 4 is shown.
3. tWTR is referenced from the first positive CLK edge after the last data-in pair.
4. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices,
in which case tWTR is not required and the READ command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
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Figure 20: WRITE-to-READ – Interrupting
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CLK
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
NOP
tWTR
ADDRESS
tDQSS (NOM)
Bank a.
Bank a.
Col m
Col n
CL = 3
tDQSS
DQS
Din
m
DQ
Din
m+1
Dout Dout
n
n+1
DM
tDQSS (MIN)
CL = 3
tDQSS
DQS
DQ
Din
m
Dout
n
Din
m+1
`
Dout
n+1
DM
tDQSS (MAX)
CL = 3
tDQSS
DQS
DQ
Din
m
Din
m+1
Dout
n
Dout
n+1
DM
Don’t Care
Notes :
1. Din m = data-in for column m; Dout n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. tWTR is referenced from the first positive CLK edge after the last data-in pair.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T2 and T2n (nominal case) to register DM.
6. If the burst of 8 was used and RD is required at T5, DM and DQS would be required at T4 and T4n because the READ command
would not mask these two data elements.
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Figure 21: WRITE-to-READ – Odd Number of Data, Interrupting
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CLK
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
NOP
tWTR
ADDRESS
tDQSS (NOM)
Bank a
Bank a
Col m
Col n
CL = 3
tDQSS
DQS
Din
m
DQ
Dout Dout
n
n+1
DM
tDQSS (MIN)
tDQSS
CL = 3
DQS
DQ
Din
m
Dout
n
Dout
n+1
Dout
n
Dout
n+1
DM
tDQSS (MAX)
CL = 3
tDQSS
DQS
DQ
Din
m
DM
Don’t Care
Notes :
1. Din m = data-in for column m; Dout n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written, three are masked.
3. tWTR is referenced from the first positive CLK edge after the last data-in pair.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T2 and T2n (nominal case) to register DM.
6. If the burst of 8 was used and RD is required at T5, DM and DQS would be required at T4 and T4n because the READ command
would not mask these two data elements.
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Figure 22: WRITE-to-PRECHARGE – Uninterrupting
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CLK
COMMAND
WRITE
NOP
NOP
NOP
NOP
PRE6
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a
Bank
Col m
(a or All)
tDQSS
DQS
Din
m
DQ
Din
m+1
Din Din
m+2 m+3
DM
tDQSS (MIN)
tDQSS
DQS
Din
m
DQ
Din
m+1
Din Din
m+2 m+3
Din
m
Din
m+1
DM
tDQSS (MAX)
tDQSS
DQS
DQ
Din Din
m+2 m+3
DM
Don’t Care
Notes :
1. Din m = data-in for column m.
2. An uninterrupted burst of 4 is shown.
3. tWR is referenced from the first positive CLK edge after the last data-in pair.
4. The PRECHARGE and WRITE commands are to same device. However, the PRECHARGE and WRITE commands may be to
different devices, in which case tW R is not required and the READ command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. PRE = PRECHARGE command.
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Figure 23: WRITE-to-PRECHARGE – Interrupting
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CLK
COMMAND
WRITE
NOP
NOP
NOP
PRE6
NOP
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a.
Bank
Col m
(a or All)
tDQSS
DQS
Din
m
DQ
Din
m+1
DM
tDQSS (MIN)
tDQSS
DQS
Din
m
DQ
Din
m+1
DM
tDQSS (MAX)
tDQSS
DQS
DQ
Din
m
Din
m+1
DM
Don’t Care
Notes :
1. Din m = data-in for column m.
2. An interrupted burst of 8 is shown.
3. tWR is referenced from the first positive CLK edge after the last data-in pair.
4. The PRECHARGE and WRITE commands are to same device. However, the PRECHARGE and WRITE commands may be to
different devices, in which case tWR is not required and the READ command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. PRE = PRECHARGE command.
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Figure 24: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
/CLK
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CLK
COMMAND
WRITE
NOP
NOP
NOP
NOP
PRE6
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a.
Bank
Col m
(a or All)
tDQSS
DQS
Din
m
DQ
DM
tDQSS (MIN)
tDQSS
DQS
Din
m
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DQ
Din
m
DM
Don’t Care
Notes :
1. Din m = data-in for column m.
2. An interrupted burst of 8 is shown.
3. tWR is referenced from the first positive CLK edge after the last data-in pair.
4. The PRECHARGE and WRITE commands are to same device. However, the PRECHARGE and WRITE commands may be to
different devices, in which case tW R is not required and the READ command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. PRE = PRECHARGE command.
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PRECHARGE
The PRECHARGE command (Figure 25) is used to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP)
after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank.
When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being
issued to that bank.
Figure 25: PRECHARGE Command
/CLK
CLK
CKE
High
/CS
/RAS
/CAS
/WE
A0–A9, A11–A13
All
A10
Single
BA0, BA1
BA
Don’t Care
Note :
1. BA = Bank Address.
2. All = All banks to be Precharged, BA1, BA0 are “Don't Care.”
3. Single = Only bank selected by BA1 and BA0 will be precharged.
Power-Down (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress: from
the issuing of a READ or WRITE command until completion of the burst; thus a clock suspend is not
supported. For READs, a burst completion is defined when the read postamble is satisfied; For WRITEs, a
burst completion is defined when the write postamble is satisfied.
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Power-Down (Active or Precharge)
Power-down (Figure 27) is entered when CKE is registered LOW. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and
output buffers, including CLK and /CLK. Exiting power-down requires the device to be at the same voltage as
when it entered power-down and a stable clock.
Note :
The power-down duration is limited by the refresh requirements of the device. While in power-down, CKE
LOW must be maintained at the inputs of the Low Power DDR SDRAM, while all other input signals are
“Don’t Care.” The power-down state is synchronously exited when CKE is registered HIGH (in conjunction
with a NOP or DESELECT command). NOPs or DESELECT commands must be maintained on the
command bus until tPDX is satisfied.
Figure 26: Power-Down Command (Active or Precharge)
/CLK
CLK
CKE
/CS
/RAS, /CAS, /WE
OR
/CS
/RAS, /CAS, /WE
A0- A13
BA0-BA1
Don’t Care
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Figure 27: Power-Down (Active or Precharge)
T0
/CLK
T1
T2
T3
T4
T5
CLK
Referencing tCKE tPDX
tCKE
tIS
CKE
tPDX1
COMMAND
Valid
NOP
NOP
NOP
Valid
No READ / WRITE
Access in progress
Enter
(active or precharge) power-down mode
Exit
(active or precharge) power-down mode
Notes: 1. Clock must toggle a minimum of once during this time.
Truth Tables
Table 13: Truth Table – CKE
Notes: 1–5
CKEn-1 CKEn
L
L
L
L
L
L
L
H
L
H
L
H
H
L
H
L
H
L
H
H
H
H
Current State
(Active) Power-Down
(Precharge) Power-Down
Self refresh
(Active) Power-Down
(Precharge) Power-Down
Self refresh
Bank(s) active
All banks idle
All banks idle
COMMANDn
X
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
See Table 15 on page 49
See Table 15 on page 49
ACTIONn
Notes
Maintain (active) power-down
Maintain (precharge) power-down
Maintain self refresh
Exit (active) power-down
6, 7
Exit (precharge) power-down
6, 7
Exit self refresh
8, 9
(Active) power-down entry
(Precharge) power-down entry
Self refresh entry
Notes :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. tCKE pertains.
6. DESELECT or NOP commands should be issued on any clock edges occurring during the tPDX period.
7. The clock must toggle at least once during the tPDX period.
8. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period.
9. The clock must toggle at least once during the tXSR period.
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Table 14 Truth Table – Current State Bank n - Command to Bank n
Notes : 1–6; notes appear below and on next page
Current State
Any
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
/CS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
/RAS
X
H
L
L
L
H
H
L
H
H
L
H
H
H
L
/CAS
X
H
H
L
L
L
L
H
L
L
H
H
L
L
H
/WE
X
H
H
H
L
H
L
L
H
L
L
L
H
L
L
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
Notes
7
7
10
10
8
10
10, 12
8
9
10, 11
10
8, 11
Notes :
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if the previous state was self refresh)
and after tPDX has been met (if the previous state was power-down).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to
the other bank are determined by its current state and Table 14, and according to Table15.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in
the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in
the row active state.
Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on
each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the DDR
SDRAM will be in the all banks idle state.
Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met.
Once tMRD is met, the Low Power DDR SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks
will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
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10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end
the READ burst prior to asserting a WRITE command.
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Table 15: Truth Table – Current State Bank n - Command to Bank m
Notes : 1–6; notes appear below and on next page
Current State
Any
Idle
Row activating,
active, or
precharging
Read
(auto precharge
Disabled)
Write
(auto precharge
Disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
/CS
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
/RAS /CAS
X
X
H
H
X
X
L
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L
L
H
/WE
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7
7, 9
7, 8
7
7, 3a
7. 9, 3a
7, 3a
7, 3a
Notes :
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if the previous state was self refresh)
or after tPDX has been met (if the previous state was power-down).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m, assuming that bank m is in such a state that given command is allowable). Exceptions are
covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Read with auto precharge enabled: See following text – 3a
Write with auto precharge enabled: See following text – 3a
3a. The read with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts: the access
period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed
with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data
in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge
was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins.
This device supports concurrent auto precharge such that when a read with auto precharge enabled or a write with auto precharge
is enabled any command to other banks is allowed, long as that command does not interrupt the read or write data transfer already
in process. either case, all other related limitations apply (e.g., contention between read data and write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is
summarized below.
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AS4C64M16MD1A-5BIN
From Command
WRITE w/AP
READ w/AP
To Command
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
Minimum Delay
(with Concurrent Auto
Precharge)
[1 + (BL/2)] tCLK + tWTR
(BL/2) tCLK
1 tCLK
1 tCLK
(BL/2) × tCLK
[CLRU + (BL/2)] tCLK
1 tCLK
1 tCLK
CLRU = CAS Latency (CL) rounded up to the next integer
BL = Burst Length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end
the READ burst prior to asserting a WRITE command.
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AS4C64M16MD1A-5BIN
Figure 28: Data Output Timing – tAC and tDQSCLK
T0
T1
T2
READ
NOP
NOP
/CLK
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CLK
COMMAND
NOP
NOP
NOP
NOP
CL = 3
tDQSCLK
(MAX)
tDQSCLK
(MAX)
DQS1
tRPST
tRPRE
tAC(MAX)
T2
All DQ values, collectively2
T2n
T3
T3n
T4
T4n
T5
T5n
tHZ(MAX)
Notes :
1. DQ transitioning after DQS transition define tDQSQ window.
2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
3. tAC is the DQ output window relative to CLK, and is the “long term” component of DQ skew.
Figure 29: Data Input Timing
/CLK
T0
T1
T1n
T2
T2n
T3
CLK
tDQSS
tDSH1
tDSS2 tDSH1 tDSS2
DQS
tWPRES
tWPRE
tDQSL tDQSH tWPST
DIN
m
DQ
DM
tDS
tDH
Don’t Care
Notes :
1. tDSH (MIN) generally occurs during tDQSS (MIN).
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. WRITE command issued at T0.
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AS4C64M16MD1A-5BIN
Figure 30: Power-Down Mode (Active or Precharge)
tCLK
/CLK
tCH
tCL
CLK
tIS
CKE
tIS tIH
tPDX
tIS tIH
COMMAND
Valid
NOP
NOP
NOP
Valid
tIS tIH
Address
Valid
Valid
DQS
DQ
DM
Must not exceed Refresh device limits
Don’t Care
ENTER2
EXIT3
POWER-DOWN MODE
POWER-DOWN MODE
Notes :
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge
power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active
power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.
3. There must be at least one clock pulse during tPDX time.
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Figure 31: Auto Refresh Mode
tCLK
T0
/CLK
tCH tCL
T4
T5
CLK
tIS tIH
CKE
Valid
Valid
tIS tIH
COMMAND
NOP2
PRE
NOP2
NOP2
AR
NOP2,3
AR6
NOP2,3
NOP2
A0-A9,
ACT
RA
A11-A13
All Bank
A10
RA
One Bank
tIS tIH
BA0, BA1
Bank4
BA
DQS5
DQ5
DM5
tRP
tRFC
tRFC6
Don’t Care
Notes :
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row address, BA = Bank address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during
clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must be active during clock positive
transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
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AS4C64M16MD1A-5BIN
Figure 32: Self Refresh Mode
tCH
tCL
Ta0(1)
/CLK
CLK
Ta1
Tb0
tCLK
tIS
tIS
CKE
tIS tIH
tIS tIH
COMMAND
NOP
AR
NOP
Valid
tIS tIH
Valid
Address
DQS
DQ
DM
tXSR3
tRP2
Enter self refresh mode
Exit self refresh mode
Don’t Care
Notes :
1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. NOPs or DESELECT are required for tXSR time with at least two clock pulses.
4. AR = AUTO REFRESH command.
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Figure 33: Bank Read – Without Auto Precharge
tCH tCL
tCLK
T0
/CLK
T4
T5
CLK
CKE
tIS tIH
COMMAND
NOP5
ACT
NOP5
READ2
NOP5
PRE6
NOP5
ACT
NOP5
tIS tIH
A0-A9
RA
A11-A13
RA
RA
tIS tIH
A10
RA
Col n
ALL BANKS
3
RA
BA
RA
ONE BANK
BA0,BA1
Bank
x
Bank x
Bank x
tRCD
tRAS
tRC
tRP
DM
Case 1 : tAC and tDQSCLK(MIN)
CL = 3
tRPRE tDQSCLK(MIN) tRPST
DQS
tLZ(MIN)
Dout Dout Dout Dout
n n+1 n+2 n+3
DQ1
tAC(MIN)
Case 2 : tAC and tDQSCLK(MAX)
CL = 3
tRPRE
tHZ(MIN)
tDQSCLK(MAX)
tRPST
DQS
tLZ(MAX)
Dout Dout Dout Dout
n n+1 n+2 n+3
DQ1
tAC(MAX)
tHZ(MAX)
Notes :
1. Dout n = data-out from column n.
Don’t Care
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
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Figure 34: Bank Read – With Auto Precharge
/CLK
CLK
tCH tCL
tCLK
T0
T4
T5
tIStIH
CKE
COMMAND
NOP5
ACT
NOP5
READ2
NOP5
NOP5
NOP5
NOP5
ACT
tIS tIH
A0-A9
RA
A11-A13
RA
Col n
RA
RA
tIS tIH
A10
BA0,BA1
RA
BA
3
RA
BA
Bank x
Bank x
Bank
x
tRCD
tRAS
tRC
tRP
DM
Case 1 : tAC and tDQSCLK(MIN)
CL = 3
tRPRE
DQS
tDQSCLK(MIN)
tRPST
tLZ(MIN)
Dout Dout Dout Dout
n n+1 n+2 n+3
DQ1
tAC(MIN)
Case 2 : tAC and tDQSCLK(MAX)
CL = 3
tRPRE
tHZ(MIN)
tDQSCLK(MAX)
tRPST
DQS
tLZ(MAX)
Dout Dout Dout Dout
n n+1 n+2 n+3
DQ1
tAC(MAX)
tHZ(MAX)
Don’t Care
Notes :
1. Dout n = data-out from column n.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
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Figure 35: Bank Write – Without Auto Precharge
/CLK
CLK
tCLK
T0
tCH tCL
T4
T5
tIS tIH
CKE
tIS tIH
COMMAND
NOP6
ACT
NOP6
WRITE2
NOP6
NOP6
NOP6
NOP6
PRE
tIS tIH
A0- A9
RA
A11-A13
RA
Col n
tIS tIH
A10
RA
BA
ALL BANKS
3
ONE BANK
BA0,BA1
Bank x
Bank x
Bank x4
tRCD
tRAS
tWR
tRP
tDQSS(NOM)
DQS
tWPST
tDQSH
tDQSL
tWPRES
tWPRE
DQ1
Din
n
DM
Don’t Care
Notes :
1. Din n = data-in for column n.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from tCLK T4 or T5.
8. tDSH is applicable during tDQSS (MAX) and is referenced from tCLK T5 or T6.
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Figure 36: Bank Write – With Auto Precharge
/CLK
tCLK
T0
tCH tCL
T4
T5
CLK
tIS tIH
CKE
tIStIH
COMMAND
NOP5
ACT
NOP5
WRITE2
NOP5
NOP5
NOP5
NOP5
PRE
tIS tIH
A0-A9
RA
A11-A13
RA
A10
Col n
3
RA
BA
tIS tIH
BA0,BA1
Bank x
Bank x
tWR
tRCD
tRAS
tRP
tDQSS(NOM)
DQS
tWPRES
tWPRE
DQ
tWPST
tDQSH
tDQSL
Din
n
DM
Don’t Care
Notes :
1. Din n = data-in for column n.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. tDSH is applicable during tDQSS (MIN) and is referenced from tCLK T4 or T5.
7. tDSH is applicable during tDQSS (MAX) and is referenced from tCLK T5 or T6.
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Figure 37: Write – DM Operation
/CLK
T0
T1
T2
T3
T4
T5
WT2
NOP6
T6
T7
T8
NOP6
NOP6
PRE
CLK
tIS tIH
tCH tCL
tCLK
CKE
tIS tIH
COMMAND
NOP6
ACT
A0-A9
RA
A11-A13
RA
NOP6
NOP6
Col n
tIS tIH
A10
RA
ALL BANKS
3
ONE BANK
tIS tIH
BA0, BA1
Bank x
Bank x
Bank x4
tRCD
tWR
tRAS
tRP
tDQSS(NOM)
tWPSH
DQS
tDQSLtDQSH
tWPRES
tWPRE
DQ
DM
tDS
Don’t Care
tDH
Notes :
1. Din n = data-in for column n.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from tCLK T4 or T5.
8. tDSH is applicable during tDQSS (MAX) and is referenced from tCLK T5 or T6.
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AS4C64M16MD1A-5BIN
DEEP POWER DOWN MODE ENTRY
The Deep Power Down Mode is entered by having burst termination command, while CKE is low. The Deep Power
Down Mode has to be maintained for a minimum of 100us. The following diagram illustrates Deep Power Down mode
entry.
/CLK
T0
T1
T2
T3
T4
T5
T6
T7
CLK
CKE
tRP
COMMAND
NOP
Precharge
All Bank
NOP
Burst
Terminate
NOP
Precharge
If needed
Deep Power Down
Entry
Figure 38. Deep Power Down Mode Entry
DEEP POWER DOWN MODE EXIT SEQUENCE
The Deep Power Down Mode is exited by asserting CKE high.
After the exit, the following sequence is needed to enter a new command
1. Maintain NOP input conditions for a minimum of 200us
2. Issue precharge commands for all banks of the device
3. Issue 2 or more auto refresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue a extended mode register set command to initialize the extended mode register
The following timing diagram illustrates deep power down exit sequence
/CLK
CLK
CKE
COMMAND
Precharge
All Bank
ADDRESS
A10
AREF
MRS
NOP EMRS NOP Active
Key
Key
Bank a
Row
Normal
MRS
Extended
MRS
Row Active
A Bank
tRP
200 us
Deep Power Down
Exit
NOP
Precharge
All Bank
Figure 39. Deep Power Down Mode Exit
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AS4C64M16MD1A-5BIN
Unit : millimeters
60 BALL FBGA
Top View
Bottom View
1
A1
2
3
4
5
A1 INDEX MARK
E1
E
6
7
8
9
9
A
A
B
B
C
C
D
D
E
D
D1
F
8
7
6
5
4
3
2
1
e
E
F
G
G
H
H
J
J
K
K
D/2
e
E/2
Side View
z
A1
b
A
E
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A
A1
E
E1
D
D1
e
b
z
Min
0.275
0.40
-
Typ
0.30
8.00
6.40
9.00
7.20
0.80
0.45
-
Unit : mm
Max
1.00
0.325
0.50
0.10
Rev.1.0. Jan. 2018
AS4C64M16MD1A-5BIN
PART NUMBERING SYSTEM
AS4C
DRAM
64M16MD1A
64M16=64Mx16
MD1= Mobile
DDR1
A = A die
5
5=200MHz
B
I
N
B = FBGA
I=Industrial
(-40° C~+85° C)
Indicates Pb
and Halogen
Free
XX
Packing Type
None:Tray
TR:Reel
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be
the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any
errors that may appear in this document. The data contained herein represents Alliance's best data and/
or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time,
without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive
information for potential customers and users, and is not intended to operate as, or provide, any guarantee
or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties
related to the sale and/or use of Alliance products including liability or warranties related to fitness for
a particular purpose, merchantability, or infringement of any intellectual property rights, except as express
agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of
Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The
purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask
works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does
not authorize its products for use as critical components in life-supporting systems where a malfunction
or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance
products in such life-supporting systems implies that the manufacturer assumes all risk of such use and
agrees to indemnify Alliance against all claims arising from such use.
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