Datasheet | Rev. 1.1 | 2012
512Mbit Single-Data-Rate (SDR) SDRAM
AS4C64M8S-7TCN 64Mx8 (16M x 8 x 4 Banks)
AS4C32M16S-7TCN 32Mx16 (8M x 16 x 4 Banks)
Datasheet Version 1. 1
1
512 Mbit SDRAM AS4C[08/16]
Revision History
R
Rev. 1.1 April 2012
Revised Operating-; Standby- and Refresh Currents
0, Nov 2011
Rev. 1.0 March 2012
initial version
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously
improve the quality of this document.
Datasheet Version 1. 1
2
512 Mbit SDRAM AS4C[08/16]
1 | Overview
This chapter gives an overview of the 512Mbit SDRAM product and describes its main characteristics.
1.1 Features
Single 3.3 V ± 0.3 V Power Supply
LVTTL – compatible I/O
DRAM organizations with 8, 16 Data In/Outputs
Single Pulsed RASinterface
Fully synchronous to Positive Clock Edge
Four Banks controlled by BA0/BA1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1,2,4,8 or full page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write Control (x8)
Dual Data Mask for byte control (x16)
Suspend Mode and Power Down Mode
Standard Power Operation
Random Column Address every CK (1-N Rule)
Operating Temperature range 0°C to 70°C. Industrial
Temperature devices (Ordering code ending with "I")
allow an operating temperature range of -40°C to
85°C 1
Auto Refresh(CBR) and Self Refresh
8192 Refresh Cycles/64ms
54-pin TSOP II (400 mil) Package
RoHS Compliant Product 2
Electrically and mechanically JEDEC compliant
1 ambient Temperature
2 RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC
issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers. For more information please visit http://www.alliancememory.com
Datasheet Version 1. 1
3
512 Mbit SDRAM AS4C[08/16]
Table 1 - Performance Table
Unit
Speed Code
-7/-7I
Max. Data Rate
CAS-RCD-RP Latencies
Max. Clock Frequency
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
1
CL3
CL2
-7A/-7AI
Note
1
SDR
133
133
MHz
fCK3
fCK2
tRCD
tRP
tRAS
tRC
3-3-3
133
100
20
20
45
67.5
2-2-2
133
133
15
15
42
60
tCK
MHz
MHz
ns
ns
ns
ns
1
Versions marked -7A(I) support both: 2-2-2 and 3-3-3 at 133MHz (CAS-RCD-RP)
1.2 Description
The 512Mbit SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits
internally configured as a quad-bank DRAM with a
synchronous interface.
The x8 device is organized as 16M × 8 I/O × 4 banks, the
x16 device is organized as 8M x 16 I/O x 4 banks. These
synchronous devices achieve data transfer rates of up to
133 Mb/sec/pin for general applications.
See Table 1 for performance figures.
The device is designed in compliance with JEDEC
standards for SDRAM memory components both
electrically and mechanically.
The control signals RAS- CAS, WE-and- CSare pulsed
signals which are sampled at the positive edge of each
externally applied clock (CK).
Datasheet Version 1. 1
A thirteen bit address bus A[12:0] together with 2 Bank
select lines BA[1:0] accept address data in a RAS/ CAS
multiplexing style.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133 MHz is
possible depending on Burst Length and CASLatency.
Auto Refresh (CBR) and Self Refresh operation, both are
supported. The 512Mb SDRAM is available in 54-pin
TSOP-Type II package.
4
512 Mbit SDRAM AS4C[08/16]
Table 2 - Ordering Information for RoHS Compliant Products
Product Part Number 1
Org.
CAS-RCD-RP
Latencies 2 3 4
Max. Clock (MHz)
Package
Note
Standard Temperature Range (0°C to 70°C) 6
AS4C64M8S-7TCN
×8
3-3-3
133
54 TSOP II
5
AS4C32M16S-7TCN
×16
133
54 TSOP II
5
AS4C64M8S-7A
×8
3-3-3
2-2-2
133
54 TSOP II
57
AS4C32M16S-7A
×16
2-2-2
133
54 TSOP II
57
Industrial Temperature Range (-40°C to 85°C) 6
1
2
3
4
5
6
7
AS4C64M8S-7TIN
×8
3-3-3
133
54 TSOP II
5
AS4C32M16S-7TIN
×16
3-3-3
133
54 TSOP II
5
AS4C64M8S-7AI
×8
2-2-2
133
54 TSOP II
57
AS4C32M16S-7AI
×16
2-2-2
133
54 TSOP II
57
For detailed information regarding the part numbering of Alliance Memory products, please contact Alliance Memory for a separated "Part No. Decoder”.
CAS: Column Address Strobe
RCD: Row Column Delay
RP: Row Precharge
RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive
2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent
chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit http://www.alliancememory.com
Operating ambient temperature surrounding the package
Versions marked -7A support both: 2-2-2 and 3-3-3 (CAS-RCD-RP)
1.3 Addressing
Table 3 - Addressing
Configuration
64 Mb x 8 1
32 Mb x16 1
Bank Address
Number of Banks
Auto Precharge
Auto Refresh Cycles
Row Address
Column Address
Number of I/Os
BA[1:0]
4
A10 / AP
8192
A[12:0]
A[9:0] A11
8
BA[1:0]
4
A10 / AP
8192
A[12:0]
A[9:0]
16
Note
Notes:
1
Referred to as ’org’
Datasheet Version 1. 1
5
512 Mbit SDRAM AS4C[08/16]
2 | Configuration
This chapter contains the chip configuration.
2.1 Configuration for 54-pin TSOP II Package
The chip configuration of the SDRAM is listed by function in Table 3. The abbreviations used in the Pin# and Buffer Type
column are explained in Table 4 and Table 5 respectively.
Table 4 - PIN Description for 54-pin TSOP II Package
Name
x8 1
Name
x16 1
Pin Type Buffer Type
38
CLK
CLK
I
LVTTL
37
CKE
CKE
I
LVTTL
18
RAS
RAS
I
LVTTL
17
16
CAS
CAS
WE
WE
I
I
LVTTL
LVTTL
19
CS
CS
I
LVTTL
20
21
23
24
25
26
29
30
31
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
I
I
I
I
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
32
A7
A7
I
LVTTL
33
34
22
A8
A9
A10
A11
A12
A8
A9
A10
A11
A12
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Pin#
Function
Clock Signals
Clock Signal, all SDRAM Inputs are sampled on the rising edge
of the clock
Clock Enable activates (HIGH) and deactivates (LOW)
the CLK Signal
Control Signals
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select enables (registered LOW) and disables
(registered HIGH) the command decoder
Address Signals
35
36
Bank Address Bus BA[1:0]
Address Inputs A[12:0]
- continued next page Notes:
1
Referred to as ’org’
Datasheet Version 1. 1
6
512 Mbit SDRAM AS4C[08/16]
Continued Table 4 - PIN Description for 54-pin TSOP II Package
Name
x8
Name
x16
PIN Type
Buffer Type
Function
2
DQ0
DQ0
I/O
LVTTL
4
NC
DQ1
I/O
LVTTL
Data Signal DQ[7:0] for x8
Data Signal DQ[15:0] for x16
5
DQ1
DQ2
I/O
LVTTL
7
NC
DQ3
I/O
LVTTL
8
DQ2
DQ4
I/O
LVTTL
10
NC
DQ5
I/O
LVTTL
11
42
DQ3
NC
DQ6
DQ8
I/O
I/O
LVTTL
LVTTL
44
DQ4
DQ9
I/O
LVTTL
45
NC
DQ10
I/O
LVTTL
47
DQ5
DQ11
I/O
LVTTL
48
NC
DQ12
I/O
LVTTL
50
DQ6
DQ13
I/O
LVTTL
51
NC
DQ14
I/O
LVTTL
53
DQ7
DQ15
I/O
LVTTL
13
NC
DQ7
I/O
LVTTL
NC
DQM
DQML
DQMH
I
I
LVTTL
LVTTL
3, 9, 43, 49
VDDQ
VDDQ
PWR
–
1, 14, 27
VDD
VDD
PWR
–
6, 12, 46, 52
VSSQ
VSSQ
PWR
–
28, 41, 54
VSS
VSS
PWR
–
DQ Power: DQ Power to the die for improved noise
immunity
Power Supply +3.3V ± 0.3V
DQ Ground: isolated power supply and ground for the
output buffers for improved noise immunity
Power Supply Ground
NC
NC
NC
–
Not Connected
PIN#
Data Signals
Data Mask
15
39
Data Mask
Data Mask
Power Supplies
Not Connected
40
Datasheet Version 1. 1
7
512 Mbit SDRAM AS4C[08/16]
Table 5 - Abbreviations for Pin Type
Abbreviation
Description
I
O
I/O
PWR
GND
NC
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional Input/Output signal.
Power
Ground
Not Connected
Table 6 - Abbreviations for Buffer Type
Abbreviation
Description
SSTL
LVTTL
CMOS
Serial Stub Terminated Logic (SSTL_18)
Low Voltage TTL
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows
multiple devices to share as a wire-OR allows multiple devices to share as a wire-OR.
OD
Datasheet Version 1. 1
8
512 Mbit SDRAM AS4C[08/16]
Figure 1 - Ball Assignment for ×8 and ×16 Components, TSOP-54 (II)
Datasheet Version 1. 1
9
512 Mbit SDRAM AS4C[08/16]
3 | Functional Description
3.1 Mode Register Set (MRS)
The Mode Register 1 stores data defining the specific mode of operation including Burst Length (BL), Burst Type,
CAS Latency (CL) 2, Operating Mode and write Burst Mode of the SDRAM. Since power on state of the register is not
defined it must be initialized in order to avoid unpredictable start-up modes.
The Mode Register content can be altered by re-executing the Mode Register Set Command if needed.
In such a case however all 4 variables must be redefined when the Mode Register Set Command is issued.
Figure 2 – Mode Register Structure
1
Operation Mode, CAS Latency, Burst Type and Burst Length are user defined variables and must be programmed into the Mode Register before Read or Write
Cycles may begin. The Mode Register is programmed using the Mode Register Set Command. It retains the data until it is reprogrammed or power is switched
off the SDRAM.
2 CAS Latency defines the delay from when a Read Command is registered on a rising Clock Edge to when the data from that Read Command becomes available
at the Data I/O´s.
Datasheet Version 1. 1
10
512 Mbit SDRAM AS4C[08/16]
Table 7 - Mode Register (MR) Definition
Field
Bits
Type1
Description
Operation Mode [14:7]
w
CL
[6:4]
w
00000000B Normal Mode
00000100B Multiple Burst with Single Write
All other states reserved.*
CAS Latency
Note: All other bit combinations are reserved.
010B CL 2
011B CL 3
BT
3
w
BL
[2:0]
w
Burst Type
0B BT Sequential
1B BT Interleaved
Burst Length
Note: All other bit combinations are reserved.
BT (Bit3=0)
BT (Bit3=0)
000B Sequential BL: 1
Interleave BL: 1
001B Sequential BL: 2
Interleave BL: 2
010B Sequential BL: 4
Interleave BL: 4
011B Sequential BL: 8
Interleave BL: 8
111B Sequential: Full Page Interleave BL: 8
w = write only register bits
* BA1 and BA0 must be set to “0” when programming Mode Register MR
Burst Mode): 0 -> Normal Mode (read and write with programmed Burst Length)
1
Datasheet Version 1. 1
11
M9 (Write
1 -> Multiple Burst & Single Write location access
512 Mbit SDRAM AS4C[08/16]
3.2 Burst Mode Operation
Read and Write Operations to the device are burst oriented.
The Burst Type defines the sequence in which the data is Output and Input to the device. The Burst Types supported
are sequential and interleaved. Please refer to the below table.
The Bust Length (BL) is programmable in the Mode Register Bits [2:0] and controls the number of bits that will be Output
after a Read Command or being Input after a Write Command.
The Burst Operation Mode can be normal (Read and Write Cycles both are operated until the selected Burst Length is
worked through) or Multiple Burst with Single Write Operation.
Table 8 - Burst Length and Sequence (Burst Type)
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
2
XX0
0, 1
0, 1
XX1
1, 0
1, 0
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
n
Cn, Cn+1, Cn+2…
1, 0, 3, 2
4
8
256 (Full Page)
Datasheet Version 1. 1
12
512 Mbit SDRAM AS4C[08/16]
4 | Truth Tables
The truth tables in this chapter summarize the commands and the signal coding to control the SDRAM.
Table 9 - Command Truth Table
CKE
Function
Device State Previous Current CS
Mode Register Set
Idle
ReRERegisterSetSeSSE
Auto (CBR) Refresh
Idle
Tt
Self-Refresh Entry
Idle
Idle (SelfRefresh)
Re. Current
Single Bank Precharge
State Table
Re. Current
Precharge all Banks
State Table
Bank Activate
Idle
Write
Active
Self-Refresh Exit
1
2
3
4
5
Cycle
Cycle
H
H
H
X
H
L
L
H
H
BA0
BA1
RAS CAS WE DQM
A12
A11
A[9:0]
A10
L
L
L
H
L
L
L
L
X
H
L
L
L
X
H
L
H
H
X
H
X
X
X
X
X
X
X
X
X
X
L
L
H
L
X
BS
L
X
H
X
L
L
H
L
X
X
H
X
H
H
X
X
L
L
L
H
H
L
H
L
X
X
BS
BS
Row Address
L
Column
Note 1 2 3
OP Code
X
X
X
X
4
4
Write with AutoPrecharge
Read
Read with AutoPrecharge
Burst Stop
No Operation
Device Deselect
Clock Suspend Mode
Entry
Clock Suspend Mode
Exit
Data Write/Output
Enable
Data Write/Output
Disable
Active
H
X
L
H
L
L
X
BS
H
Column
4
Active
H
X
L
H
L
H
X
BS
L
Column
4
Active
H
X
L
H
L
H
X
BS
H
Column
4
Active
Any
Any
H
H
H
X
X
X
L
L
H
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Active
H
L
X
X
X
X
X
X
X
X
5
Active
L
H
X
X
X
X
X
X
X
X
5
Active
H
X
X
X
X
X
L
X
X
X
6
Active
H
X
X
X
X
X
H
X
X
X
Power Down Entry
Idle/Active
H
L
X
H
X
H
X
X
7, 8
H
X
H
X
H
X
Any(Power
L
Down)
X
H
X
H
X
Power Down Exit
H
L
H
L
X
X
X
X
7, 8
6
All SDRAM Operations are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
“X” means H or L (but a defined logic level).
Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted
through the specified initialization sequence before normal operation can continue.
Bank addresses BA[1:0] determine which bank is to be operated upon
In normal access mode, CKE is held high and CK is enabled. When CKE is low it freezes the internal clock and extends data Read and Write operations. One
clock delay is required for mode entry and exit.
Datasheet Version 1. 1
13
512 Mbit SDRAM AS4C[08/16]
6
7
8
DQM has two functions for the data DQ Read and Write operations. During a Read Cycle when DQM goes high during a clock timing the data outputs are
disabled and become high impedance after a two-clock delay. During Write Cycles when activated the Write operation at the clock cycle is prohibited
(zero clock latency).
All banks must be precharged before entering Power Down Mode. If this command is issued during a Burst operation, the device state will be Clock Suspend
Mode. The Powerd Down Mode does not perform any Refresh operations therefore the device can not remain in this mode longer than the Refresh period
(tREF) duration. One clock delay is required for mode entry and exit.
A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
Table 10 – Bank Selection Bits (BS) Truth Table
BA0
BA1
Bank
L
H
L
H
L
L
H
H
Bank 0
Bank 1
Bank 2
Bank 3
Datasheet Version 1. 1
14
512 Mbit SDRAM AS4C[08/16]
Table 11 - Clock Enable (CKE) Truth Table
Current State
Self Refresh
Power Down
All Banks Idle
Any State
other than
listed above
1.
2.
3.
4.
5.
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BAO,
BA1
A12
- A0
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Power Down Mode exit, all Banks Idle
2
L
L
X
X
X
X
X
X
Maintain Power Down Mode
H
H
H
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
L
L
L
H
X
H
H
L
L
L
L
OP Code
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
L
L
L
H
X
H
L
L
L
L
L
X
X
X
H
H
X
H
L
L
L
3
Refer to the Idle State section of the
Current State Truth Table
X
3
3
CBR Refresh
Mode Register Set
4
3
Refer to the Idle State section of the
Current State Truth Table
3
X
Entry Self Refresh
4
L
OP Code
Mode Register Set
X
X
X
X
Power Down
X
X
X
X
X
Refer to operations in the Current State
Truth Table
X
X
X
X
X
X
Begin Clock Suspend next Cycle
H
X
X
X
X
X
X
Exit Clock Suspend next Cycle
L
X
X
X
X
X
X
Maintain Clock Suspend
3
4
5
For the given Current State CKE must be low in the previous Cycle.
When CKE has a low to high transition, the Clock and other Inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES )
must be satisfied. When exiting power down mode, a NOP command (or Device Deselected Command) is required on the first rising clock
after CKE goes high (see page 26).
The address inputs depend on the command that is issued. See the Idle State section of the current State Truth Table for more information.
The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only entered from the all banks idle state.
Must be a legal command as defined in the Current State Truth Table.
Datasheet Version 1. 1
15
512 Mbit SDRAM AS4C[08/16]
Table 12 – Current State Truth Table (See Note 1) Part 1/3
Current State
Command
CS
Idle
Row Active
Read
Write
Datasheet Version 1. 1
RAS CAS
WE
BAO, BA1
Action
A12- A0
Notes
Description
L
L
L
L
OP Code
Mode Register Set
L
L
L
H
X
X
Auto or Self Refresh Start Auto or Self Refresh
L
L
H
L
BS
X
Precharge
No Operation
L
L
H
H
BS
Bank Activate
Activate the specified bank and row
L
H
L
L
BS
Column
Write w/o Prechage ILLEGAL
4
L
H
L
H
BS
Column
Read w/o Prechage ILLEGAL
4
L
H
H
L
X
X
Burst Stop
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation or Power Down
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
Precharge
6
L
L
H
H
BS
Bank Activate
ILLEGAL
4
L
H
L
L
BS
Column
Write
Start Write; Determine if
Auto Precharge
7, 8
L
H
L
H
BS
Column
Read
Start Read; Determine if
Auto Precharge
7, 8
L
H
H
L
X
X
Burst Stop
ILLEGAL
Row Address
OP Code
Row Address
Set the Mode Register
2
2, 3
5
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
Terminate Burst; Start Precharge
L
L
H
H
BS
Bank Activate
ILLEGAL
L
H
L
L
BS
Column
Write
Terminate Burst; Start Write Cycle
8, 9
L
H
L
H
BS
Column
Read
Terminate Burst; Start a new
Read Cycle
8, 9
L
H
H
L
X
X
Burst Stop
Burst Stop
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
L
L
H
L
BS
L
L
H
H
BS
L
H
L
L
BS
L
H
L
H
L
H
H
L
H
H
H
X
X
X
OP Code
Row Address
OP Code
4
X
Auto or Self Refresh ILLEGAL
X
Precharge
Terminate Burst; Start the Precharge
Bank Activate
ILLEGAL
Column
Write
Terminate Burst; Start a new
Write Cycle
8, 9
BS
Column
Read
Terminate Burst; Start the Read Cycle
8, 9
L
X
X
Burst Stop
Burst Stop
H
X
X
No Operation
Continue the Burst
X
X
Device Deselect
Continue the Burst
Row Address
16
4
512 Mbit SDRAM AS4C[08/16]
Table 12 – Current State Truth Table
Part 2/3
Current State
Command
CS
Read with Auto
Precharge
Write with Auto
Precharge
Precharging
Row Activating
Datasheet Version 1. 1
RAS CAS
L
L
L
L
WE
BAO, BA1
Action
A12- A0
Notes
Description
L
L
OP Code
Mode Register Set
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
Bank Activate
ILLEGAL
4
L
H
L
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Stop
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
Bank Activate
ILLEGAL
4
L
H
L
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Stop
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
No Operation; Bank(s) idle after tRP
L
L
H
H
BS
Bank Activate
ILLEGAL
4
L
H
L
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Stop
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
Bank Activate
ILLEGAL
4, 10
L
H
L
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Stop
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Row Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation; Row Active after tRCD
Row Address
OP Code
Row Address
OP Code
Row Address
OP Code
Row Address
17
ILLEGAL
512 Mbit SDRAM AS4C[08/16]
Table 12 – Current State Truth Table
Part 3/3
Current State
Command
CS
Write Recovering
Write Recovering
with Auto
Precharge
Refreshing
Mode Register
Accessing
Datasheet Version 1. 1
RAS CAS
WE
BAO, BA1
Action
A12- A0
Notes
Description
L
L
L
L
L
L
L
H
X
OP Code
X
Mode Register Set
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
Bank Activate
ILLEGAL
4
L
H
L
L
BS
Column
Write
Start Write; Determine if Auto
Precharge
9
L
H
L
H
BS
Column
Read
Start Read; Determine if Auto
Precharge
9
L
H
H
H
X
X
No Operation
No Operation; Row Active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Row Active after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
4
L
L
H
H
BS
Bank Activate
ILLEGAL
4
L
H
L
L
BS
Column
Write
ILLEGAL
4, 9
L
H
L
H
BS
Column
Read
ILLEGAL
4, 9
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BS
X
Precharge
ILLEGAL
L
L
H
H
BS
Bank Activate
ILLEGAL
L
H
L
L
BS
Column
Write
ILLEGAL
L
H
L
H
BS
Column
Read
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
L
L
H
L
BS
L
L
H
H
BS
L
H
L
L
BS
L
H
L
H
BS
L
H
H
H
X
H
X
X
X
X
Row Address
OP Code
Row Address
OP Code
Row Address
OP Code
ILLEGAL
X
Auto or Self Refresh ILLEGAL
X
Precharge
ILLEGAL
Bank Activate
ILLEGAL
Column
Write
ILLEGAL
Column
Read
ILLEGAL
X
No Operation
No Operation; Idle after two
clock cycles
X
Device Deselect
No Operation; Idle after two
clock cycles
Row Address
18
512 Mbit SDRAM AS4C[08/16]
Legend of the Current State Truth Table (Part 1 to 3)
1.
CKE is assumed to be active (high) in the previous cycle for all entries.
The Current State is the state of the bank that the Command is being applied to.
2.
All Banks must be idle; otherwise, it is an illegal action.
3.
If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh Operation, if CKE is inactive (low) than the Self Refresh mode is entered.
4.
The Current State refers to only one of the banks. If BS selects this bank then the action is illegal.
If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank.
5.
If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6.
The minimum and maximum Active time (tRAS) must be satisfied.
7.
The RASto CASDelay (tRCD) must occur before the command is given.
8.
Column address A10 is used to determine if the Auto Precharge function is activated.
9.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied
Datasheet Version 1. 1
19
512 Mbit SDRAM AS4C[08/16]
5 | Electrical Characteristics
This chapter describes the Electrical Characteristics.
5.1 Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device at any time.
Table 13 - Absolute Maximum Ratings
Symbol
Parameter
VDD
VDDQ
VIN VOUT
PD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
TSTG
1
Rating
Unit
Min.
Max.
–0.3
–0.3
–0.3
–
–55
+4.6
+4.6
Note
V
V
V
W
°C
VDD +0.3
+1.0
+125
1
Storage Temperature is the ambient (case surface) temperature (on the center/top side) of the DRAM
Attention:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 14 - DRAM Component Operating Temperature Range
1
2
3
Symbol
Parameter
Rating
Min.
Max.
TA
TA
Operating Temperature for standard product
Operating Temperature for Industrial Temperature product
0
-40
+70
+85
Unit
Note
°C
°C
123
12 3
Operating Temperature is the ambient temperature around the DRAM.
The Operating Temperature ranges are the temperatures where all DRAM specification will be supported.
During operation, the temperature must be maintained under all other specification parameters.
Datasheet Version 1. 1
20
512 Mbit SDRAM AS4C[08/16]
5.2 DC Characteristics
Table 15 - Recommended DC Operating Conditions
Symbol
Parameter
Rating
Typ.
Min.
VDD
VDDQ
VIH
VTT
1
2
3
Supply Voltage
Supply Voltage for Output
Input High Voltage
Termination Voltage
3.0
3.0
2.0
– 0.3
3.3
3.3
-–
-–
Unit
Note
V
V
V
V
1
Max.
3.6
3.6
VDD + 0.3
0.8
1
12
13
All Voltages are referenced to VSS and VSSQ
VIH (max) = VDD + 1.2V for pulse width ≤ 5ns
VIL (min) = VSS + 1.2V for pulse width ≤ 5ns
Table 16 - Input and Output Leakage Currents
1
2
Symbol
Parameter / Condition
IIL
IOL
Input Leakage Current; any input 0 V < VIN < VDD
Output Leakage Current; 0 V < VOUT < VDDQ
Min.
Max.
Unit
Note
–2
–2
+2
+2
μA
μA
1, 2
Min.
Max.
Unit
Note
2.4
–
–
0.4
V
V
1
2
All other pins not under test = 0 V
VDD = 3.3V ± 0.3V
Table 17 – DC Logic Output Levels
1
2
Symbol
Parameter / Condition
VOH
VOL
Output Level (LVTTL); Output “H” Voltage Level
Output Level (LVTTL); Output “L” Voltage Level
2
Iout = -2.0mA
Iout = +2.0mA
Datasheet Version 1. 1
21
512 Mbit SDRAM AS4C[08/16]
5.3 Operating-, Standby- and Refresh Currents
Table 18 – Operating-, Standby- and Refresh Currents
Symbol
Parameter
Test Condition
ICC1
Operating Current
1 bank operation 1
tRC = tRC(min), tCK = min
ICC2P
Precharge Standby Current CKE ≤ VIL(max), tCK =min, CS= VIH(min)
in Power Down Mode
CKE ≤ VIL(max), tCK = ∞, CS= VIH(min)
Precharge Standby Current
V
t
V
in Non-Power Down Mode CKE ≥ IH(min), CK =min, CS= IH(min)
ICC2PS
ICC2N
ICC3N
ICC3P
ICC3NS
ICC4
ICC5
ICC6N
1
2
3
4
5
6
7
No Operating Current
(Active State 4bank)
Unit
-7/-7A (133MHz)
Max.
CKE ≥ VIH(min), tCK =min, CS= VIH(min)
CKE ≤ VIL(max), tCK =min
CKE ≥ VIL(min), tCK = ∞
Operating Current (Burst tCK =min, Rea/Write command cycling,
Multiple banks active, gapless data, BL=4
Mode)
Auto (CBR) Refresh Current tCK =min, tRC = tRC(min), CBR command Cycling
CKE ≤ 0.2V
Self Refresh Current
Note
130
mA
7
mA
5
mA
58
mA
75
10
49
mA
mA
mA
4
120
mA
36
270
5
mA
mA
23
4
5
7
Active-Precharge command cycling without Burst Operation.
These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC.
Input signals are changed up to three times during tRC(min).
The specified values are obtained with the output open.
Input signals are changed once during three clock cycles.
Active Standby Current will be higher if Clock Suspend is entered during a Burst Read Cycle (add 1mA per DQ).
Input signals are changed once during tCK =min
Input signals are stable
Datasheet Version 1. 1
22
512 Mbit SDRAM AS4C[08/16]
5.4 Input/Output Capacitance
This chapter contains the Input and the Output Capacitance.
Table 19 - Input/Output Capacitance
Symbol
Parameter
Min.
Typ
Max
CCK
CI
CIO
Input Capacitance, CK
Input Capacitance, all other Input - only pins
Input/Output Capacitance, DQn
2.5
2.5
4.0
2.8
3.0
4.5
3.5
3.8
6.5
Datasheet Version 1. 1
23
Unit
pF
pF
pF
Notes
512 Mbit SDRAM AS4C[08/16]
5.5 Clock- and Clock Enable Parameters
This chapter describes the Clock- and Clock Enable Parameters.
Table 20 – Clock and Clock Enable Parameters
Speed Grade
Symbol Parameter
tCK3
tCK2
tAC3
tAC2
tCKH
tCKL
tCES
tCEH
tSB
tT
1
-7 / -7I
Min.
Max.
Clock Cycle Time, CAS Latency = 3
Clock Cycle Time, CAS Latency = 2
Clock Access Time, CAS Latency = 3
Clock Access Time, CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Clock Enable Set-up Time
Clock Enable Hold Time
Power Down Mode Entry Time
Transition Time (Rise and Fall)
7.5
10
—
—
2.5
2.5
1.5
0.8
0
0.5
1000
1000
5.4
6
—
—
—
—
7.5
10
-7A / -7AI
Min.
Max.
7
7.5
—
—
2.5
2.5
1.5
0.8
0
0.5
Unit
1000
1000
5.4
5.4
—
—
—
—
7.5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-7A / -7AI
Min.
Max.
Unit
Note
1
1
Access time is measured at 1.4V
5.6 Common Parameters
This chapter describes the Common Parameters.
Table 21 – Common Parameters
Speed Grade
Symbol Parameter
tCS
tCH
tAS
tAH
tRCD
tRC
tRAS
tRP
tRRD
tCCD
1
-7 / -7I
Command Setup Time
Command Hold Time
Address and Bank Select Set-up Time
Address and Bank Select Hold Time
RAS to CAS Delay
Bank Cycle Time
Active Command Period
Precharge Time
Bank to Bank Delay Time
CAS to CAS Delay Time
Min.
Max.
1.5
0.8
1.5
0.8
20
66
45
20
15
1
—
—
—
—
—
—
100K
—
—
—
1.5
0.8
1.5
0.8
15
60
37
15
14
1
—
—
—
—
—
—
100K
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
Note
1
1
1
1
1
The Parameters account for the number of Clock Cycle and depend on the operating frequency of the clock as follows:
Number of Clock Cycles = specified value of timing / clock period (fractions are counted as whole numbers).
Datasheet Version 1. 1
24
512 Mbit SDRAM AS4C[08/16]
6 | AC Timing Parameters
Table 22 – Mode Register Set Cycle
Speed Grade
Symbol Parameter
tRSC
-7 / -7I
Mode Register Set Cycle Time
Min.
Max.
15
—
-7A / -7AI
Min.
Max.
15
—
Unit
Note
ns
Table 23 – Refresh Cycle
Speed Grade
Symbol Parameter
tREF
tSREX
1
-7 / -7I
Refresh Period
Self Refresh Exit Time
Min.
Max.
—
1
64
—
-7A / -7AI
Min.
Max.
—
1
64
—
Unit
ms
CK
Note
1
8192 auto refresh cycles
Table 24 – Read Cycle
Speed Grade
Symbol Parameter
1
2
tOH
Data Out Hold Time
tLZ
tHZ(3)
tHZ(2)
tDQZ
Data Out to Low Impedance Time
Data Out to High Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
-7 / -7I
CL = 3
CL = 2
Min.
Max.
—
2.7
1
—
—
2
—
—
—
5.4
6
—
-7A / -7AI
Min.
Max.
—
2.7
1
—
—
2
—
—
—
5.4
5.4
—
Unit
ns
ns
ns
ns
Note
1
2
CK
Data Out Hold Time with no load must meet 1.8ns
Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels
Table 25 – Write Cycle
Speed Grade
Symbol Parameter
-7 / -7I
Min.
Max.
1.5
0.8
15
tDS
tDH
tDPL
Mode Data In Set-up Time
Data In Hold Time
Data Input to Precharge
1.5
0.8
15
tWR
Write Recovery Time
15
—
—
—
—
tDAL
tDQW
Data In to Active Delay
5
DQM Write Mask Latency
0
Datasheet Version 1. 1
-7A / -7AI
Min.
Max.
25
Unit
ns
ns
ns
14
—
—
—
—
—
4
—
CK
—
0
—
CK
Note
ns
512 Mbit SDRAM AS4C[08/16]
7 | Package Outline
This chapter contains the package dimension figures.
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Figure 3 - Package Outline 54 - Pin Plastic TSOP (400mil)
Datasheet Version 1. 1
26
512 Mbit SDRAM AS4C[08/16]
8 | Contents
Revision History
2
1 | Overview
3
1.1 Features
3
1.2 Description
4
1.3 Addressing
5
2 | Configuration
6
2.1 Configuration for 54-pin TSOP II Package
6
3 | Functional Description
10
3.1 Mode Register Set (MRS)
10
3.2 Burst Mode Operation
12
4 | Truth Tables
13
5 | Electrical Characteristics
20
5.1 Absolute Maximum Ratings
20
5.2 DC Characteristics
21
5.3 Operating-, Standby- and Refresh Currents
22
5.4 Input/Output Capacitance
23
5.5 Clock- and Clock Enable Parameters
24
5.6 Common Parameters
24
6 | AC Timing Parameters
25
7 | Package Outline
26
8 | Contents
27
List of Tables
28
List of Illustrations
29
Edition March 2012 | Published by Alliance Memory, Inc.
30
Alliance Memory, Inc. | Global Presence
Datasheet Version 1. 1
27
512 Mbit SDRAM AS4C[08/16]
List of Tables
Table 1 - Performance Table
Table 2 - Ordering Information for RoHS Compliant Products
Table 3 - Addressing
Table 4 - PIN Description for 54-pin TSOP II Package
Table 5 - Abbreviations for Pin Type
Table 6 - Abbreviations for Buffer Type
Table 7 - Mode Register (MR) Definition
Table 8 - Burst Length and Sequence (Burst Type)
Table 9 - Command Truth Table
Table 10 - Bank Selection Bits (BS) Truth Table
Table 11 - Clock Enable (CKE) Truth Table
Table 12 - Current State Truth Table (Part 1/3)
Table 12 - Current State Truth Table (Part 2/3)
Table 12 - Current State Truth Table (Part 3/3)
Table 13 - Absolute Maximum Ratings
Table 14 - DRAM Component Operating Temperature Range
Table 15 - Recommended DC Operating Conditions
Table 16 - Input and Output Leakage Currents
Table 17 - DC Logic Output Levels
Table 18 - Operating-, Standby- and Refresh Currents
Table 19 - Input/Output Capacitance
Table 20 – Clock- and Clock Enable Parameters
Table 21 - Common Parameters
Table 22 - Mode Register Set Cycle
Table 23 - Refresh Cycle
Table 24 - Read Cycle
Table 25 - Write Cycle
Datasheet Version 1. 1
28
4
5
5
6
8
8
11
12
13
14
15
16
17
18
20
20
21
21
21
22
23
24
24
25
25
25
25
512 Mbit SDRAM AS4C[08/16]
List of Illustrations
Figure 1 - Ball Assignment for ×8 and ×16 Components, TSOP-54 (II)
Figure 2 - Mode Register Structure
Figure 3 - Package Outline 54 - Pin Plastic TSOP (400mil)
Datasheet Version 1. 1
29
9
10
27
512 Mbit SDRAM AS4C[08/16]
Edition April 2012 | Published by Alliance Memory, Inc.
Alliance Memory, Inc.
551 Taylor Way
San Carlos, CA 94070
Tel: 1-650-610-6800
Fax: 1-650-620-9211
© Alliance Memory, Inc. 2012
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE OF
CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY TYPICAL VALUES
STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE, ALLIANE MEMORY, INC.
HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT LIMITATION
WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Alliance
Memory Office.
Warnings
Due to technical requirements components may contain dangerous substances.
For information on the types in question please contact your nearest Alliance Memory office.
Alliance Memory may only be used in life-support devices or systems with the express written approval of Alliance
Memory, if a failure of such components can reasonably be expected to cause the failure of that life-support device or
system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to
be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is
reasonable to assume that the health of the user or other persons may be endangered.
www.alliancememory.com
Datasheet Version 1. 1
30
512 Mbit SDRAM AS4C[08/16]
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Alliance Memory:
AS4C64M8SA-7TCNTR AS4C64M8SA-7TCN
工商网监
湘ICP备2023018690号
