AS4C8M16D1-5BIN

128M DDR1 -AS4C8M16D1 Revision History AS4ϴDϭϲϭ - ϲϬ-ball FBGA PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date DĂLJ201ϱ $OOLDQFH0HPRU\,QF7D\ORU:D\6DQ&DUORV&$7(/)$; $OOLDQFH0HPRU\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH &RQILGHQWLDO  5HY 0D\ 128M DDR1 -AS4C8M16D1 )HDWXUHV ¥ Fast clock rate: 250/200MHz • Operating temperature: - Commercial (0°C~70°C) - Industrial (-40°C~85°C) ¥ Differential Clock CK & CK input ¥ Bi-directional DQS ¥ DLL enable/disable by EMRS ¥ Fully synchronous operation ¥ Internal pipeline architecture ¥ Four internal banks, 2M x 16-bit for each bank ¥ Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved ¥ Individual byte write mask control ¥ DM Write Latency = 0 ¥ Auto Refresh and Self Refresh ¥ 4096 refresh cycles / 64ms ¥ Precharge & active power down ¥ Power supplies: VDD & VDDQ = 2.5V ± 0.2V ¥ Interface: SSTL_2 I/O Interface ¥ Package: 60-Ball, 8x13x1.2 mm (max) FBGA - Pb free and Halogen free &RQILGHQWLDO  5HY 0D\ 128M DDR1 -AS4C8M16D1 2YHUYLHZ The 128Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK DQG&. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The device provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, 128Mb DDR features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance. 7DEOH2UGHULQJ,QIRUPDWLRQ 3DUW1XPEHU $6&0'%&1 $6&0'%,1 &RQILGHQWLDO 2UJ  [  [ 7HPSHUDWXUH 0D[&ORFN0+]  &RPPHUFLDOƒ&WRƒ&  ,QGXVWULDOƒ&WRƒ&  3DFNDJH EDOO)%*$ EDOO)%*$ 5HY 0D\ 128M DDR1 -AS4C8M16D1 )LJXUH%DOO$VVLJQPHQW7RS9LHZ &RQILGHQWLDO 1 2 A 9664 '4 B '4 C 3 7 8 966 9'' '4 9''4 9''4 '4 '4 9664 '4 '4 9664 '4 '4 9''4 '4 D '4 9''4 '4 '4 9664 '4 E '4 9664 8'46 /'46 9''4 '4 F 95() 966 8'0 /'0 9'' 1& G &. &. :( &$6 H 1& &.( 5$6 &6 J $ $ %$ %$ K $ $ $ $ L $ $ $ $ M $ 966 9'' $
 9 5HY0D\ 128M DDR1 -AS4C8M16D1 )LJXUH%ORFN'LDJUDP &. &. '// &/2&. %8))(5 &200$1' '(&2'(5 &2/801 &2817(5 $$3 &21752/ 6,*1$/ *(1(5$725 02'( 5(*,67(5 0[ &(//$55$< %$1. &ROXPQ'HFRGHU a $ $ %$ %$ 5()5(6+ &2817(5 /'46 8'46 '$7$ 6752%( %8))(5 '4 5RZ 'HFRGHU $''5(66 %8))(5 $ 0[ &(//$55$< %$1. &ROXPQ'HFRGHU '4 %XIIHU /'0 8'0  5RZ 'HFRGHU a '4 &RQILGHQWLDO 0[ &(//$55$< %$1. &ROXPQ'HFRGHU 5RZ 'HFRGHU &6 5$6 &$6 :( 5RZ 'HFRGHU &.( 0[ &(//$55$< %$1. &ROXPQ'HFRGHU 5HY0D\ 128M DDR1 -AS4C8M16D1 3LQ'HVFULSWLRQV 7DEOH3LQ'HWDLOV 6\PERO 7\SH 'HVFULSWLRQ CK, CK Input 'LIIHUHQWLDO &ORFN CK, CK are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. Both CK and CK increment the internal burst counter and controls the output registers. CKE Input &ORFN (QDEOH CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0, BA1 Input %DQN $FWLYDWH BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. A0-A11 Input $GGUHVV,QSXWVA0-A11 are sampled during the BankActivate command (row address A0A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge). CS Input &KLS6HOHFW CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS Input 5RZ $GGUHVV 6WUREH The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. CAS Input &ROXPQ$GGUHVV6WUREH The CAS signal defines the operation commands in conjunction with the RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGHÓ or ÒLOW". WE Input :ULWH (QDEOH The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. LDQS, Input / UDQS Output %LGLUHFWLRQDO'DWD6WUREHSpecifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. LDM, Input 'DWD ,QSXW 0DVN Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. DQ0 - DQ15 Input / Output 'DWD ,2 The DQ0-DQ15 input and output data are synchronized with positive and negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes. VDD Supply 3RZHU6XSSO\+2.5V ± 0.2V VSS Supply *URXQG VDDQ Supply '43RZHU+2.5V ± 0.2V. Provide isolated power to DQs for improved noise immunity. VSSQ Supply '4*URXQGProvide isolated ground to DQs for improved noise immunity. VREF Supply 5HIHUHQFH9ROWDJHIRU,QSXWV+0.5*VDDQ NC - UDM &RQILGHQWLDO 1R&RQQHFWNo internal connection, these pins suggest to be left unconnected.  5HY0D\ 128M DDR1 -AS4C8M16D1 2SHUDWLRQ0RGH Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3 shows the truth table for the operation commands. 7DEOH7UXWK7DEOH1RWH &RPPDQG BankActivate 6WDWH &.(Q &.(Q '0 %$ $ $ Idle(3) H X X V L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X Write Active(3) H X L L H L H X X Write and AutoPrecharge Active(3) V L L H L L X V H Column address (A0 ~ A8) H X L H L L Read Active(3) H X X V L L H L H H X X V H Column address (A0 ~ A8) Read and Autoprecharge Active(3) L H L H Mode Register Set Idle H X X OP code L L L L Extended MRS Idle H X X OP code L L L L No-Operation Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V H X X X L H H H X X X X Data Input Mask Enable(5) Active H X H X X X X 1RWH 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 2, 4, and 8 burst operation. 5. LDM and UDM can be enabled respectively. X X X Burst Stop Row address &6  5$6  &$6  :(  (SelfRefresh) Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit Idle Any H L L H X X X X X X X X (PowerDown) Active Any H L L H X X X X X X X X (PowerDown) Data Input Mask Disable &RQILGHQWLDO Active H X L  X X X 5HY 0D\ 128M DDR1 -AS4C8M16D1 0RGH5HJLVWHU6HW056 The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A11 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies. 7DEOH0RGH5HJLVWHU%LWPDS BA1 BA0 A11 A10 0 0 A8 0 0 A7 Test Mode 0 Normal mode 0 DLL Reset 1 Test mode 1 X A9 BA0 Mode 0 MRS 1 EMRS A8 A7 T.M. A6 A5 A4 CAS Latency A6 A5 A4 CAS Latency Reserved 0 0 0 Reserved 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 A3 BT A2 A1 A0 Burst Length A3 Burst Type 0 Sequential Address Field Mode Register A2 A1 A0 0 0 0 Burst Length Reserved 0 0 1 2 2 0 1 0 4 3 Reserved Reserved 2.5 Reserved 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 8 Reserved Reserved Reserved Reserved 1 Interleave ¥ Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, and 8. 7DEOH%XUVW/HQJWK A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved &RQILGHQWLDO  5HY 0D\ 128M DDR1 -AS4C8M16D1 ¥ Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4, and 8. 7DEOH$GGUHVVLQJ0RGH ¥ A3 Addressing Mode 0 Sequential 1 Interleave Burst Definition, Addressing Sequence of Sequential and Interleave Mode 7DEOH%XUVW$GGUHVVRUGHULQJ Burst Length 2 4 8 Start Address A2 A1 A0 X X 0 X X 1 X 0 0 X 0 1 X 1 0 X 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sequential Interleave 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 ¥ CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ! CAS Latency X tCK 7DEOH&$6/DWHQF\ A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 clocks 1 1 1 Reserved &RQILGHQWLDO  5HY 0D\ 128M DDR1 -AS4C8M16D1 ¥ Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. 7DEOH7HVW0RGH A8 A7 Test Mode 0 0 Normal mode 1 0 DLL Reset 1 Test mode X ¥ (BA0, BA1) 7DEOH056(056 BA1 BA0 A11 ~ A0 RFU 0 MRS Cycle RFU 1 Extended Functions (EMRS) ([WHQGHG0RGH5HJLVWHU6HW(056 The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE . The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes. 7DEOH([WHQGHG0RGH5HJLVWHU%LWPDS BA1 BA0 A11 0 1 A10 A9 A8 A7 RFU must be set to Ò0Ó A6 Mode MRS A6 0 A1 0 Drive Strength Full 1 EMRS 0 1 Weak 1 0 1 &RQILGHQWLDO A4 A3 A2 A1 A0 Address Field DS1 RFU must be set to Ò0Ó DS0 DLL Extended Mode Register BA0 0 1 A5 Comment A0 0 DLL Enable 1 Disable RFU Reserved For Future Matched impedance Output driver matches impedance  5HY 0D\ 128M DDR1 -AS4C8M16D1 7DEOH$EVROXWH0D[LPXP5DWLQJ 6\PERO 5DWLQJ ,WHP VIN, VOUT I/O Pins Voltage VIN - 0.5~VDDQ + 0.5 V - 1~3.6 V - 1~3.6 V Commercial 0~70 !C Industrial -40~85 !C - 55~150 !C 1 W VREF and Inputs Voltage VDD, VDDQ Power Supply Voltage TA Ambient Temperature TSTG Storage Temperature PD 8QLW  Power Dissipation Short Circuit Output Current IOS 50 mA Note1: Stress greater than those listed under ÒAbsolute Maximum RatingsÓ may cause permanent damage of the devices Note2: These voltages are relative to Vss 7DEOH5HFRPPHQGHG'&2SHUDWLQJ&RQGLWLRQV 6\PERO VDD 3DUDPHWHU Power Supply Voltage VDDQ Power Supply Voltage (for I/O Buffer) VREF VTT 0LQ 8QLW 2.3 2.7 V 2.3 2.7 V Input Reference Voltage 0.49 * VDDQ 0.51 * VDDQ V Termination Voltage VREF - 0.04 VREF + 0.04 V VREF + 0.15 VDDQ + 0.3 V VIH (DC) Input High Voltage (DC) VIL (DC) Input Low Voltage (DC) VIN (DC) Input Voltage Level, CK and CK inputs Input Leakage current, Any input 0V " VIN " VDD II (All other pins not under test = 0 V) IOZ Output Leakage current IOH Output High Current (VOUT = 1.95V) IOL 0D[ Output Low Current (VOUT = 0.35V) -0.3 VREF - 0.15 V -0.3 VDDQ + 0.3 V -2 2 µA -5 µA -16.2 5  mA 16.2  mA 0LQ 0D[ 8QLW 2 3 pF 7DEOH&DSDFLWDQFH9'' 9I 0+]7$ ¡& 6\PERO CIN1 CIN2 3DUDPHWHU Input Capacitance (CK, CK ) Input Capacitance (All other input-only pins) 2 3 DQ, DQS, DM Input/Output Capacitance CI/O 4 5 Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested &RQILGHQWLDO  pF pF 5HY 0D\ 128M DDR1 -AS4C8M16D1 7DEOH'&&KDUDFWHULVWLFV9'' 9“97$ a¡& 3DUDPHWHU 7HVW&RQGLWLRQ 6\PERO 23(5$7,1*&855(17One bank; Active-Precharge; tRC=tRC (min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; IDD0 Address and control inputs changing once every two clock cycles. 23(5$7,1*&855(17One bank; Active-Read-Precharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing IDD1 once per clock cycle 35(&+$5*(32:(5'2:167$1'%