128M DDR1 -AS4C8M16D1
Revision History
AS48Dϭϲ1 - 66-pin TSOPII PACKAGE
Revision
Rev 1.1
Rev.1.2
Date
Details
Preliminary datasheet
Add Part numbering system
Feb 2009
May 2015
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
-1/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
8M x 16 DDR Synchronous DRAM (SDRAM)
Released (Rev. 1.2, May /2015)
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Features
Overview
Fast clock rate: 200MHz
Differential Clock CK & CK input
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 2M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
4096 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge
& active power down
Power supplies: VDD & VDDQ = 2.5V 5%
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
The 128Mb DDR AS4C8M16D1 SDRAM is a
high-speed
CMOS
double
data
rate
synchronous DRAM containing 128 Mbits. It is
internally configured as a quad 2M x 16 DRAM
with a synchronous interface (all signals are
registered on the positive edge of the clock
signal, CK). Data outputs occur at both rising
edges of CK and CK.
Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected
location and continue for a programmed
number of locations in a programmed
sequence. Accesses begin with the registration
of a BankActivate command which is then
followed by a Read or Write command. The
DDR SDRAM provides programmable Read or
Write burst lengths of 2, 4, or 8. An auto
precharge function may be enabled to provide
a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy
to use. In addition, The DDR SDRAM features
programmable DLL option. By having a
programmable mode register and extended
mode register, the system can choose the
most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth
and high performance.
Table 1.Ordering Information
Part Number
AS4C8M16D1-TCN
AS4C8M16D1-5TIN
Org
Max Clock (MHz)
8M x 16
200
8M x 16
200
Temperature Temp Range
Commercial
0 ~ 70°C
Industrial
-40 ~ 85°C
Package
66pin TSOPII
66pin TSOPII
T: indicates TSOP II package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
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VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 2. Block Diagram
CK
CK
DLL
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
A10/AP
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
2M x 16
CELL ARRAY
(BANK #1)
Column Decoder
~
A9
A11
BA0
BA1
REFRESH
COUNTER
LDQS
UDQS
DATA
STROBE
BUFFER
DQ0
Row
Decoder
ADDRESS
BUFFER
A0
2M x 16
CELL ARRAY
(BANK #2)
Column Decoder
DQ
Buffer
Row
Decoder
~
DQ15
LDM
UDM
Confidential
2M x 16
CELL ARRAY
(BANK #0)
Column Decoder
Row
Decoder
CS
RAS
CAS
WE
Row
Decoder
CKE
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2M x 16
CELL ARRAY
(BANK #3)
Column Decoder
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Pin Descriptions
Table 2. Pin Details
Symbol
Type
Description
CK, CK
Input
Differential Clock: CK, CK are driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. Both CK and CK increment the internal burst counter
and controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
low synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains low. When
all banks are in the idle state, deactivating the clock controls the entry to the Power Down
and Self Refresh modes.
BA0, BA1
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A11
Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row address
A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto
Precharge).
CS
Input
Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS is sampled HIGH. CS provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS
Input
Row Address Strobe: The RAS signal defines the operation commands in conjunction
with the CAS and WE signals and is latched at the positive edges of CK. When RAS
and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE signal. When the WE is
asserted "HIGH," the BankActivate command is selected and the bank designated by BA
is turned on to the active state. When the WE is asserted "LOW," the Precharge
command is selected and the bank designated by BA is switched to the idle state after the
precharge operation.
CAS
Input
Column Address Strobe: The CAS signal defines the operation commands in
conjunction with the RAS and WE signals and is latched at the positive edges of CK.
When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by
asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE
"HIGH” or “LOW".
WE
Input
Write Enable: The WE signal defines the operation commands in conjunction with the
RAS and CAS signals and is latched at the positive edges of CK. The WE input is used
to select the BankActivate or Precharge command and Read or Write command.
LDQS,
Input /
UDQS
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe
is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.
LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15
Input /
Output
Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and
negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes.
VDD
Supply
Power Supply: +2.5V 5%
VSS
Supply
Ground
VDDQ
Supply
DQ Power: +2.5V 5%. Provide isolated power to DQs for improved noise immunity.
UDM
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VREF
Supply
Reference Voltage for Inputs: +0.5*VDDQ
NC
-
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No Connect: No internal connection, these pins suggest to be left unconnected.
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 4
shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
BankActivate
State
CKEn-1 CKEn DM BA0,1 A10 A0-9,11
Idle(3)
H
X
X
V
BankPrecharge
Any
H
X
X
V
L
PrechargeAll
Any
H
X
X
X
Write
Active(3)
H
X
X
Write and AutoPrecharge
Active(3)
H
X
Read
Active(3)
H
Read and Autoprecharge
Active(3)
Mode Register Set
RAS CAS
WE
L
L
H
H
X
L
L
H
L
H
X
L
L
H
L
V
L
L
H
L
L
X
V
H
Column
address
(A0 ~ A8)
L
H
L
L
X
X
V
L
L
H
L
H
H
X
X
V
H
Column
address
(A0 ~ A8)
L
H
L
H
Idle
H
X
X
OP code
L
L
L
L
Extended MRS
Idle
H
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
X
X
X
X
X
X
X
X
Burst Stop
Row address
CS
(SelfRefresh)
Precharge Power Down Mode Entry
Precharge Power Down Mode Exit
Idle
Any
H
L
L
H
X
X
X
X
X
X
X
X
(PowerDown)
Active Power Down Mode Entry
Active Power Down Mode Exit
Active
Any
H
L
L
H
X
X
X
X
X
X
X
X
(PowerDown)
Data Input Mask Disable
Active
H
X
L
X
X
X
Data Input Mask Enable(5)
Active
H
X
H
X
X
X
Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 2, 4, and 8 burst operation.
5. LDM and UDM can be enabled respectively.
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Mode Register Set (MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS
Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default
value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored
in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low
on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to
writing into the mode register, and CKE should be High). The state of address pins A0~A11 and BA0, BA1 in the
same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of
two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is
divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and
CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the
undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device
operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths,
burst types and CAS latencies.
Table 4. Mode Register Bitmap
BA1 BA0 A11 A10
0
A8
0
1
X
0
A9
0
A7 Test Mode
0 Normal mode
0
DLL Reset
1
Test mode
BA0 Mode
0
MRS
1 EMRS
A8
A7
T.M.
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A6
A5
A4
CAS Latency
A4 CAS Latency
0
Reserved
1
Reserved
0
2
3
1
Reserved
0
Reserved
1
2.5
0
Reserved
1
A3
BT
A2
A1
A0
Burst Length
A3 Burst Type
0 Sequential
1 Interleave
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Address Field
Mode Register
Burst Length
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4,
and 8.
Table 5. Burst Length
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential
Mode and Interleave Mode support burst length of 2, 4, and 8.
Table 6. Addressing Mode
A3
Addressing Mode
0
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 7. Burst Address ordering
Burst
Length
2
4
8
Start Address
A2
A1
A0
X
X
0
X
X
1
X
0
0
X
0
1
X
1
0
X
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Sequential
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying
the following formula must be programmed into this field.
tCAC(min) CAS Latency X tCK
Table 8. CAS Latency
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2 clocks
0
1
1
3 clocks
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5 clocks
1
1
1
Reserved
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 9. Test Mode
A8
A7
Test Mode
0
0
Normal mode
1
0
DLL Reset
1
Test mode
X
(BA0, BA1)
Table 10. MRS/EMRS
BA1
BA0
A11 ~ A0
RFU
0
MRS Cycle
RFU
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength.
The default value of the extended mode register is not defined, therefore must be written after power up for proper
operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE . The state of A0, A2
~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low.
The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A11
0
BA0
0
1
1
Mode
MRS
EMRS
Confidential
A10
A9
A8
A7
RFU must be set to “0”
A6
A5
A4
A3
A2
A1
A0
Address Field
DS1 RFU must be set to “0” DS0 DLL Extended Mode Register
A6 A1
Drive Strength
Comment
0
0
Full
0
1
Weak
1
0
RFU
Reserved For Future
1
1 Matched impedance Output driver matches impedance
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A0
0
1
DLL
Enable
Disable
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Table 12. Absolute Maximum Rating
Symbol
Item
VIN, VOUT
I/O Pins Voltage
VIN
VDD, VDDQ
TA
Rating
Unit
Note
- 0.5~VDDQ + 0.5
V
1,2
VREF and Inputs Voltage
- 1~3.6
V
1,2
Power Supply Voltage
- 1~3.6
V
1,2
Commercial
0~70
°C
1
Industrial
-40~85
°C
1
Ambient Temperature
-5
TSTG
Storage Temperature
- 55~150
°C
1
PD
Power Dissipation
1
W
1
IOS
Short Circuit Output Current
50
mA
1
Note1: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of
the devices
Note2: These voltages are relative to Vss
Table 13. Recommended D.C. Operating Conditions (TA = -40 ~ 85 C)
Parameter
Symbol
Min.
Max.
Unit
Note
Power Supply Voltage
VDD
2.375
2.625
V
1,2
Power Supply Voltage (for I/O Buffer)
VDDQ
2.375
2.625
V
1,2
Input Reference Voltage
VREF
0.49* VDDQ
0.51* VDDQ
V
Termination Voltage
VTT
VREF - 0.04
VREF + 0.04
V
Input High Voltage (DC)
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V
Input Low Voltage (DC)
VIL (DC)
-0.3
VREF - 0.15
V
Input Voltage Level, CK and CK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
II
-5
5
A
Input Leakage current
1,2
Output Leakage current
IOZ
-5
5
A
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2 mA
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA
Min.
Max.
Unit
2
4
pF
Table 14. Capacitance (VDD = 2.5V±5%, f = 1MHz, TA = 25 C)
Symbol
CIN1
Parameter
Input Capacitance (CK, CK )
CIN2
Input Capacitance (All other input-only pins)
2
4
pF
CI/O
DQ, DQS, DM Input/Output Capacitance
4
6
pF
Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Table 15. D.C. Characteristics (VDD = 2.5V 5%, TA = -40~85 C)
Parameter & Test Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC (min);
tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles.
OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4;
tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing
once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; tCK=tCK(min); CKE=LOW
IDLE STANDLY CURRENT : CKE = HIGH; CS =HIGH(DESELECT); All
banks idle; tCK=tCK(min); Address and control inputs changing once per
clock cycle; VIN=VREF for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; powerdown mode; CKE=LOW; tCK=tCK(min)
Symbol
-5
Max.
Unit
IDD0
120
mA
IDD1
140
mA
IDD2P
10
mA
IDD2N
50
mA
IDD3P
40
mA
80
mA
180
mA
180
mA
ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ;
IDD3N
tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per
clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle
OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst;
one bank active; Address and control inputs changing once per clock cycle; IDD4R
tCK=tCK(min); lout=0mA;50% of data changing on every transfer
OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous
Burst ;one bank active; address and control inputs changing once per clock
IDD4W
cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50%
of data changing on every transfer
AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min)
IDD5
200
mA
SELF REFRESH CURRENT: Self Refresh Mode ; CKE≦0.2V;tCK=tCK(min)
IDD6
4
mA
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min);
tCK=tCK(min); Address and control inputs change only during Active, READ ,
or WRITE command
IDD7
300
mA
Figure 3: Timing Waveform for IDD7 Measurement at 200 MHz CK Operation
CK
CK
COMMAND
tRCD
ACT
READ
AP
ACT
READ
AP
ACT
READ
AP
ACT
READ
AP
ACT
...pattern repeats...
ADDRESS
Bank 0
Row d
Bank 3
Col c
Bank 1
Row e
Bank 0
Col d
Bank 2
Row f
Bank 1
Col e
Bank 3
Row g
Bank 2
Col f
Bank 0
Row h
CL=3
DQS
DQ
Confidential
D0 a D0 a D0 a D0 a D0 b D0 b D0 b D0 b D0 c D0 c D0 c D0 c D0 d D0 d D0 d D0 d D0 e D0 e D0 e D0 e D0 f D0 f
-12/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Table 16. Electrical AC Characteristics (VDD = 2.5V 5%, TA = -40~85 C)
Symbol
-5
Parameter
tCK
Clock cycle time
tCH
tCL
Clock high level width
Clock low level width
CL=2
CL=2.5
CL = 3
tDQSCK DQS-out access time from CK, CK
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDQSH
tDQSL
Output access time from CK, CK
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
DQS-in setup time
DQS write preamble
DQS write postamble
DQS in high level pulse width
DQS in low level pulse width
tIS
Address and Control input setup time
tAC
Unit
Min
7.5
6
5
0.45
0.45
Max
12
12
12
0.55
0.55
-0.6
0.6
ns
-0.7
0.7
ns
0.4
1.1
0.6
1.25
0.6
70K
-
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
tCK
tCK
tIH
Address and Control input hold time
tDS
tDH
tHP
tQH
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tMRD
tCCD
tDAL
tXSRD
tPDEX
tREFI
tIPW
tDIPW
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Clock half period
DQ/DQS output hold time from DQS
Row cycle time
Refresh row cycle time
Row active time
Active to Read or Write delay
Row precharge time
Row active to Row active delay
Write recovery time
Mode register set cycle time
Col. Address to Col. Address delay
Auto precharge write recovery + Precharge time
Self refresh exit to read command delay
Power down exit time
Refresh interval time
Control and Address input pulse width
DQ & DM input pulse width (for each input)
0.9
0.4
0.72
0
0.25
0.4
0.35
0.35
0.6
0.7
0.6
0.7
0.4
0.4
tCLMIN or tCHMIN
tHP - tQHS
60
70
40
18
18
10
15
2
1
7
200
tCK + tIS
2.2
1.75
tHZ
Data-out high-impedance window from CK, CK
-
0.7
ns
tLZ
Data-out low-impedance window from CK, CK
-0.7
0.7
ns
tQHS
tDSS
tDSH
Data Hold Skew Factor
DQS falling edge to CK rising – setup time
DQS falling edge to CK rising – hold time
0.2
0.2
0.5
-
ns
tCK
tCK
Confidential
Fast slew rate
Slow slew rate
Fast slew rate
Slow slew rate
-13/65-
15.6
-
Rev.1.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
ns
s
ns
ns
May 2015
128M DDR1 -AS4C8M16D1
tWTR
tXSNR
tRAP
Internal Write to Read command delay
Exit Self-Refresh to non-Read command
Active to Autoprecharge delay
2
75
-
tRASmin
tCK
ns
ns
Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V 5%, TA = -40~85 C)
Parameter
Symbol
Min.
Max.
Unit
Input High Voltage (AC)
VIH (AC)
VREF + 0.35
-
V
Input Low Voltage (AC)
VIL (AC)
-
VREF – 0.35
V
Input Different Voltage, CK and CK inputs
VID (AC)
0.7
VDDQ + 0.6
V
Input Crossing Point Voltage, CK and CK inputs
VIX (AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
Note:
1. All voltages are referenced to VSS.
2. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of tCK and tRC. Input signals are changed one time during tCK.
3. Power-up sequence is described in Note 5.
4. A.C. Test Conditions
Table 18. SSTL _2 Interface
Reference Level of Output Signals (VREF)
0.5 * VDDQ
Output Load
Reference to the Test Load
Input Signal Levels(VIH / VIL)
VREF+0.35 V / VREF-0.35V
Input Signals Slew Rate
1 V/ns
Reference Level of Input Signals
0.5 * VDDQ
Figure 4. SSTL_2 A.C. Test Load
0.5 * VDDQ
50Ω
DQ, DQS
Z0=50Ω
Confidential
-14/65-
30pF
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
5. Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held
"NOP" state and maintain CKE “LOW”.
2) Start clock and maintain stable condition for minimum 200s.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
Confidential
-15/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Timing Waveforms
Figure 5. Activating a Specific Row in a Specific Bank
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
Address
RA
BA0,1
BA
RA=Row Address
BA=Bank Address
Don’t Care
Confidential
-16/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 6. tRCD and tRRD Definition
CK
CK
COMMAND
ACT
Address
Row
Row
Col
BA0,BA1
Bank A
Bank B
Bank B
NOP
NOP
ACT
tRRD
NOP
NOP
RD/WR
NOP
tRCD
Don’t Care
Figure 7. READ Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0 - A8
CA
EN AP
A10
DIS AP
BA0,1
BA
CA=Column Address
BA=Bank Address
EN AP=Enable Autoprecharge
DIS AP=Disable Autoprecharge
Don’t Care
Confidential
-17/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 8. Read Burst Required CAS Latencies (CL=2)
CK
CK
COMMAND
READ
ADDRESS
Bank A,
Col n
NOP
NOP
NOP
NOP
NOP
CL=2
DQS
DO
n
DQ
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order
following DO n
Don’t Care
Read Burst Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
READ
ADDRESS
Bank A,
Col n
NOP
NOP
NOP
NOP
NOP
CL=2.5
DQS
DO
n
DQ
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Confidential
-18/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Read Burst Required CAS Latencies (CL=3)
CK
CK
COMMAND
READ
ADDRESS
Bank A,
Col n
NOP
NOP
NOP
NOP
NOP
CL=3
DQS
DO
n
DQ
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Confidential
-19/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 9. Consecutive Read Bursts Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
Confidential
-20/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Consecutive Read Bursts Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2.5
DQS
DO
n
DQ
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
Confidential
-21/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Consecutive Read Bursts Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
Bank,
Col n
READ
NOP
NOP
NOP
Bank,
Col o
CL=3
DQS
DO
n
DQ
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
Confidential
-22/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 10. Non-Consecutive Read Bursts Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2
DQS
DO
n
DQ
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Non-Consecutive Read Bursts Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2.5
DQS
DO
n
DQ
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Confidential
-23/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Non-Consecutive Read Bursts Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=3
DQS
DO
n
DQ
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Confidential
-24/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 11. Random Read Accesses Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
Bank,
Col n
Bank,
Col o
Bank,
Col p
Bank,
Col q
NOP
NOP
CL=2
DQS
DQ
DO
n
DO
n'
DO
o
DO
o'
DO
p
DO
p'
DO
q
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Confidential
-25/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Random Read Accesses Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
Bank,
Col n
Bank,
Col o
Bank,
Col p
Bank,
Col q
NOP
NOP
CL=2.5
DQS
DO
n
DQ
DO
n'
DO
o
DO
o'
DO
p
DO
p'
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Confidential
-26/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Random Read Accesses Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
Bank,
Col n
Bank,
Col o
Bank,
Col p
Bank,
Col q
NOP
NOP
CL=3
DQS
DO
n
DQ
DO
n'
DO
o
DO
o'
DO
p
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Confidential
-27/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 12. Terminating a Read Burst Required CAS Latencies (CL=2)
CK
CK
COMMAND
READ
ADDRESS
Bank A,
Col n
NOP
BST
NOP
NOP
NOP
CL=2
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Confidential
-28/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Terminating a Read Burst Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
READ
ADDRESS
Bank A,
Col n
NOP
BST
NOP
NOP
NOP
CL=2.5
DQS
DO
n
DQ
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Confidential
-29/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Terminating a Read Burst Required CAS Latencies (CL=3)
CK
CK
COMMAND
READ
ADDRESS
Bank A,
Col n
NOP
BST
NOP
NOP
NOP
CL=3
DQS
DO
n
DQ
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Confidential
-30/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 13. Read to Write Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
BST
NOP
NOP
WRITE
NOP
Bank,
Col o
Bank,
Col n
tDQSS
min
CL=2
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
-31/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Read to Write Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
BST
NOP
NOP
NOP
WRITE
Bank,
Col o
Bank,
Col n
tDQSS
min
CL=2.5
DQS
DO
n
DQ
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
-32/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Read to Write Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
BST
NOP
NOP
NOP
WRITE
Bank,
Col o
Bank,
Col n
tDQSS
min
CL=3
DQS
DO
n
DQ
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
-33/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 14. Read to Precharge Required CAS Latencies (CL=2)
CK
CK
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=2
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
-34/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Read to Precharge Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=2.5
DQS
DO
n
DQ
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
-35/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Read to Precharge Required CAS Latencies (CL=3)
CK
CK
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=3
DQS
DO
n
DQ
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
-36/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 15. Write Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0 - A8
CA
EN AP
A10
DIS AP
BA0,1
BA
CA=Column Address
BA=Bank Address
EN AP=Enable Autoprecharge
DIS AP=Disable Autoprecharge
Don’t Care
Confidential
-37/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 16. Write Max DQSS
CK
T0
T1
T2
T3
T4
T5
T6
T7
CK
COMMAND
WRITE
ADDRESS
Bank A,
Col n
NOP
NOP
NOP
tDQSS
max
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data In are applied in the programmed
order following DI n
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE
disabled)
Don’t Care
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-38/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 17. Write Min DQSS
CK
T0
T1
T2
T3
T4
T5
T6
CK
COMMAND
ADDRESS
NOP
WRITE
NOP
NOP
Bank A,
Col n
tDQSS
min
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data In are applied in the programmed
order following DI n
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE disabled)
Don’t Care
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-39/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 18. Write Burst Nom, Min, and Max tDQSS
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
COMMAND
ADDRESS
NOP
WRITE
NOP
NOP
NOP
NOP
Bank ,
Col n
tDQSS (nom)
DQS
DI
n
DQ
DM
tDQSS (min)
DQS
DQ
DI
n
DM
tDQSS (max)
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data are applied in the programmed order following DI n
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE disabled)
DM=UDM & LDM
Don’t Care
Confidential
-40/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 19. Write to Write Max tDQSS
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
COMMAND
ADDRESS
WRITE
NOP
WRITE
NOP
NOP
NOP
Bank ,
Col o
Bank ,
Col n
tDQSS (max)
DQS
DQ
DI
n
DI
o
DM
DI n , etc. = Data In for column n,etc.
3 subsequent elements of Data In are applied in the programmed order following DI n
3 subsequent elements of Data In are applied in the programmed order following DI o
Non-interrupted bursts of 4 are shown
DM= UDM & LDM
Don’t Care
Confidential
-41/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 20. Write to Write Max tDQSS, Non Consecutive
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
Bank
Col n
WRITE
NOP
NOP
Bank
Col o
tDQSS (max)
DQS
DQ
DI
n
DI
o
DM
DI n, etc. = Data In for column n, etc.
3 subsequent elements of Data In are applied in the programmed order following DI n
3 subsequent elements of Data In are applied in the programmed order following DI o
Non-interrupted bursts of 4 are shown
DM= UDM & LDM
Don’t Care
Confidential
-42/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 21. Random Write Cycles Max tDQSS
CK
T0
T1
T2
T4
T3
T5
T6
T8
T7
T9
CK
COMMAND
ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
Bank
Col n
Bank
Col o
Bank
Col p
Bank
Col q
Bank
Col r
tDQSS (max)
DQS
DQ
DI
n
DI
n'
DI
o
DI
o'
DI
p
DI
p'
DI
q
DI
q'
DM
DI n, etc. = Data In for column n, etc.
n', etc. = the next Data In following DI n, etc. according to the programmed burst order
Programmed Burst Length 2, 4, or 8 in cases shown
If burst of 4 or 8, the burst would be truncated
Each WRITE command may be to any bank and may be to the same or different devices
DM= UDM & LDM
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 22. Write to Read Max tDQSS Non Interrupting
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
NOP
tWTR
ADDRESS
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DI
n
DQ
DM
DI n, etc. = Data In for column n, etc.
1 subsequent elements of Data In are applied in the programmed order following DI n
A non-interrupted burst of 2 is shown
tWTR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
DM= UDM & LDM
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 23. Write to Read Max tDQSS Interrupting
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DI
n
DQ
DM
DI n, etc. = Data In for column n, etc.
1 subsequent elements of Data In are applied in the programmed order following DI n
An interrupted burst of 8 is shown, 2 data elements are written
tWTR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
DM= UDM & LDM
Don’t Care
Confidential
-45/65-
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 24. Write to Read Max tDQSS, ODD Number of Data, Interrupting
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
COMMAND
WRITE
NOP
NOP
NOP
READ
NOP
tWTR
ADDRESS
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DI
n
DQ
DM
DI n = Data In for column n
An interrupted burst of 8 is shown, 1 data elements are written
tWTR is referenced from the first positive CK edge after the last Data In Pair (not the last desired
Data In element)
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
DM= UDM & LDM
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 25. Write to Precharge Max tDQSS, NON- Interrupting
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
COMMAND
WRITE
ADDRESS
Bank a,
Col n
NOP
NOP
NOP
NOP
PRE
tWR
Bank
(a or al)
tRP
tDQSS (max)
DQS
DQ
DI
n
DM
DI n = Data In for column n
1 subsequent elements of Data In are applied in the programmed order following DI n
A non-interrupted burst of 2 is shown
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
DM= UDM & LDM
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 26. Write to Precharge Max tDQSS, Interrupting
CK
T0
T1
T2
T3
T4
T5
T6
T8
T7
T9
T10
T11
CK
COMMAND
WRITE
NOP
NOP
NOP
PRE
NOP
tWR
ADDRESS
Bank a,
Col n
Bank
(a or all)
tDQSS (max)
tRP
*2
DQS
DI
n
DQ
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 2 data elements are written
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
DM= UDM & LDM
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 27. Write to Precharge Max tDQSS, ODD Number of Data Interrupting
CK
T0
T1
T2
T3
T4
T5
T6
T8
T7
T9
T10
T11
CK
COMMAND
WRITE
NOP
NOP
NOP
NOP
PRE
tWR
ADDRESS
Bank a,
Col n
Bank
(a or all)
tDQSS (max)
tRP
*2
DQS
DQ
DI
n
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 1 data element is written
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
DM= UDM & LDM
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 28. Precharge Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A9, A11
ALL BANKS
A10
ONE BANK
BA0,1
BA
BA= Bank Address (if A10 is
LOW, otherwise don't care)
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 29. Power-Down
T0
T1
T2
T4
T3
Tn
Tn+3 Tn+4 Tn+5 Tn+6
Tn+1 Tn+2
CK
CK
tIS
tIS
CKE
COMMAND
NOP
NOP
VALID
Exit power-down
mode
Enter power-down
mode
No column access
in progress
VALID
Don’t Care
Figure 30. Clock Frequency Change in Precharge
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
CK
CK
CMD
CKE
NOP
NOP
NOP
Frequency Change
Occurs here
tRP
Confidential
-51/65-
NOP
NOP
Valid
tIS
Stable new clock
Before power down
exit
Minmum 2 clocks
Required before
Changing frequency
DLL
RESET
200 Clocks
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 31. Data input (Write) Timing
tDQSH
tDQSL
DQS
tDS
DQ
tDH
tDS
DI
n
DM
tDH
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order
following DI n
Don’t Care
Figure 32. Data Output (Read) Timing
tCH
tCL
CK
CK
DQS
DQ
tDQSQ
max
tDQSQ
tQH
max
tQH
Burst Length = 4 in the case shown
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 33. Initialize and Mode Register Sets
VDD
VDDQ
tVDT>=0
VTT
(system*)
tCK
tCH tCL
VREF
CK
CK
tIS tIH
CKE
LVCMOS LOW LEVEL
tIS tIH
NOP
COMMAND
PRE
MRS
EMRS
PRE
AR
AR
MRS
ACT
CODE
RA
CODE
RA
BA0=L
BA1=L
BA
DM
tIS tIH
A0-A9,
A11
CODE
ALL BANKS
A10
tIS tIH
CODE
tIS tIH
ALL BANKS
CODE
CODE
tIS tIH
tIS tIH
BA0=H
BA1=L
BA0,BA1
BA0=L
BA1=L
High-Z
DQS
High-Z
DQ
T=200µs
**tMRD
**tMRD
Extended mode
Register set
Power-up:
VDD and
CLK stable
tRP
tRFC
tRFC
**tMRD
200 cycles of CK**
Load Mode
Register,
Reset DLL (with A8=H)
Load Mode
Register,
(with A8=L)
Don’t Care
*=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable
command can be applied the two auto Refresh commands may be moved to follow the first MRS but precede the second
PRECHARGE ALL command.
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 34. Power Down Mode
tCK
tCH
tCL
CK
CK
tIS tIH
CKE
tIS
tIS
tIS tIH
COMMAND
VALID*
NOP
NOP
VALID
tIS tIH
ADDR
VALID
VALID
DQS
DQ
DM
Enter
power-down mode
Exit
power-down mode
No column accesses are allowed to be in progress at the time Power-Down is entered
*=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down
mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active)
then the Power-Down mode shown is active Power Down.
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 35. Auto Refresh Mode
tCK
tCH tCL
CK
CK
tIS tIH
CKE
VALID
VALID
tIS tIH
COMMAND
NOP
PRE
NOP
NOP
AR
NOP
AR
NOP
NOP
ACT
A0-A8
RA
A9,A11
RA
ALL BANKS
RA
A10
ONE BANKS
tIS
BA0,BA1
tIH
BA
*Bank(s)
DQS
DQ
DM
tRP
tRFC
tRFC
* = “Don't Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks)
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC
DM, DQ and DQS signals are all “Don't Care”/High-Z for operations shown
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 36. Self Refresh Mode
tCK
tCH
CK
Clock must be stable before
Exiting Self Refresh mode
tCL
CK
tIS tIH
CKE
tIS
tIS
tIS tIH
COMMAND
NOP
NOP
AR
VALID
tIS tIH
VALID
ADDR
DQS
DQ
DM
tRP*
tXSNR/
tXSRD**
Enter Self Refresh
mode
Exit Self Refresh
mode
* = Device must be in the “All banks idle” state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is
required before a READ command can be applied.
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 37. Read without Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS tIH
CKE
VALID
VALID
VALID
NOP
NOP
NOP
tIS tIH
NOP
COMMAND
READ
PRE
NOP
NOP
NOP
ACT
tIS tIH
Col n
A0-A8
RA
RA
A9,A11
tIS
tIH
ALL BANKS
RA
A10
DIS AP
ONE BANKS
tIS tIH
Bank X
BA0,BA1
Bank X
*Bank X
CL=3
tRP
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
min
tRPRE
tRPST
DQS
tLZ
min
DQ
DO
n
tLZ
tAC
min
Case 2:
tAC/tDQSCK=max
min
tDQSCK
max
tRPRE
tRPST
DQS
tLZ
max
DQ
tLZ
tHZ
max
DO
n
max
tAC
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* =“Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Don’t Care
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 38. Read with Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS tIH
CKE
VALID
VALID
VALID
NOP
NOP
NOP
tIS tIH
NOP
COMMAND
READ
NOP
NOP
NOP
NOP
ACT
tIS tIH
Col n
A0-A8
RA
RA
A9,A11
EN AP
RA
A10
tIS tIH
tIS tIH
Bank X
BA0,BA1
Bank X
CL=3
tRP
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
min
tRPRE
DQS
tRPST
tLZ
min
DO
n
DQ
tLZ
tAC
min
min
Case 2:
tAC/tDQSCK=max
tDQSCK
max
tRPRE
tRPST
DQS
tLZ
max
DQ
tHZ
max
DO
n
tLZ
max
tAC
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
The READ command may not be issued until tRAP has been satisfied. If Fast Autoprecharge is supported, tRAP = tRCD, else the READ
may not be issued prior to tRASmin – (BL*tCK/2)
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 39. Bank Read Access
tCK
tCH tCL
CK
CK
tIS tIH
CKE
tIS tIH
NOP
COMMAND
ACT
NOP
NOP
NOP
READ
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A8
RA
A9,A11
RA
Col n
RA
tIS
A10
RA
tIH
ALL BANKS
RA
RA
tIS tIH
Bank X
BA0,BA1
DIS AP
ONE BANKS
Bank X
*Bank X
Bank X
tRC
tRAS
tRCD
tRP
CL=3
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
min
tRPRE
DQS
tLZ
DO
n
min
DQ
tLZ
tAC
tDQSCK
min
Case 2:
tAC/tDQSCK=max
tRPST
min
max
tRPRE
tRPST
DQS
tHZ
tLZ
max
max
DQ
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DO
n
tLZ
max
tAC
max
DIS AP = Disable Autoprecharge
* = ”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS
would be limiting)
Confidential
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Don’t Care
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 40. Write without Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS tIH
CKE
VALID
tIS tIH
COMMAND
NOP
NOP
NOP
NOP
WRITE
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A8
RA
Col n
RA
A9,A11
tIS tIH
ALL BANKS
RA
A10
ONE BANKS
DIS AP
tIS tIH
BA0,BA1
Bank X
Case 1:
tDQSS=min
tDQSS
BA
*Bank X
tDSH
tDQSH
tRP
tDSH
tWR
tWPST
DQS
tDQSL
tWPRES
tWPRE
DI
n
DQ
DM
tDSS
Case 2:
tDQSS=max
tDQSS
tDQSH
tDSS
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the +
25% window of the corresponding positive clock edge
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
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Don’t Care
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 41. Write with Auto Precharge
tCK
tCH tCL
CK
CK
tIS tIH
CKE
VALID
VALID
VALID
NOP
NOP
NOP
tIS tIH
COMMAND
NOP
NOP
NOP
NOP
WRITE
NOP
ACT
tIS tIH
A0-A8
RA
Col n
RA
A9,A11
DIS AP
RA
A10
tIS tIH
BA0,BA1
Bank X
BA
tDAL
Case 1:
tDQSS=min
tDQSS
tDSH
tDQSH
tDSH
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
Case 2:
tDQSS=max
tDQSS
tDSS
tDQSH
tDSS
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DI n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Confidential
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Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 42. Bank Write Access
tCK
tCH tCL
CK
CK
tIS tIH
CKE
tIS tIH
NOP
COMMAND
ACT
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
PRE
tIS tIH
A0-A8
RA
A9,A11
RA
A10
RA
Col n
tIS tIH
Bank X
BA0,BA1
tIS tIH
ALL BANKS
DIS AP
ONE BANK
Bank X
*Bank X
tRAS
tRCD
Case 1:
tDQSS=min
tWR
tDQSS
tDSH
tDQSH
tDSH
tWPST
DQS
tWPRES
tWPRE
tDQSL
DI
n
DQ
DM
tDSS
Case 2:
tDQSS=max
tDQSS
tDQSH
tDSS
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
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Don’t Care
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 43. Write DM Operation
tCK
tCH tCL
CK
CK
tIS tIH
CKE
VALID
tIS tIH
COMMAND
NOP
NOP
NOP
NOP
WRITE
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A8
RA
Col n
RA
A9,A11
tIS
tIH
ALL BANKS
RA
A10
ONE BANKS
DIS AP
tIS tIH
BA0,BA1
Bank X
Case 1:
tDQSS=min
tDQSS
BA
*Bank X
tDSH
tDQSH
tRP
tDSH
tWR
tWPST
DQS
tDQSL
tWPRES
tWPRE
DI
n
DQ
DM
tDSS
Case 2:
tDQSS=max
tDQSS
tDSS
tDQSH
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
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Don’t Care
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
Figure 44. 66 Pin TSOP II Package Outline Drawing Information:
Units: mm
D
D
C
A2
L
HE
E
L1
C
A
θ
A1
b
e
S
F
(TYP)
Symbol
A
A1
A2
b
e
C
D
E
HE
L
L1
F
θ
S
D
y
Confidential
Dimension in mm
Min
Nom
Max
--0.05
0.9
0.22
--0.095
22.09
10.03
11.56
0.40
----0°
-----
----1.0
--0.65
0.125
22.22
10.16
11.76
0.5
0.8
0.25
--0.71
---
1.2
0.2
1.1
0.45
--0.21
22.35
10.29
11.96
0.6
----8°
--0.10
Dimension in inch
Min
Nom
Max
--0.002
0.035
0.009
--0.004
0.87
0.395
0.455
0.016
----0°
-----
----0.039
--0.026
0.005
0.875
0.4
0.463
0.02
0.032
0.01
--0.028
---
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0.047
0.008
0.043
0.018
--0.008
0.88
0.405
0.471
0.024
----8°
--0.004
Rev.1.2
May 2015
128M DDR1 -AS4C8M16D1
PART NUMBERING SYSTEM
AS4C
8M16D1
5
T
DRAM
8M16 = 8Mx16
D1=DDR1
5=200MHz
T = TSOPII
C/I
C=Commercial
(0¡ C70¡ C)
I=Industrial
(-40¡ C85¡ C)
N
Indicates Pb and
Halogen Free
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such
use and agrees to indemnify Alliance against all claims arising from such use.
Confidential
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May 2015
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