AS4C8M16MSA-6BINTR

AS4C8M16MSA-6BIN Revision History 128M (8M x 16) /RZ3RZHU6'5$0 AS4C801606$ 54ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Dec. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN 128M(8Mx16) Low Power SDRAM Features - Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8 or full page - 64ms refresh period (4K cycle) - JEDEC Compatibility - Low Power Features - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 54ball FBGA with 0.8mm ball pitch - AS4C8M16MSA : Pb-Free & Halogen Free Functional Description The AS4C8M16MSA Family is high-performance CMOS Dynamic RAMs (DRAM) organized as 8M x 16. These devices feature advanced circuit design to provide low active current and extremely low standby current. T he d evi c e i s c om pat i bl e wi t h t h e J E DE C s t a n da rd LP-SDRAM specifications. Table I.Ordering Information Product part No Org AS4C8M16MSA-6BIN 8M x 16 Temperature Max Clock (MHz) Package 166 54-ball FBGA Industrial -40°C to 85°C Table II.Key Specifications tCK(3) tAC(3) tRAS tRC Confidential AS4C8M16MSA-6BIN Clock Cycle time(min.) Access time from CLK (max.) Row Active time(min.) Row Cycle time(min.) - 2 of 46 - -6 6ns 5.5ns 48 ns 60ns Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Logic Block Diagram CKE CLK /CS /WE /CAS /RAS Control Logic Refresh Counter Bank 0 Row Address Latch/ Decoder Row Address Mux Mode Register Extended Mode Register Bank 3 Bank 2 Bank 1 Bank 0 Memory Array LDQM UDQM Data Output Register 8Kx4K Sense Amp Bank Control Logic A0-A11 BA0-BA1 Write Drivers DQM Mask DQ0 DQ15 Address Register Column Decoder Data Input Register Column Address Latch Pin Configuration 54 ball 0.8mm pitch FBGA (8mm x 8mm) Top View Confidential 1 2 3 A VSS DQ15 VSSQ B DQ14 DQ13 C DQ12 D 4 5 7 8 9 VDDQ DQ0 VDD VDDQ VSSQ DQ2 DQ1 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE /CAS /RAS /WE G NC A11 A9 BA0 BA1 /CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD - 3 of 46 - 6 Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Pin Description Symbol Type CLK Input Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF Refresh operation(all banks idle), ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. /CS Input Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. /CAS, /RAS, /WE Input Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered. LDQM, UDQM Input Input/Output Mask: L(U)DQM is sampled HIGH and is an input mask signal for write accesses and an output disable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0 – DQ7 and UDQM corresponds to DQ8–DQ15. BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. A0-A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. DQ I/O NC - VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VDD Supply Power Supply: Voltage dependant on option. VSS Supply Ground. Confidential Description Data Input/Output : Data bus No Connect - 4 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN FUNCTIONAL DESCRIPTION Initialization The Alliance Memory 128Mb SDRAM is a quad-bank DRAM that operates at 1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK ). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM must be initialized prior to normal operation. The following sections provide detailed information regarding device initialization, register definition, command descriptions and device operation. SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable (meets the clock specifications in the AC characteristics), the SDRAM requires a 200µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. The COMMAND INHIBIT or NOP should be applied at least once during the 200µs delay. After the 200µs delay, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Refer Figure 1. Confidential - 5 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Figure 1. Initialize and Load Mode Register[1.2.3.] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE /CS /RAS /CAS Key ADDR Key RA BA0 BA BA1 BA A10/AP RA HiZ DQ HiZ /WE DQM tRP Precharge (All Bank) tRFC Auto Refresh tRFC Auto Refresh Normal MRS Extended MRS Row Active a Bank Note : 1. The two AUTO REFRESH commands at T4 and T9 may be applied before either LOAD MODE REGISTER (LMR) command. 2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address 3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order; However, all must occur prior to an Active command. Register Definition There are two mode registers which contain settings to achieve low power consumption. The two registers : Mode Register and Extended Mode Register are discussed below. Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Table 1. The mode register is programmed via the LOAD MODE REGIS- TER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of Confidential burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the width burst mode, M10, M11, M12, M13 and M14 should be set to zero. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented. The burst length is programmable, as shown in Table 2. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1,2, 4, or 8 locations are available for both the - 6 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 when the burst length is set to two; by A2-A8 when the burst length is set to four; and by A3-A8 when the burst length is set to eight. The remaining(least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type The burst type can be set to either Sequential or Interleaved by using the M3 bit in the Mode register. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 2. [4.5.6.7.8.9.10.] Table 1. Mode Register Definition. M13BA1 M12BA0 M11A11 M10A10 M9-A9 Reserved(Set to ‘0’) WB M8-A8 M7-A7 M6-A6 Op Mode M5-A5 M4-A4 CAS Latency BT Burst Length M3 M2 M1 M0 M3=0 M3=1 000 1 1 001 2 2 010 4 4 011 8 8 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 111 Full Page Reserved M3-A3 M2-A2 M1-A1 M0-A0 Burst Length Burst Type 0 Sequential 1 Interleaved M9 Write Burst Mode 0 Prog. Burst Length 1 Single Mode Access M6 M5 M4 CAS Latency M8 M7 M6-M0 Operating Mode 000 Reserved 0 0 Defined Standard Operation 001 1 - - - All other states reserved 010 2 011 3 100 Reserved 101 Reserved 110 Reserved 111 Reserved Note : 4. For full-page accesses: y = 512 5. For a burst length of two, A1-A8 select the block-of-two burst; A0 selects the starting column within the block. 6. For a burst length of four, A2-A8 select the block-of-four burst; A0-A1 select the starting column within the block. 7. For a burst length of eight, A3-A8 select the block-of-eight burst; A0-A2 select the starting column within the block. 8. For a full-page burst, the full row is selected and A0-A8 select the starting column. 9. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 10. For a burst length of one, A0-A8 select the unique column to be accessed, and mode register bit M3 is ignored. Confidential - 7 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 2. Burst Length Definition. Order of Accesses within a Burst Burst Length Starting Column Address Type=Sequential Type=Interleaved 0 0-1 0-1 1 1-0 1-0 00 0-1-2-3 0-1-2-3 01 1-2-3-0 1-0-3-2 10 2-3-0-1 2-3-0-1 11 3-0-1-2 3-2-1-0 000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 n=A0-A8(location 0-y) Bn, Bn+1, Bn+2…..Bn,… Not supported A0 2 A1 A0 4 A2 A1 A0 8 Full Page(y) Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes.Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge r, and the latency is q clocks, the data will be available by clock edge r + q. The DQs will start driving as a result of the clock edge one cycle earlier (r + q- 1), and provided that the relevant access times are met, the data will be valid by clock edge r + q. Confidential For exam ple, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 3 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Write Burst Mode When M9=0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9=1, the programmed burst length applies to READ bursts, but write accesses are single-location (non-burst) accesses. - 8 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 CLK Command Read NOP tLZ tOH DQ Dout tAC CAS Latency=1 T0 T1 T2 T3 Read NOP NOP CLK Command tLZ tOH Dout DQ tAC CAS Latency=2 T0 T1 T2 T3 T4 CLK Command Read NOP NOP NOP tLZ tOH DQ Dout tAC CAS Latency=3 Figure 2. CAS Latency Confidential - 9 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 3. CAS Latency. Allowable Operating Frequency (MHz) Speed CAS Latency = 1 CAS Latency = 2 CAS Latency = 3 166MHz  50  83  166 100MHz  40  83  100 EXTENDED MODE REGISTER The Extended Mode Register controls additional functions such as Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed via the Mode Register Set command (BA1=1, BA0=0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with M7 through M12 set to “0”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time initiating any subsequent operation. Violating either of these requirements results in unspecified operation. PARTIAL ARRAY SELF REFRESH The Partial Array Self Refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during SELF REFRESH. The data in the deselected bank will be lost. Driver Strength Control AUTO TEMPERATURE COMPENSATED SELF REFRESH The driver strength feature allows one to reduce the drive strength of the I/O’s on the device during low frequency operation. This allows systems to reduce the noise associated with the I/O’s switching. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. In order to save power consumption, according to the temperature, Mobile-SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically. Table 4. Extended Mode Register Definition EM13BA1 EM12BA0 1 0 Confidential EM11A11 EM10A10 EM9A9 All must be set to ‘0’ EM8A8 EM7A7 EM6A6 EM5A5 Driver Strength - 10 of 46 - EM4A4 EM3A3 0 0 EM2A2 EM1A1 EM0A0 PASR Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 5. Extended Mode Register Table[11.12.]. A2 A1 A0 Self Refresh Coverage A7 A6 A5 Driver Strength 0 0 0 All Banks 0 0 0 100% 0 0 1 Half of Total Bank(BA1=0) 0 0 1 50% 0 1 0 Quarter of Total Bank(BA1=BA0=0) 0 1 0 25% 0 1 1 RFU 0 1 1 12.5% 1 0 0 RFU 1 0 0 75% 1 One Eighth of Total Bank (BA1=BA0=Row Address MSB=0 ) 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 1 0 1 1 0 One Sixteenth of Total Bank (BA1=BA0=Row Address MSB=0) 1 1 1 RFU Note : 11. 12. EM14 and EM13 (BA1 and BA0) must be “1, 0” to select the Extended Mode Register(vs. the base Mode Register). RFU: Reserved for Future Use Table 6. Commands[13.14.15.16.17.18.19.20.] . CKE /CS /RAS /CAS /WE DQM ADDR DQ COMMAND INHIBIT(NOP) X H X X X X X X NO OPERATION(NOP) H L H H H X X X X Name(Function) ACTIVE(Select bank and activate row)[14] H L L H H X Bank/ Row READ(Select bank and column, and start READ burst)[15] H L H L H L/H[20] Bank/ Col X WRITE(Select bank and column, and start WRITE burst)[15] H L H L L L/H[20] Bank/ Col Valid BURST TERMINATE H L H H L X X Active H L L H L X Code X H L L L H X X X PRECHARGE(Deactivate row in bank or banks)[16] AUTO REFRESH or SELF REFRESH(Enter Self Refresh LOAD MODE REGISTER[19] Mode)[17. 18] H L L L L X Opcode X Write Enable/Output Enable[20] H - - - - L - Active Write Inhibit/Output High-Z[20] H - - - - H Deep Power Down(Enter DPD Mode) L L H H L X Confidential - 11 of 46 - High Z X X Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Note : 13. CKE is HIGH for all commands shown except SELF REFRESH and Deep Power Down. 14. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 15. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 16. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 17. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 18. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 19. A0-A9 define the op-code written to the mode register and BA0, BA1 determine Normal MRS and Extended MRS. 20. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). LDQM controls DQ0-7 and UDQM controls DQ8-15. Commands Table 6. provides a reference of all the commands available with the state of the control signals for executing a specific command. COMMAND INHIBIT The COMMAND INHIBIT function effectively deselects the SDRAM by preventing new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (/CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0-A11, BA0, BA1. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. Table 1, Table 4 And Table 5 provide the definition for the Mode Register and Extended Mode Register. ACTIVE The ACTIVE command is used to activate a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. Confidential WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the active row in a particular bank or the active row in all banks. The bank(s) will be available for a subsequent row access after a specified time (tRP) from the issued PRECHARGE command. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE AUTO PRECHARGE is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. AUTO PRECHARGE thus performs the same PRECHARGE command described above , without requiring an explicit command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE does not apply in the full page mode burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. - 12 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command. The addressing is generated by the internal refresh controller. The address bits thus are a “Don’t Care” during an AUTO REFRESH command. The Alliance Memory 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC*2), once every 64ms. DEEP POWER DOWN Deep Power Down Mode is an operating mode to achieve extreme power reduction by cutting the power of the whole memory array of the device. Data will not be retained once the device enters DPD Mode. Full initialization is required when the device exits from DPD Mode. [Figure 29.30] SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM( without external clocking), even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (meet the clock specifications in the AC characteristics) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize he row refresh counter. Confidential - 13 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Maximum Ratings Voltage on VDD/VDDQ Supply Relative to VSS …….…….………………………...-0.5V to + 3.6V Voltage on Inputs, NC or I/O Pins Relative to VSS …….…….…………………….…. –0.5V to +3.6V Storage Temperature(plastic) ………….………. -55℃ to + 150℃ Power Dissipation ………………………….….………………1W *Stresses greater than those listed under “Maximum Ratings” may cause permanent damage to the device.This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Device AS4C8M16MSA Range Ambient Temperature VDD VDDQ Industrial -40℃ to +85℃ 1.7V to 1.95V 1.7V to VDD DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS [21.22.] Parameter / Condition Symbol Min Max Units Supply Voltage VDD 1.7 1.95 V I/O Supply Voltage VDDQ 1.7 VDD V VIH 0.8* VDDQ VDDQ +0.3 V VIL -0.3 0.2*VDDQ V Data Output High Voltage : Logic 1 : All Inputs(-0.1mA) VOH 0.9* VDDQ Data Output Low Voltage : Logic 0 : All Inputs(0.1mA) VOL Input High Voltage : Logic 1 All Inputs Input Low Voltage : Logic 0 All Inputs [23.] [23.] V 0.1*VDDQ V Input Leakage Current : Any Input 0V=VIN=VDD (All other pins not under test=0V) II -5 5 ㎂ Output Leakage Current : DQs are disabled ; 0V= VOUT=VDDQ lOZ -5 5 ㎂ Table 7. AC OPERATING CONDITIONS[21.22.23.24.25.26.] Parameter / Condition Symbol Value Units Input High Voltage : Logic 1 All Inputs VIH 0.8* VDDQ V Input Low Voltage : Logic 0 All Inputs VIL 0.2* VDDQ V 0.5*VDDQ V Input and Output Measurement Reference Level Confidential - 14 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 8. IDD Specifications and Conditions [21.22.26.27.]. Parameter -6 Units Operating Current: Active Mode; Burst =2 ; Read or Write ; t RC  tRC(min); CAS Latency =3 [28.29.30.] 50 ㎃ IDD2P Precharge Standby Current in power down mode : CKE  VIL(max) 0.2 ㎃ IDD2N Precharge Standby Current in non power down mode : CKE  VIH(min), /CS  VIH(min) [28.29.30,31.] 15 ㎃ IDD3P Active Standby Current in power down mode; CKE  VIL(max) [28.29,30.31.] 2 ㎃ IDD3N Active Standby Current in non power down mode (One Bank Active); CKE  VIH(min), /CS  VIH(min) [28.29,30.31.] 20 ㎃ IDD4 Operating Current: Burst Mode: Continuous Burst ; Read or Write : All banks Active, CAS Latency =3[28.29.30.] 75 ㎃ IDD5 Auto Refresh Current : tRFC  tRFC(138ns) 100 ㎃ Self Refresh Current : CKE  0.2V, 4 Banks, tCLK= ∞, 85°C 250 ㎂ Self Refresh Current : CKE  0.2V, 2 Banks , tCLK= ∞, 85°C 200 ㎂ Self Refresh Current : CKE  0.2V, 1 Banks, tCLK= ∞, 85°C 180 ㎂ Deep power down, tCLK= ∞ 10 ㎂ IDD1 IDD6 IDD7 Description Note : 21. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C ≤ TA ≤ +85°C for IT parts) is ensured. 22. An initial pause of 200µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the t REF refresh requirement is exceeded. 23. All states and sequences not shown are illegal or reserved. 24. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between VIL and VIH) in a monotonic manner. 25. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to V OH or VOL. The last valid data element will meet t OH before going High-Z. 26. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than t T (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point. 27. IDD specifications are tested after the device is properly initialized. 28. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 29. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 30. Input signals are changed one time during 20ns. 31. Unless otherwise note, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 32. CKE is HIGH during refresh command period t RFC (MIN) else CKE is LOW. The IDD 6 limit is actually a nominal value and does not result in a fail value Capacitance[] Parameter Description CIN Input Capacitance COUT Output Capacitance AC Test Loads Test Conditions TA=25℃, f=1Mhz, VDD(typ) Max Units 4 pF 6 pF VDDQ/2 50W Z0=50W OUTPUT 30pF Confidential - 15 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN AC Characteristics AC Characteristics Symbol Parameter tCLKS3 Clock Period[33.] -6 Min Max 6.0 Units ns tCLKS2 12 Clock High Time tCH 2.5 ns Clock Low Time tCL 2.5 ns Address Setup Time to Clock tCAS 2.0 ns Address Hold Time to Clock tCAH 1.0 ns CKE Setup Time to Clock tCKS 2.0 ns CKE Hold Time to Clock tCKH 1.0 ns Clock Access Time [34, 35] CL=3 tAC(3) 5.5 ns CL=2 CL=1 tAC(2) 6 ns tAC(1) 22 ns Output Hold Time from Clock tOH 2.5 ns Data In Setup Time to Clock tCDS 2.0 ns Data In Hold Time to Clock tCDH 1.0 ns /CS, /RAS, /CAS, /WE, /DQM Setup Time to Clock tCMS 2.0 ns /CS, /RAS, /CAS, /WE, /DQM Hold Time to Clock tCMH 1.0 ns Data High Impedance 6 ns 100000 ns Time[25.] tHZ Active to Precharge Command tRAS 48 Active to Active Command Period tRC 60 Active to Read/Write Delay tRCD 18 Refresh Period(4096 rows) tREF Auto Refresh Period tRFC 80 ns Precharge Command Period tRP 18 ns Active Bank ‘a’ to Active Bank ’b’ Command tRRD 12 ns Transition Time [36.] Write Recovery Time[37.] Exit Self Refresh to Active Command [38.] ns ns 64 tT 0.5 tWR 15 1.2 ms ns ns tXSR 80 ns READ/WRITE command to READ/WRITE command[39.] tCCD 1 tCLK CKE to clock disable or power-down entry mode[40.] tCKED 1 tCLK CKE to clock enable or power-down exit setup mode [40.] DQM to input data delay[39.] DQM to data mask during WRITEs [39.] DQM to data high-impedance during READs[39.] WRITE command to input data delay Data-in to ACTIVE command [39.] [41.] Data-in to PRECHARGE command[42.] Last data-in to burst STOP command Confidential [39.] - 16 of 46 - tPED 1 tCLK tDQD 0 tCLK tDQM 0 tCLK tDQZ 2 tCLK tDWD 0 tCLK tDAL 5 tCLK tDPL 2 tCLK tBDL 1 tCLK Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN AC Characteristics AC Characteristics Symbol Parameter -6 Min Max Units Last data-in to new READ/WRITE command[40.] tCDL 1 tCLK Last data-in to PRECHARGE command[43.] tRDL 2 tCLK command[44.] tMRD 2 tCLK CL=3 tROH(3) 3 tCLK CL=2 tROH(2) 2 tCLK CL=1 tROH(1) 1 tCLK LOAD MODE REGISTER command to ACTIVE or REFRESH Data-out to high-impedance from PRECHARGE command[40.] Note : 33. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 34. tAC for -166Mhz at CL=3 with no load is 5ns and is guaranteed by design. 35. tAC for -166Mhz at CL=3 and VDD of 1.8V is 5.5ns. 36. AC characteristics assume tT = 1ns. 37. Auto precharge mode only. The precharge timing budget (tRP) begins at 3ns for -166Mhz after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 38. CLK must be toggled a minimum of two times during this period. 39. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 40. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 41. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 42. Timing actually specified by tWR. 43. JEDEC and PC100 specify three clocks. Confidential - 17 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Operation Figure 3. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 2. shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (The burst will wrap around at the end of the page). A continuous flow of data can be maintained by having additional Read Burst or single Read Command. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 4. for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Full-speed random read accesses can be performed to the same bank, as shown in Figure 5. , or each subsequent READ may be performed to a different bank. BANK / ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. A READ or WRITE command may then be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a t RCD specification of 18ns with a 166MHz clock (6ns period) results in 3 clocks. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. READs READ bursts are initiated with a READ command, as shown in Read Command CLK CKE High /CS /RAS /CAS /WE A0-A8 Column Address A9, A11 Enable Auto Precharge A10 Disable Auto Precharge BA0, 1 Bank Address Don’t Care Figure 3. Read Command Confidential - 18 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 Read NOP NOP T3 T4 T5 Read NOP CLK Command NOP X=0cycles Bank Col n Address Bank Col b Dout n DQ Dout n+1 Dout n+2 Dout n+3 Dout b CAS Latency=1 T0 T1 T2 T3 CLK T5 T6 X=1cycles Command Read Address Bank Col n NOP NOP NOP Read NOP NOP Bank Col b Dout n DQ T4 Dout n+1 Dout n+2 Dout n+3 Dout b CAS Latency=2 Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 Confidential - 19 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 Read NOP T3 T4 T5 T6 T7 CLK Command NOP NOP Read NOP NOP NOP X=2cycles Bank Col n Address Bank Col b Dout n DQ Dout n+1 Dout n+2 Dout n+3 Dout b CAS Latency=3 Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 T0 T1 T2 T3 Command Read Read Read Read Address Bank Col n Bank Col a Bank Col x Bank Col m T4 CLK DQ Dout n Dout a Dout x NOP Dout m CAS Latency=1 Figure 5. Random Read Accesses for CAS Latency =1,2,3 Confidential - 20 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 T3 Command Read Read Read Read Address Bank Col n Bank Col a Bank Col x Bank Col m T4 T5 CLK Dout n DQ NOP Dout a NOP Dout x Dout m CAS Latency=2 T0 T1 T2 T3 Command Read Read Read Read Address Bank Col n Bank Col a Bank Col x Bank Col m T4 T5 T6 CLK Dout n DQ NOP Dout a NOP Dout x NOP Dout m CAS Latency=3 Figure 5. Random Read Accesses for CAS Latency =1,2,3 A Read Burst can be terminated by a subsequent Write command, and data from a fixed length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least Confidential a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 6. and Figure 7. . The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM - 21 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN was active on the clock just prior to the WRITE command that truncated the READ command. The DQM signal must be asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 6. shows the case where the clock frequency T0 T1 allows for bus contention to be avoided without adding a NOP cycle, and Figure 7. shows the case with the additional NOP cycle. T2 T3 T4 CLK DQM tCLK Command Read Address Bank Col n NOP NOP NOP Write Bank Col b tHZ Dout n DQ CAS Latency=3 Din b tDS Figure 6. Read to Write Confidential - 22 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T2 T1 T3 T4 T5 CLK DQM tCLK Command Read Address Bank Col n NOP NOP NOP NOP Write Bank Col b tHZ Dout n DQ Din b CAS Latency=3 tDS Figure 7. Read to Write with extra clock cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CMD Read Write Read masked by write DQM Din n DQ CMD Din n+1 Read Din n+2 Write Din n+3 Read masked by DQM DQM Din n DQ CMD Read Din n+2 Din n+3 Din n+1 Din n+2 Write Read CAS=2 DQM DQ Din n+1 Dout n Din n Din n+3 Figure 8. Read Interrupted by Write with DQM ; CAS Latency =2 Confidential - 23 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN A fixed-length READ burst or a full-page burst may be followed by, or truncated with, a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 9. for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, T0 T2 T1 a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 10. for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. T3 T4 T5 CLK Command T6 T7 tRP Read NOP NOP NOP Precharge NOP NOP Active X=0cycles Address Bank a Col n Bank (a or all) Dout n DQ Dout n+1 Dout n+2 Dout n+3 T3 T4 Bank a Row CAS Latency=1 T0 T2 T1 T5 CLK Command T6 T7 tRP Read NOP NOP NOP Precharge NOP NOP Active X=1cycles Address Bank a Col n Bank (a or all) Dout n DQ Dout n+1 Dout n+2 Bank a Row Dout n+3 CAS Latency=2 Figure 9. Read to Precharge Confidential - 24 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 T3 T4 T5 CLK Command T6 T7 tRP Read NOP NOP NOP Precharge NOP NOP Active X=2cycles Address Bank a Col n Bank (a or all) Dout n DQ Dout n+1 Bank a Row Dout n+2 Dout n+3 T5 T6 CAS Latency=3 Figure 9. Read to Precharge T0 T1 Read NOP T2 T3 T4 T7 CLK Command NOP NOP Burst Terminate NOP NOP NOP X=0cycles Address DQ Bank a Col n Dout n Dout n+1 Dout n+2 Dout n+3 CAS Latency=1 Figure 10. Terminating a Read Burst Confidential - 25 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 Read NOP T2 T3 T4 T5 T6 T7 CLK Command NOP NOP Burst Terminate NOP NOP NOP X=1cycles Address Bank a Col n Dout n DQ Dout n+1 Dout n+2 Dout n+3 T3 T4 T5 CAS Latency=2 T0 T1 Read NOP T2 T6 T7 CLK Command NOP NOP Burst Terminate NOP NOP NOP X=2cycles Address DQ Bank a Col n Dout n Dout n+1 Dout n+2 Dout n+3 CAS Latency=3 Figure 10. Terminating a Read Burst Confidential - 26 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE HIGH *note 45. tRC /CS tRP tRCD /RAS *note 46. /CAS ADDR RAa CAa RAb CAb BA0 BA1 A10/AP RAa RAb tOH CL=2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tRAC tAC *note 47. DQ tHZ *note 48. tWR tOH Qa0 CL=3 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tRAC *note 47. tAC tHZ *note 48. tWR /WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) Don’t Care Note : 45. Minimum row cycle times is required to complete internal DRAM operation. 46. Row precharge can interrupt burst on any cycle.[CAS Latency -1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after the clock. 47. Access time from Row active command. t CLK *(tRCD + CAS latency - 1) + tAC 48. Out put will be Hi-Z after the end of burst. (1,2,3,8 & Full page bit burst) Figure 11. Read & Write Cycle at Same Bank @Burst Length=4 Confidential - 27 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE HIGH *note 45. tRC /CS tRCD tRP /RAS *note 46. /CAS ADDR RAa CAa RAb CAb BA0 BA1 A10/AP RAa RAb tOH CL=2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tRAC tAC *note 47. DQ tHZ *note 48. tWR tOH Qa0 CL=3 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tRAC *note 47. tAC tHZ *note 48. tWR /WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Don’t Care Figure 12. Read & Write Cycle at Same Bank @Burst Length=4 Confidential - 28 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE HIGH /CS /RAS *note 49. /CAS ADDR RAa RBb CAa RCc CBb RDd CCc RAa RBb RCc RDd CDd BA0 BA1 A10/AP CL=2 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 DQ CL=3 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 /WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (C-Bank) Read (D-Bank) Precharge (D-Bank) Precharge (C-Bank) Row Active (C-Bank) Precharge (A-Bank) Precharge (B-Bank) Don’t Care Note : 49. Row precharge will interrupt writing. Last data input, t WR before Row precharge, will be written. Figure 13. Page Read Cycle at Same Bank @ Burst Length=4 WRITE WRITE bursts are initiated with a WRITE command,as shown Confidential in Figure 14. The starting column and bank addresses are provided with the WRITE command, and auto precharge is - 29 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixedlength burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 15.). A full-page burst will continue until terminated. (wrap around at the end of the page) An example is shown in Figure 16. . Data n + 1 is either the last of a burst of two or the last desired of a longer burst. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 17. , or each subsequent WRITE may be performed to a different bank. Write Command CLK CKE High /CS /RAS /CAS /WE A0-A8 Column Address A9, A11 Enable Auto Precharge A10 Disable Auto Precharge BA0, 1 Bank Address Don’t Care Figure 14. Write Command Confidential - 30 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 Command Write NOP NOP Address Bank Col n T3 CLK Din n DQ NOP Din n+1 Figure 15. Write Burst - Burst length of 2 T0 T1 T2 Command Write NOP Write Address Bank Col n CLK DQ Bank Col b Din n Din n+1 Din b Figure 16. Write to Write - Transition from a burst of 2 to a single write Data for a fixed-length WRITE burst a full-page WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank.The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge Confidential prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 19. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. - 31 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 T3 Command Write Write Write Write Address Bank Col n Bank Col a Bank Col x Bank Col m Din n Din a Din x Din m CLK DQ Figure 17. Random Write Cycles T0 T1 T2 NOP Read T3 T4 T5 CLK Command Write Address Bank Col n DQ Din n NOP NOP NOP Bank Col b Din n+1 Dout b Dout b+1 Figure 18. Write to Read Burst of 2 Write and Read(CAS Latency =2) Confidential - 32 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 CLK T2 T1 T3 T4 T5 Active NOP NOP NOP Active T6 tWR @ tCLK >=15ns DQM tRP Command Write Address Bank Col n NOP Precharge NOP Bank (a or all) Bank a Row tWR DQ DQM Din n+1 Din n tWR @ tCLK =tCKS tCKS CKE NOP Command All banks Idle NOP tRCD tRAS tRC Input buffers gated off Enter Power Down Mode Active Exit Power Down Mode Figure 22. Power Down CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burstcounters are not incremented, as long as the clock is suspended. (See examples in Figure 23. and Figure 24. .) Clock Confidential suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. READ commands access columns according to the programmed burst length and sequence. - 36 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 T3 T4 T5 CLK CKE Internal CLK Command NOP Write Address Bank Col n DQ Din n NOP NOP Din n+1 Din n+2 Figure 23. Clock Suspend During Write Burst Confidential - 37 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 T3 T4 T5 T6 CLK CKE Internal CLK Command Read Address Bank Col n NOP NOP NOP Dout n DQ Dout n+1 NOP Dout n+2 NOP Dout n+3 Figure 24. Clock Suspend During Read Burst - Burst of 4 (CAS latency =2) Concurrent Auto Precharge If an access command with Auto Precharge is being executed ; an access command (either a Read or Write ) is not allowed by SDRAM’s. If this feature is allowed then the SDRAM supports Concurrent Auto Precharge. Alliance Memory SDRAMs support Concurrent Auto Precharge. Four cases where Concurrent Auto Precharge occurs are defined below. Read With Auto Precharge 1. Interrupted by a Read(with or without auto precharge): A read to bank m will interrupt a Read on bank n, CAS latency later. The precharge to bank n will begin when the Read to bank m is registered. (Figure 25. ) 2. Interrupted by a Write(with or without auto precharge): A Write to bank m will interrupt a Read on bank n when registered. Confidential DQM should be used two clocks prior to the Write command to prevent bus contention. The Precharge to bank n will begin when the write to bank m is registered. (Figure 26. ) Write with Auto Precharge 3. Interrupted by a Read(with or without auto precharge): A Read to bank m will interrupt a Write on bank n when registered , with the data-out appearing CAS latency later. The Precharge to bank n will begin after tWR is met, where tWR begins when the Read to bank m is registered. The last valid Write to bank n will be data-in registered one clock prior to the Read to bank m.(Figure 27. ) 4. Interrupted by a Write ( with or without auto Precharge): A Write to bank m will interrupt a Write on bank n when registered. The Precharge to bank n will begin after tWR is met ,where tWR begins when the Write to bank m is registered. The latest valid data Write to bank n will be data registered one clock prior to a Write to bank m.( Figure 28. ) - 38 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 Read-AP Bank n NOP T3 T4 T5 T6 NOP NOP NOP T7 CLK Command NOP Read-AP Bank m Internal States NOP tRP - Bank m tRP - Bank n Bank n Page Active Bank m Page Active Read with a Burst of 4 Idle Read with Burst of 4 Bank n Col a Address Interrupt Burst, Precharge Precharge Bank m Col d Dout a DQ Dout a+1 Dout d Dout d+1 CAS Latency=3(Bank n) CAS Latency=3(Bank m) Figure 25. Read with Auto Precharge Interrupted by a Read(CAS Latency =3) T0 T1 T2 Read-AP Bank n NOP NOP T3 T4 T5 T6 T7 CLK Command NOP Write-AP Bank m NOP NOP tRP - Bank n Internal States Bank n Page Active Bank m Page Active Address NOP Read with a Burst of 4 tWR - Bank m Interrupt Burst, Precharge Idle Write with Burst of 4 Write-Bank m Bank m Col d Bank n Col a DQM Dout a DQ Din d Din d+1 Din d+2 Din d+3 CAS Latency=3(Bank n) Figure 26. Read With Auto Precharge Interrupted by a Write(Read CAS Latency =3) Confidential - 39 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN T0 T1 T2 Write-AP Bank n NOP T3 T4 T5 T6 NOP NOP NOP T7 CLK Command NOP Internal States Bank n Read-AP Bank m NOP tRP - Bank m tWR- Bank n Page Active Write with a Burst of 4 Interrupt Burst, Write-Bank Precharge tRP - Bank n Bank m Page Active Read with Burst of 4 Bank n Col a Address Din a DQ Precharge Bank m Col d Din a+1 Dout d Dout d+1 CAS Latency=3(Bank m) Figure 27. Write with Auto Precharge Interrupted by a Read(CAS Latency =3) T0 T1 T2 Write-AP Bank n NOP T3 T4 T5 T6 NOP NOP T7 CLK Command NOP NOP Internal States Bank n Write-AP Bank m tWR -Bank n Page Active Write with a Burst of 4 NOP tRP -Bank n Interrupt Burst, Write-Bank Precharge tWR - Bank m Bank m Address DQ Page Active Write with Burst of 4 Bank n Col a Din a Write-Bank m Bank m Col d Din a+1 Din a+2 Din d Din d+1 Din d+2 Din d+2 Figure 28. Write with Auto Precharge Interrupted by a Write Confidential - 40 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN DEEP POWER DOWN MODE ENTRY The Deep Power Down Mode is entered by having burst termination command, while CKE is low. The Deep Power Down Mode has to be maintained for a minimum of 200us. The following diagram illustrates Deep Power Down mode entry. CLK CKE tRP Command NOP Precharge All Bank NOP Burst Terminate NOP Precharge If needed Deep Power Down Entry Figure 29. Deep Power Down Mode Entry DEEP POWER DOWN MODE EXIT SEQUENCE The Deep Power Down Mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command 1. Maintain NOP input conditions for a minimum of 200us 2. Issue precharge commands for all banks of the device 3. Issue 2 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue a extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down exit sequence CLK CKE Precharge All Bank Command Address NOP AREF A10 NOP EMRS NOP Active Key Key Bank a Row Normal MRS Extended MRS Row Active A Bank tRP 200 us Deep Power Down Exit MRS Precharge All Bank Figure 30. Deep Power Down Mode Exit Confidential - 41 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 9. CKE[50.51.52.53.] . CKEn-1 CKEn L L L H H L H H Current State Commandn Actionn Power Down X Maintain Power Down Self Refresh X Maintain Self Refresh Clock Suspend X Maintain Clock Suspend Power Down[54.] Self Refresh[55.] Command Inhibit or NOP Command Inhibit or NOP Exit Power Down Exit Self Refresh Clock Suspend[56.] X Exit Clock Suspend All Banks Idle Command Inhibit or NOP Power Down Entry All Banks Idle Reading or Writing Auto Refresh Valid Self Refresh Entry Clock Suspend Entry See Table 10. Note : 50. 51. 52. 53. 54. 55. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current State is the state of the SDRAM immediately prior to the clock edge n. Commandn is the command registered at clock edge n , and Action n is a result of Commandn. All states and sequences not shown are illegal or reserved. Exiting power down at clock edge n will put the device in all the banks idle state in time for clock edge n+1(provided the tCKS is met) Exiting self refresh at clock edge n will put the device in all the banks idle state once t XSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum of two NOP commands must be provided during the t XSR period. 56. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1. Table 10. Current State Bank n, Command to Bank n[57.58.59.60.61.62.] . Current State Any Idle CS# RAS# CAS# WE# Command(Action) H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) L L H H ACTIVE (Select and activate row) L L L H AUTO REFRESH[63.] L L L L LOAD MODE REGISTER [63.] L L H L PRECHARGE [67.] Note : 57. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9. ) and after tXSR has been met (if the previous state was self refresh). 58. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 59. Current state definitions: Idle: The bank has been precharged, and t RP has been met. Row Active: A row in the bank has been activated, and t RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 60. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10. and according to Table 11. . Precharging: Starts with registration of a PRECHARGE command and ends when t RP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when t RCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when t RP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when t RP has been met. Once tRP is met, the bank will be in the idle state. 61. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when t RC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when t MRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t RP is met. Once tRP is met, all banks will be in the idle state. 62. All states and sequences not shown are illegal or reserved. 63. Not bank-specific; requires that all banks are idle. 64. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 65. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 66. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or W RITEs with auto precharge disabled. 67. Does not affect the state of the bank and acts as a NOP to that bank. Confidential - 42 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 10. Current State Bank n, Command to Bank n[57.58.59.60.61.62.] . Current State Row Active Read(Auto Precharge Disabled) Write (Auto Precharge Disabled) CS# RAS# CAS# WE# Command(Action) L H L H READ (Select column and start READ burst)[66.] L H L L WRITE (Select column and start WRITE burst)[66.] L L H L PRECHARGE (Deactivate row in bank or banks)[64.] L H L H READ (Select column and start new READ burst)[66.] L H L L WRITE (Select column and start WRITE burst)[66.] L L H L PRECHARGE (Truncate READ burst, start RECHARGE)[64.] L H H L BURST TERMINATE[65.] L H L H READ (Select column and start READ burst)[66.] L H L L WRITE (Select column and start new WRITE burst)[66.] L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE)[64.] L H H L BURST TERMINATE[65.] Table 11. Current State Bank n, Command to Bank m[68.69.70.71.72.73.] . Current State Any Idle Row Activating, Active, or Precharging Read(Auto Precharge Disabled) Write(Auto Precharge Disabled) Confidential CS# RAS# CAS# WE# H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) X X X X Any Command Otherwise Allowed to Bank m L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst)[74.] L H L L WRITE (Select column and start WRITE burst)[74.] L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start new READ burst)[74.78.] L H L L WRITE (Select column and start WRITE burst)[74.79.] L L H L PRECHARGE[76.] L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst)[74.79.] L H L L WRITE (Select column and start new WRITE burst)[76.80.] L L H L PRECHARGE[76.] - 43 of 46 - Command(Action) Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN Table 11. Current State Bank n, Command to Bank m[68.69.70.71.72.73.] . Current State Read (With Auto Precharge) Write (With Auto Precharge) CS# RAS# CAS# WE# Command(Action) L L H L ACTIVE (Select and activate row) L H L H READ (Select column and start new READ burst)[74.75.81.] L H L L WRITE (Select column and start WRITE burst)[74.75.82.] L L H L PRECHARGE[76.] L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst)[74.75.83.] L H L L WRITE (Select column and start new WRITE burst)[74.75.84.] L L H L PRECHARGE[76.] Note : 68. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if the previous state was self refresh). 69. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 70. Current state definitions: Idle: The bank has been precharged, and t RP has been met. Row Active: A row in the bank has been activated, and t RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabl ed, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 71. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 72. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 73. All states and sequences not shown are illegal or reserved. 74. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 75. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst. 76. Burst in bank n continues as initiated. 77. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. 78. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used twwo clock prior to the WRITE command to prevent bus contention. 79. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 80. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 81. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 25.) . 82. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 26. ). 83. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m(Figure 27. ). 84. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 28. ). Confidential - 44 of 46 - Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN PACKAGE DIMENSION Unit : millimeters 54 BALL FINE PITCH BGA Top View Bottom View E 1 #A1 2 3 4 5 A1 INDEX MARK E1 6 7 8 9 9 A A B B C C D D D1 D E 8 7 6 5 4 3 2 1 e E F F G G H H J J D/2 e E/2 Side View A1 z b A E Confidential - 45 of 46 - A A1 E E1 D D1 e b z Min 0.20 0.30 - Typ 0.25 8.00 6.40 8.00 6.40 0.80 0.35 - Unit : mm Max 1.00 0.30 0.40 0.10 Rev.1.0 Dec. 2017 AS4C8M16MSA-6BIN PART NUMBERING SYSTEM AS4C 8M16MSA DRAM 8M16=8Mx16 MS=Mobile SDRAM A=A Die Rev. 6 6=166MHz B B = FBGA I N I=Industrial Indicates Pb and (-40° C~+85° C) Halogen Free XX Packing Type None:Tray TR:Reel Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 46 of 46 - Rev.1.0 Dec. 2017