AS4C8M16S-6BIN

AS4C8M16S 128M - 8M x 16 bit Synchronous DRAM (SDRAM) Confidential (Rev. 2, Feb. /2014) Features Overview Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function x Auto Refresh and Self Refresh x 4096 refresh cycles/64ms x CKE power down mode x Single +3.3V r 0.3V power supply x Interface: LVTTL x Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C) - Automotive A2 (-40 ~ 105°C) 54-pin 400 mil plastic TSOP II package x 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package x All parts ROHS Compliant The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. x x x x x x Table 1. Key Specifications AS4C16M16S tCK3 Clock Cycle time (min.) tAC3 Access time from CLK (max.) tRAS Row Active time (min.) tRC Row Cycle time (min.) The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. -6/7 6/7 ns 5.4/5.4 ns 42/42 ns 60/63 ns Table 2. Ordering Information Part Number Frequency Package AS4C8M16S-7TCN 143 MHz 54 pin TSOP II AS4C8M16S-6TCN 166 MHz 54 pin TSOP II AS4C8M16S-6TIN 166 MHz 54 pin TSOP II AS4C8M16S-6BIN 166 MHz 54 ball TFBGA AS4C8M16S-7BCN 143 MHz 54 ball TFBGA AS4C8M16S-6TAN 166 MHz 54 pin TSOP II T : indicates TSOP II package B : indicates TFBGA package N : indicates Pb free and Halogen free – ROHS compliant parts C: Commercial I: Industrial A: Automotive temperatures Confidential 1 Rev. 2 Feb. /2014 AS4C8M16S Figure 1.1 Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE# CAS# RAS# CS# BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Confidential 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Figure 1.2 Ball Assignment (Top View) VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC/RFU UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 2 1 2 3 A VSS DQ15 B DQ14 C … 7 8 9 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS# RAS# WE# G NC A11 A9 BA0 BA1 CS# H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Rev. 2 Feb. /2014 AS4C8M16S Figure 2. Block Diagram CLOCK BUFFER Row Decoder CLK CKE 2M x 16 CELL ARRAY (BANK #A) Column Decoder COMMAND DECODER DQ0 DQ Buffer CONTROL SIGNAL GENERATOR ~ CS# RAS# CAS# WE# DQ15 A10/AP COLUMN COUNTER MODE REGISTER A9 A11 BA0 BA1 2M x 16 CELL ARRAY (BANK #B) Column Decoder ADDRESS BUFFER Row Decoder ~ A0 Row Decoder LDQM, UDQM REFRESH COUNTER 2M x 16 CELL ARRAY (BANK #C) Row Decoder Column Decoder 2M x 16 CELL ARRAY (BANK #D) Column Decoder Confidential 3 Rev. 2 Feb. /2014 AS4C8M16S Pin Descriptions Table 3. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. BA0,BA1 Input Bank Activate: BA0, BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the opcode during a Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted “LOW” and CAS# is asserted “HIGH,” either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted “HIGH,” the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE# is asserted “LOW,” the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held “HIGH” and CS# is asserted “LOW,” the column access is started by asserting CAS# “LOW.” Then, the Read or Write command is selected by asserting WE# “LOW” or “HIGH.” WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Confidential 4 Rev. 2 Feb. /2014 AS4C8M16S LDQM, UDQM Input DQ0-DQ15 Input / Output NC/RFU - VDDQ Supply Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode. Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskable during Reads and Writes. No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3Vr 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0V) VDD Supply Power Supply: +3.3V r 0.3V VSS Supply Ground Confidential 5 Rev. 2 Feb. /2014 AS4C8M16S Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4 shows the truth table for the operation commands. Table 4. Truth Table (Note (1), (2)) Command BankActivate BankPrecharge PrechargeAll State CKEn-1 CKEn DQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE# Idle(3) H X X V Row address Any H X X V L L L H H X L L H L Any H X X X H X L L H L Write Active(3) H X V V L L H L L Write and AutoPrecharge Active(3) H X V V H Column address (A0 ~ A8) L H L L Read Active(3) H X V V L H L H Active(3) H X V V H Column address (A0 ~ A8) L Read and Autoprecharge L H L H Idle H X X L L L L Mode Register Set No-Operation OP code Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H Idle L H X X X X H X X X L H H H H X X X L V V V H X X X L H H H Burst Stop SelfRefresh Exit (SelfRefresh) Clock Suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Active Any(5) H H L L X X X X X X X X Active L H X X X X X X X X Any L H X X X X H X X X L H H H X X X X X X (PowerDown) Data Write/Output Enable Active H X L X X X Data Mask/Output Disable Active H X H X X X X X Note: 1. V=Valid, X=Don’t Care L=Low level H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. Confidential 6 Rev. 2 Feb. /2014 AS4C8M16S Commands 0 BankActivate (RAS# = “L”, CAS# = “H”, WE# = “H”, Bas = Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0, 1 signals. By latching the row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD (min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC (min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the two banks. tRRD (min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 Tn+3 T3 Tn+4 Tn+5 Tn+6 CLK ADDRESS Bank A Row Addr. Bank A Col Addr. Bank B Row Addr. R/W A with AutoPrecharge Bank B Activate RAS# - CAS# delay(tRCD) COMMAND Bank A Activate NOP NOP Bank A Row Addr. RAS# - RAS# delay time(tRRD) NOP NOP Bank A Activate RAS# - Cycle time(tRC) AutoPrecharge Begin Don’t Care Figure 3. BankActivate Command Cycle (Burst Length = n) 2 BankPrecharge command (RAS# = “L”, CAS# = “H”, WE# = “L”, Bas = Bank, A10 = “L”, A0-A9 and A11 = Don’t care) The BankPrecharge command precharges the bank designated by BA signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 PrechargeAll command (RAS# = “L”, CAS# = “H”, WE# = “L”, Bas = Don’t care, A10 = “H”, A0-A9 and A11 = Don’t care) The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. 4 Read command (RAS# = “H”, CAS# = “L”, WE# = “H”, Bas = Bank, A10 = “L”, A0-A8 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least t RCD (min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). Confidential 7 Rev. 2 Feb. /2014 AS4C8M16S T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP CAS# Latency=2 tCK2, DQ DOUT A0 CAS# Latency=3 tCK3, DQ NOP NOP NOP NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP NOP DOUT A3 Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A READ B NOP CAS# Latency=2 tCK2, DQ DOUT A0 CAS# Latency=3 tCK3, DQ NOP NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 NOP DOUT B3 Figure 5. Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention. T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CLK DQM COMMAND NOP NOP Bank A Activate NOP CAS# Latency=2 tCK2, DQ NOP READ A WRITE A NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 Figure 6. Read to Write Interval (Burst Length t 4, CAS# Latency = 2) Confidential 8 Rev. 2 Feb. /2014 AS4C8M16S T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP READ A NOP NOP NOP CAS# Latency=3 tCK3, DQ NOP WRITE B NOP NOP DIN B0 DIN B1 DIN B2 DOUT A0 Must be Hi-Z before the Write Command Don’t Care Figure 7. Read to Write Interval (Burst Length ʁ 4, CAS# Latency = 3) T1 T0 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP NOP CAS# Latency=2 tCK2, DQ WRITE B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 Must be Hi-Z before the Write Command Don’t Care Figure 8. Read to Write Interval (Burst Length t 4, CAS# Latency = 2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS latency. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Bank, Col A ADDRESS Bank Row Bank (s) tRP COMMAND READ A CAS# Latency=2 tCK2, DQ NOP NOP NOP DOUT A0 CAS# Latency=3 tCK3, DQ Precharge NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP Activate NOP DOUT A3 Figure 9. Read to Precharge (CAS# Latency = 2, 3) 5 Read and AutoPrecharge command (RAS# = “H”, CAS# = “L”, WE# = “H”, Bas = Bank, A10 = “H”, A0-A8 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay Confidential 9 Rev. 2 Feb. /2014 AS4C8M16S 6 of {tRP (min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. Write command (RAS# = “H”, CAS# = “L”, WE# = “L”, Bas = Bank, A10 = “L”, A0-A8 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least t RCD (min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP DQ WRITE A NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care NOP NOP NOP The first data element and the write are registered on the same clock edge Figure 10. Burst Write Operation (Burst Length = 4) A write burst without the auto precharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND DQ NOP WRITE A WRITE B NOP NOP NOP DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 NOP NOP NOP Figure 11. Write Interrupted by a Write (Burst Length = 4) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed. Confidential 10 Rev. 2 Feb. /2014 AS4C8M16S T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A READ B NOP CAS# Latency=2 tCK2, DQ DIN A0 don’t care CAS# Latency=3 tCK3, DQ DIN A0 don’t care NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 don’t care NOP NOP NOP DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T1 T0 T2 T3 T4 T5 T6 T7 CLK DQM tRP COMMAND WRITE NOP NOP Bank Col n ADDRESS NOP Precharge NOP Activate NOP ROW Bank (s) tWR DIN n DQ DIN N+1 Don’t Care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Figure 13. Write to Precharge 7 Write and AutoPrecharge command (RAS# = “H”, CAS# = “L”, WE# = “L”, Bas = Bank, A10 = “H”, A0-A8 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CLK COMMAND Bank A Activate NOP NOP WRITE A Auto Precharge NOP NOP NOP NOP NOP Bank A Activate tDAL DQ DIN A0 tDAL=tWR+tRP Confidential DIN A1 Begin AutoPrecharge Bank can be reactivated at completion of tDAL 11 Rev. 2 Feb. /2014 AS4C8M16S Figure 14. Burst Write with Auto-Precharge (Burst Length = 2) 8 Mode Register Set command (RAS# = “L”, CAS# = “L”, WE# = “L”, A0-A11 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register. Two clock cycles are required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. Table 5. Mode Register Bitmap BA0,1 A11,A10 A9 RFU* RFU* WBL A9 0 1 Write Burst Length Burst Single Bit A8 A7 Test Mode A8 0 1 0 A7 0 0 1 A6 A5 A4 CAS Latency Test Mode Normal Vendor Use Only Vendor Use Only A3 BT A2 A3 0 1 A1 A0 Burst Length Burst Type Sequential Interleave A6 0 0 0 0 1 A5 A4 CAS Latency A2 A1 A0 Burst Length 0 0 Reserved 0 0 0 1 0 1 Reserved 0 0 1 2 1 0 2 clocks 0 1 0 4 1 1 3 clocks 0 1 1 8 0 0 Reserved 1 1 1 Full Page (Sequential) All other Reserved All other Reserved *Note: RFU (Reserved for future use) should stay “0” during MRS cycle. Confidential 12 Rev. 2 Feb. /2014 AS4C8M16S T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK CKE tMRD CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9, A11 DQM DQ tRP Hi-Z PrechargeAll Mode Register Set Command Don’t Care Any Command Figure 15. Mode Register Set Cycle Confidential 13 Rev. 2 Feb. /2014 AS4C8M16S x Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. Table 6. Burst Length Field A2 A1 A0 Burst Length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Full Page Full Page Length: 512 x Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. Table 7. Burst Type Field x A3 Burst Type 0 Sequential 1 Interleave Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 8. Burst Definition Burst Length 2 4 8 Full page Start Address A2 A1 A0 X X 0 X X 1 X 0 0 X 0 1 X 1 0 X 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 location = 0-511 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 n, n+1, n+2, n+3, …511, 0, 1, 2, … n-1, n, … Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Not Support x CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) d CAS Latency X tCK Confidential 14 Rev. 2 Feb. /2014 AS4C8M16S Table 9. CAS Latency Field A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 X X Reserved Test Mode Field (A8~A7) x These two bits are used to enter the test mode and must be programmed to “00” in normal operation. Table 10. Test Mode Field A8 A7 Test Mode 0 0 normal mode 0 1 Vendor Use Only 1 X Vendor Use Only x Write Burst Length (A9) This bit is used to select the write burst mode. When the A9 bit is “0”, the Burst-Read-Burst-Write mode is selected. When the A9 bit is “1”, the Burst-Read-Single-Write mode is selected. Table 11. Write Burst Length A9 Write Burst Mode 0 Burst-Read-Burst-Write 1 Burst-Read-Single-Write Note: A10 and BA should stay “L” during mode set cycle. 9 No-Operation command (RAS# = “H”, CAS# = “H”, WE# = “H”) The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states. 10 Burst Stop command (RAS# = “H”, CAS# = “H”, WE# = “L”) The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS latency (refer to the following figure). The termination of a write burst is shown in the following figure. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS# Latency=2 tCK2, DQ CAS# Latency=3 tCK3, DQ READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP The burst ends after a delay equal to the CAS# Latency DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 ! Figure 16. Termination of a Burst Read Operation (Burst Length 烍 4, CAS# Latency = 2, 3) Confidential 15 Rev. 2 Feb. /2014 AS4C8M16S T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND DQ NOP WRITE A NOP NOP Burst Stop DIN A0 DIN A1 DIN A2 don’t care NOP NOP NOP NOP Figure 17. Termination of a Burst Write Operation (Burst Length = X) 11 Device Deselect command (CS# = “H”) The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. 12 AutoRefresh command (RAS# = “L”, CAS# = “L”, WE# = “H”, CKE = “H”, A11 = “Don‘t care, A0-A9 = Don’t care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “don’t care” during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 4096 times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed. 13 SelfRefresh Entry command (RAS# = “L”, CAS# = “L”, WE# = “H”, CKE = “L”, A0-A9 = Don’t care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM become “don’t care” with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). 14 SelfRefresh Exit command This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for t XSR(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. 15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = “L”) When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the subsequent cycle by issuing this command (asserting CKE “LOW”). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations. Confidential 16 Rev. 2 Feb. /2014 AS4C8M16S 16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= “H”) When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE “HIGH”, the command should be NOP or deselect). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. 17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = “L”, “H”) During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. Confidential 17 Rev. 2 Feb. /2014 AS4C8M16S Table 12. Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage TA Ambient Temperature Rating Unit Note -6/7 - 1.0 ~ 4.6 V 1 -1.0 ~ 4.6 V 1 0 ~ 70 °C 1 Industrial -40 ~ 85 °C 1 Automotive -40 ~ 105 °C 1 Commercial TSTG Storage Temperature - 55 ~ 125 °C 1 TSOLDER Soldering Temperature (10 second) 260 °C 1 PD Power Dissipation 1 W 1 IOS Short Circuit Output Current 50 mA 1 Table 13. Recommended D.C. Operating Conditions (TA = -40~85°C) Symbol Parameter Min. Typ. Max. VDD Power Supply Voltage 3.0 3.3 3.6 Unit Note V 2 VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2 VIH LVTTL Input High Voltage 2.0 3.0 VDDQ +0.3 V 2 VIL LVTTL Input Low Voltage - 0.3 0 0.8 V 2 IIL Input Leakage Current ( 0V d VIN d VDD, All other pins not under test = 0V ) - 10 炼 10 PA IOL Output Leakage Current Output disable, 0V d VOUT d VDDQ) - 10 炼 10 PA VOH LVTTL Output "H" Level Voltage ( IOUT = -2mA ) 2.4 炼 炼 V VOL LVTTL Output "L" Level Voltage ( IOUT = 2mA ) 炼 炼 0.4 V Table 14. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C) Symbol CI CI/O Parameter Min. Max. Unit Input Capacitance 2 5 pF Input/Output Capacitance 5 6.5 pF Note: These parameters are periodically sampled and are not 100% tested. Confidential 18 Rev. 2 Feb. /2014 AS4C8M16S Table 15. D.C. Characteristics (VDD = 3.3V r 0.3V, TA = -40~85°C) Symbol Description/Test condition Operating Current tRC t tRC(min), Outputs Open One bank active Precharge Standby Current in non-power down mode tCK = 15ns, CS# t VIH(min), CKE t VIH Input signals are changed every 2clks Precharge Standby Current in non-power down mode tCK = f, CLK d VIL(max), CKE t VIH Precharge Standby Current in power down mode tCK = 15ns, CKE d VIL(max) Precharge Standby Current in power down mode tCK = f, CKE d VIL(max) Active Standby Current in non-power down mode tCK = 15ns, CKE t VIH(min), CS# t VIH(min) Input signals are changed every 2clks Active Standby Current in non-power down mode CKE t VIH(min), CLK d VIL(max), tCK = f Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave Refresh Current tRC t tRC(min) Self Refresh Current CKE d 0.2V ; for other inputs VIH t VDD - 0.2, VIL d 0.2V Confidential IDD1 -6 -7 Unit Note Max. 3 120 110 20 20 IDD2NS 15 15 IDD2P 2 2 IDD2PS 2 2 IDD2N mA IDD3N 30 30 IDD3NS 25 25 IDD4 140 130 3, 4 IDD5 200 200 3 2 2 6 6 TA = 0~70°C TA = -40~85°C 19 IDD6 Rev. 2 Feb. /2014 AS4C8M16S Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V²²0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8) Symbol tRC -6 A.C. Parameter -7 Min Max. Min Max. 60 - 63 - 18 - 21 - 18 - 21 - 12 - 14 - 42 100k 42 100k 2 - 2 - 1 - 1 - CL* = 2 9 - 10 - CL* = 3 6 - 7 - Unit Note tWR Row cycle time (same bank) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to row activate delay (different banks) Row activate to precharge time (same bank) Write recovery time tCCD CAS# to CAS# Delay time tCK Clock cycle time tCH Clock high time 2.5 - 2.5 - 10 tCL Clock low time 2.5 - 2.5 - 10 Access time from CLK (positive edge) CL* = 2 tAC - 6 - 6 CL* = 3 - 5 - 5.4 tOH Data output hold time 2.5 - 2.7 - tLZ Data output low impedance 1 - 1 - tHZ Data output high impedance - 5 - 5.4 8 tIS Data/Address/Control Input set-up time 1.5 - 1.5 - 10 tIH Data/Address/Control Input hold time 1 - 1 - 10 tPDE Power Down Exit set-up time tIS+ tCK - tIS+ tCK - tREFI Refresh Interval Time - 15.6 - 15.6 Ps tXSR Exit Self Refresh to Read Command time tIS+ tRC - tIS+ tRC - ns tRCD tRP tRRD tRAS ns tCK 9 10 ns 9 +!CL is CAS Latency. Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.0V for pulse width ≤ 3ns. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11. 6. A.C. Test Conditions Confidential 20 Rev. 2 Feb. /2014 AS4C8M16S Table 17. LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 1.4V 3.3V 50 : 1.2k: Z0= 50 : Output Output 30pF 30pF 870: Figure 18.1 LVTTL D.C. Test Load (A) Figure 18.2 LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter. 10. Assumed input rise and fall time tT (tR & tF) = 1 ns If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input signals are held "NOP" state. 2) Start clock and maintain stable condition for minimum 200 Ps, then bring CKE= “H” and, it is recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. * The Auto Refresh command can be issue before or after Mode Register Set command Confidential 21 Rev. 2 Feb. /2014 AS4C8M16S Timing Waveforms Figure 19. AC Parameters for Write Timing (Burst Length=4) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCH tCL CKE tIS tIS Begin Auto Precharge Bank A tIH Begin Auto Precharge Bank B CS# RAS# CAS# WE# BA0,1 tIH A10 RAx RBx RAy tIS A0-A9, A11 RAx CAx RBx CBx RAy CAy DQM tRCD tDAL tIS tRC DQ Hi-Z Ax0 Activate Command Bank A Ax1 Write with Auto Precharge Command Bank A Ax2 Activate Command Bank B tWR tIH Ax3 Bx0 Bx1 Write with Auto Precharge Command Bank B Bx2 Bx3 Ay0 Ay1 Activate Command Bank A Write Command Bank A Ay2 Ay3 Precharge Command Bank A Don’t Care Confidential 22 Rev. 2 Feb. /2014 AS4C8M16S Figure 20. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 tCH tCL CKE tIS Begin Auto Precharge Bank B tIS tIH tIH CS# RAS# CAS# WE# BA0,1 tIH A10 RAx RBx RAy tIS A0-A9, A11 RAx CAx RBx CBx RAy tRRD tRAS DQM Hi-Z tRP tHZ tLZ DQ tRC tAC tRCD Ax0 Ax1 Bx0 tHZ tOH Activate Command Bank A Read Command Bank A Bx1 Read with Precharge Auto Precharge Command Command Bank A Bank B Activate Command Bank B Activate Command Bank A Don’t Care Confidential 23 Rev. 2 Feb. /2014 AS4C8M16S Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx tRP tRC tRC CAx tRCD DQM DQ Ax0 Precharge All Command Auto Refresh Command Auto Refresh Command Activate Command Bank A Ax1 Read Command Bank A Don’t Care Confidential 24 Rev. 2 Feb. /2014 AS4C8M16S Figure 22. Power on Sequence and Auto Refresh T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High Level Is reguired Minimum for 2 Refresh Cycles are required CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9, A11 DQM DQ tRP tMRD Hi-Z Precharge All Command Inputs must be Stable for 200μs Mode Register Set Command 1st Auto Refresh(*) Command Any Command 2nd Auto Refresh(*) Command Don’t Care Note(*): The Auto Refresh command can be issue before or after Mode Register Set command Confidential 25 Rev. 2 Feb. /2014 AS4C8M16S Figure 23. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 CLK *Note 1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 *Note 2 CKE tXSR *Note 5 *Note 3,4 *Note 8 tPDE tIS tIH *Note 6 tIS CS# *Note 7 RAS# *Note 9 CAS# WE# BA0,1 A10 A0-A9, A11 DQM DQ Hi-Z Hi-Z Self Refresh Exit Self Refresh Entry Auto Refresh Don’t Care Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". 4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh. 5. 6. 7. 8. 9. To Exit SelfRefresh Mode System clock restart and be stable before returning CKE high. Enable CKE and CKE should be set high for valid setup time and hold time. CS# starts from high. Minimum tXSR is required after CKE going high to complete SelfRefresh exit. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh. Confidential 26 Rev. 2 Feb. /2014 AS4C8M16S Figure 24.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax2 Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential 27 Rev. 2 Feb. /2014 AS4C8M16S Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential 28 Rev. 2 Feb. /2014 AS4C8M16S Figure 25. Clock Suspension During Burst Write (Using CKE) (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A Confidential DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 DAx3 Clock Suspend 3 Cycles Clock Suspend 2 Cycles Don’t Care 29 Rev. 2 Feb. /2014 AS4C8M16S Figure 26. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 CLK T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tIH tIS tPDE CKE Valid CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ tHZ Hi-Z Ax0 ACTIVE Activate Read STANDBY Command Command Bank A Bank A Power Down Power Down Mode Exit Mode Entry Confidential Ax1 Ax2 Clock Suspension Start Ax3 Clock Suspension End Precharge Command Bank A PRECHARGE STANDBY Power Down Mode Entry 30 Power Down Mode Exit Any Command Don’t Care Rev. 2 Feb. /2014 AS4C8M16S Figure 27.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAw A0-A9, A11 RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Aw3 Read Command Bank A Ax0 Ax1 Read Command Bank A Ay0 Ay1 Ay2 Ay3 Precharge Command Bank A Az0 Activate Command Bank A Read Command Bank A Don’t Care Confidential 31 Rev. 2 Feb. /2014 AS4C8M16S Figure 27.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAw A0-A9, A11 RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Read Command Bank A Aw3 Ax0 Read Command Bank A Ax1 Ay0 Ay1 Ay2 Precharge Command Bank A Ay3 Activate Command Bank A Read Command Bank A Don’t Care Confidential 32 Rev. 2 Feb. /2014 AS4C8M16S Figure 28. Random Column Write (Page within same Bank) (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RBw A0-A9, A11 RBw RBz CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 Activate Command Bank B Write Command Bank B DBx1 Write Command Bank B DBy0 DBy1 DBy2 Write Command Bank B DBy3 DBz0 Precharge Command Bank B Activate Command Bank B DBz1 Write Command Bank B Don’t Care Confidential 33 Rev. 2 Feb. /2014 AS4C8M16S Figure 29.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RBx A0-A9, A11 RBx CBx Hi-Z Activate Command Bank B Confidential RBy RAx CAx RBy tAC tRCD DQM DQ RAx tRP Bx0 Read Command Bank B CBy Bx1 Bx2 Bx3 Bx4 Bx5 Activate Command Bank A 34 Bx6 Bx7 Ax0 Read Command Bank A Precharge Command Bank B Ax1 Ax2 Ax3 Ax4 Activate Command Bank B Ax5 Ax6 Ax7 Read Command Bank B Don’t Care Rev. 2 Feb. /2014 AS4C8M16S Figure 29.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RBx A0-A9, A11 RBx CBx Hi-Z Activate Command Bank B RBy RAx CAx RBy tAC tRCD DQM DQ RAx tRP Bx0 Read Command Bank B CBy Bx1 Bx2 Bx3 Bx4 Activate Command Bank A Bx5 Bx6 Read Command Bank A Bx7 Ax0 Precharge Command Bank B Ax1 Ax2 Ax3 Ax4 Activate Command Bank B Ax5 Ax6 Read Command Bank B Ax7 By0 Precharge Command Bank A Don’t Care Confidential 35 Rev. 2 Feb. /2014 AS4C8M16S Figure 30. Random Row Write (Interleaving Banks) (Burst Length=8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx RAy RBx CBx tRCD DQM DQ RBx Hi-Z Activate Command Bank A RAy tWR* DAx0 DAx1 DAx2 DAx3 Write Command Bank A DAx4 DAx5 DAx6 DAx7 Activate Command Bank B DBx0 CAy tRP DBx1 DBx2 DBx3 Write Command Bank B Precharge Command Bank A tWR* DBx4 DBx5 DBx6 DBx7 Activate Command Bank A DAy1 DAy2 Write Command Bank A DAy3 Precharge Command Bank B Don’t Care *tWR>tWR (min.) Confidential DAy0 36 Rev. 2 Feb. /2014 AS4C8M16S Figure 31.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Activate Command Bank A Ax1 Ax2 Ax3 DAy0 DAy1 Read Command Bank A Write Command Bank A DAy3 The Write Data is Masked with a Zero Clock Latency Az0 Read Command Bank A Az1 Az3 The Read Data is Masked with a Two Clock Latency Don’t Care Confidential 37 Rev. 2 Feb. /2014 AS4C8M16S Figure 31.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Activate Command Bank A Confidential Ax1 Ax2 Ax3 Read Command Bank A DAy0 DAy1 Write Command Bank A 38 DAy3 Az0 The Write Data is Masked with a Zero Clock Read Latency Command Bank A Rev. 2 Az1 Az3 The Read Data is Masked with a Two Clock Latency Don’t Care Feb. /2014 AS4C8M16S Figure 32.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T5 T6 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBx CAy RBx CBw CBx Ax3 Bw0 CBy CAy CBz tRCD DQM tAC DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Activate Command Bank B Ax2 Read Command Bank B Bw1 Read Command Bank B Bx0 Bx1 Read Command Bank B By0 By1 Read Command Bank A Ay0 Ay1 Read Command Bank B Bz0 Bz1 Precharge Command Bank A Bz2 Bz3 Precharge Command Bank B Don’t Care Confidential 39 Rev. 2 Feb. /2014 AS4C8M16S Figure 32.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBx CAx RBx CBx CBy CBz CAy tRCD DQM tAC DQ Hi-Z Ax0 Activate Command Bank A Confidential Read Command Bank A Activate Command Bank B Ax1 Ax2 Read Command Bank B Ax3 Bx0 Read Command Bank B Bx1 By0 Read Command Bank B By1 Bz0 Read Command Bank A Bz1 Ay0 Precharge Command Bank B Ay1 Ay2 Ay3 Precharge Command Bank A Don’t Care 40 Rev. 2 Feb. /2014 AS4C8M16S Figure 33. Interleaved Column Write Cycle (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBw CAx RBw CBw CBx CBy CAy CBz tWR tRCD tWR DQM tRRD>tRRD (min) DQ Hi-Z DAx0 Activate Command Bank A Confidential DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 Write Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank B 41 DBy1 Write Command Bank B DAy0 DAy1 DBz0 Write Command Bank A DBz1 DBz2 DBz3 Write Command Bank B Precharge Command Bank A Precharge Command Bank B Don’t Care Rev. 2 Feb. /2014 AS4C8M16S Figure 34.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE Begin Auto Precharge Bank B High Begin Auto Precharge Bank A CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBx CAx RBy RBx CBx CAy RBy CBy RAz tRP DQM DQ RAz Hi-Z Activate Command Bank A Ax0 Read Command Bank A Ax1 Activate Command Bank B Ax2 Ax3 Bx0 Read with Auto Precharge Command Bank B Bx1 Bx2 Bx3 Read with Auto precharge Command Bank A Ay0 Ay1 Ay2 Activate Command Bank B Ay3 By0 By1 By2 Read with Activate Auto Precharge Command Command Bank A Bank B Don’t Care Confidential 42 Rev. 2 Feb. /2014 AS4C8M16S Figure 34.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE Begin Auto Precharge Bank A Begin Auto Precharge Bank B High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBy RBx CAx RBx CBx CAy RBy CBy tRP DQM DQ Hi-Z Activate Command Bank A Confidential Ax0 Read Command Bank A Activate Command Bank B Ax1 Ax2 Ax3 Bx0 Read with Auto Precharge Command Bank B Bx1 Bx2 Read with Auto Precharge Command Bank A Bx3 Ay0 Ay1 Activate Command Bank B Ay2 Ay3 By0 By1 By2 Read with Auto Precharge Command Bank B Don’t Care 43 Rev. 2 Feb. /2014 AS4C8M16S Figure 35. Auto Precharge after Write Burst (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE Begin Auto Precharge Bank A Begin Auto Precharge Bank B High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBy RBx CAx RBx CBx CAy RBy CBy tDAL DQM DQ Hi-Z Activate Command Bank A Confidential DAx0 DAx1 DAx2 Write Command Bank A Activate Command Bank B DAx3 DBx0 DBx1 DBx2 DBx3 Write with Auto Precharge Command Bank B DAy0 DAy1 DAy2 Write with Auto Precharge Command Bank A DAy3 DBy0 DBy1 DBy2 Activate Command Bank B DBy3 Write with Auto Precharge Command Bank B Don’t Care 44 Rev. 2 Feb. /2014 AS4C8M16S Figure 36.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBy RBx CAx RBx CBx RBy tRP DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 The burst counter wraps Activate Read Command from the highest order Command page address back to zero Bank B Bank B during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Bursting beginning with the starting address Confidential 45 Bx+4 Bx+5 Bx+6 Precharge Command Bank B Activate Command Bank B Burst Stop Command Don’t Care Rev. 2 Feb. /2014 AS4C8M16S Figure 36.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBy RBx CAx RBx CBx RBy tRP DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Activate Command Bank B Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Bx+3 Bx+4 Bx+5 Precharge Command Bank B Burst Stop Command Activate Command Bank B Don’t Care Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Bursting beginning with the starting address Confidential 46 Rev. 2 Feb. /2014 AS4C8M16S Figure 37. Full Page Write Cycle (Burst Length=Full Page) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RBy RBx CAx RBx CBx RBy DQM Data is ignored DQ Hi-Z Activate Command Bank A Confidential DAx DAx+1 Write Command Bank A DAx+2 DAx+3 DAx-1 DAx DAx+1 Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 47 Precharge Command Bank B Burst Stop Command Rev. 2 Activate Command Bank B Don’t Care Feb. /2014 AS4C8M16S Figure 38. Byte Read and Write Operation (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx CAy CAz LDQM UDQM DQ0-DQ7 Ax0 DQ8-DQ15 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax1 Ax2 Upper Byte is masked DAy1 Ax3 DAy0 Lower Byte is masked DAy1 Write Command Bank A Day2 DAy3 Upper Byte is masked Az0 Read Command Bank A Az1 Az2 Az1 Az2 Lower Byte is masked Az3 Lower Byte is masked Don’t Care Confidential 48 Rev. 2 Feb. /2014 AS4C8M16S Figure 39. Random Row Read (Interleaving Banks) (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B High Begin Auto Precharge Bank A CS# RAS# CAS# WE# BA0,1 A10 RBu A0-A9, A11 RBu RAu CBu RAu CAu RBw RAv RBv RBv CBv tRP RAv CAv RBw tRP tRP DQM DQ Bu0 Activate Command Bank B Confidential Activate Command Bank A Read Bank B with Auto Precharge Bu1 Bu2 Bu3 Read Bank A with Auto Precharge Au0 Au1 Au2 Activate Command Bank B 49 Au3 Bv0 Activate Command Bank A Read Bank B with Auto Precharge Bv1 Bv2 Bv3 Read Bank A with Auto Precharge Av0 Av1 Av2 Av3 Activate Command Bank B Don’t Care Rev. 2 Feb. /2014 AS4C8M16S Figure 40. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0-A9, A11 RAx RBx RBw CAx CBx CBy CAy CAz CBz RBw tRP DQM tRRD DQ Hi-Z tRCD Ax0 Activate Command Bank A Confidential Ax1 Bx0 Activate Read Command Command Bank B Bank B Read Read Command Command Bank A Bank A Ay0 Ay1 Read Command Bank B By0 By1 Read Command Bank A Az0 Az1 Az2 Read Command Bank B Bz0 Bz1 Bz2 Precharge Activate Command Bank B Command (Precharge Temination) Bank B Don’t Care 50 Rev. 2 Feb. /2014 AS4C8M16S Figure 41. Full Page Random Column Write (Burst Length=Full Page) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0-A9, A11 RAx RBx RBw CAx CBx CBy CAy CAz CBz RBw tWR tRP DQM tRRD DQ Hi-Z DAx0 DAx1 Activate Command Bank A Confidential tRCD Activate Command Bank B Write Command Bank A DBx0 DAy0 DAy1 DBy0 DBy1 Write Command Bank B Write Command Bank A Write Command Bank B DAz0 DAz1 Write Command Bank A DAz2 DBz0 DBz1 Write Command Bank B DBz2 Precharge Activate Command Bank B Command (Precharge Temination) Bank B Write Data are masked 51 Rev. 2 Don’t Care Feb. /2014 AS4C8M16S Figure 42. Precharge Termination of a Burst (Burst Length=4, 8 or Full Page, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx RAy CAx RAz RAy tWR CAy RAz tRP tRP DQM DQ DAx0 DAx1 Activate Command Bank B Confidential Precharge Write Command Command Bank A Bank A Precharge Termination of a Write Burst Write Data are masked Ay0 Activate Command Bank A Read Command Bank A Ay1 Precharge Command Bank A Ay2 Activate Command Bank A Precharge Termination of a Read Burst Don’t Care 52 Rev. 2 Feb. /2014 AS4C8M16S Figure 43. 54 Pin TSOP II Package Outline Drawing Information 28 HE E 0.254 54 Tq L L1 1 27 B S Symbol A A1 A2 B C D E e HE L L1 S y ȧ e Min --0.002 0.035 0.010 0.004 0.87 0.395 --0.455 0.016 ----0± y C A1 A2 A D L L1 Dimension in inch Nom Max Min Dimension in mm Nom Max ----0.039 0.014 0.006 0.875 0.400 0.031 0.463 --0.032 0.028 ----- 0.047 0.008 0.043 0.018 0.008 0.88 0.405 --0.471 0.024 ----0.004 8± --0.05 0.9 0.25 0.12 22.09 10.03 --11.56 0.4 ------0± ----1.0 0.35 0.165 22.22 10.16 0.8 11.76 0.5 0.84 0.71 ----- 1.2 0.2 1.1 0.45 0.21 22.35 10.29 --11.96 0.6 ----0.1 8± Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension: mm Confidential 53 Rev. 2 Feb. /2014 AS4C8M16S Figure 44. 54 Ball TFBGA Package Outline Drawing Information Bottom View TOP View Side View Symbol A A1 A2 c D E D1 E1 e b F Confidential Dimension in inch Min Nom Max Dimension in mm Min Nom Max -- -- 0.047 -- -- 1.20 0.012 0.024 0.007 0.311 0.311 ---0.016 -- 0.014 0.026 0.008 0.315 0.315 0.252 0.252 0.031 0.018 0.126 0.016 0.028 0.010 0.319 0.319 ---0.020 -- 0.30 0.61 0.17 7.90 7.90 ---0.40 -- 0.35 0.66 0.21 8.00 8.00 6.40 6.40 0.80 0.45 3.20 0.40 0.71 0.25 8.10 8.10 ---0.50 -- 54 Rev. 2 Feb. /2014 AS4C8M16S Confidential 55 Rev. 2 Feb. /2014