OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
FEATURES
GENERAL DESCRIPTION
Fast access time : 35/55ns
Low power consumption:
Operating current : 12/10/7mA (TYP.)
Standby current : 1µA (TYP.)
Single 2.7V ~ 5.5V power supply
All outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 1.5V (MIN.)
Lead free and green package available
Package : 32-pin 450 mil SOP
32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
The AS6C1008 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C1008 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The AS6C1008-55 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product Family
AS6C1008
Operating Temperature
-40 ~ 85℃
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A16
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
OCTOBER/2007, V 1.a
128Kx8
MEMORY ARRAY
Vcc Range
2.7 ~ 5.5V
Speed
35/55ns
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A16
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#, CE2
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Alliance Memory Inc.
Page 1 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
PIN CONFIGURATION
1
32
Vcc
2
31
A15
A14
3
30
CE2
A12
4
29
WE#
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
AS6C1008
NC
A16
25
A11
24
OE#
23
A10
22
CE#
21
DQ7
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
Vss
16
17
DQ3
A11
A9
A8
A13
WE#
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS6C1008
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
TSOP-I/STSOP
SOP/P-DIP
A
A0
A1
CE2
A3
A6
A8
B
DQ4
A2
WE#
A4
A7
DQ0
C
DQ5
NC
A5
D
Vss
Vcc
E
Vcc
Vss
F
DQ6
NC
NC
G
DQ7 OE#
CE#
A16
A15
DQ3
A11
A12
A13
A14
5
6
H
A9
A10
1
2
3
4
TFBGA
DQ1
DQ2
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Terminal Voltage with Respect to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
OCTOBER/2007, V 1.a
SYMBOL
VTERM
RATING
-0.5 to 7.0
UNIT
V
TA
-40 to 85(I grade)
℃
TSTG
PD
IOUT
-65 to 150
1
50
260
℃
W
mA
℃
TSOLDER
Alliance Memory Inc.
Page 2 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
X
L
L
L
CE2
X
L
H
H
H
OE#
X
X
H
L
X
WE#
X
X
H
H
L
SUPPLY CURRENT
ISB1
ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
I/O OPERATION
High-Z
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
PARAMETER
Supply Voltage
VCC
2.7
*1
Input High Voltage
VIH
0.7*Vcc
*2
Input Low Voltage
VIL
- 0.2
VCC ≧ VIN ≧VSS
Input Leakage Current
ILI
-1
Output Leakage
VCC ≧ VOUT ≧ VSS,
-1
ILO
Output Disabled
Current
Output High Voltage
VOH IOH = -1mA
2.2
Output Low Voltage
VOL IOL = 2mA
Cycle time = Min.
- 35
CE# = VIL and CE2 = VIH, - 55
ICC
II/O = 0mA
Average Operating
Cycle time = 1µs
Power supply Current
CE#≦0.2V and CE2≧VCC-0.2V,
ICC1
II/O = 0mA
other pins at 0.2V or VCC-0.2V
-SL
CE# ≧VCC-0.2V
or
CE2≦0.2V
-SLE/-SLI
Standby Power
ISB1
Other pins at 0.2V
Supply Current
-LL
or Vcc-0.2V
-LLE/-LLI
-
TYP.
3.0
-
*4
MAX.
5.5
VCC+0.3
0.6
1
UNIT
V
V
V
µA
-
1
µA
2.7
12
10
0.4
80
60
V
V
mA
mA
1
10
mA
1
1
1
1
10
10
20
50
µA
µA
µA
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 3 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
CAPACITANCE (TA = 25 C, f = 1.0MHz)
O
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
MAX
6
8
-
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
AS6C1008
MIN.
MAX.
35
35
35
25
10
5
15
15
10
-
UNIT
AS6C1008
MIN.
MAX.
35
30
30
0
25
0
20
0
5
15
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 4 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 5 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
tAS
tWP
tWR
WE#
tWHZ
Dout
T OW
High-Z
(4)
(4)
tDW
tDH
Data Valid
Din
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
CE2
tWP
WE#
tWHZ
Dout
(4)
High-Z
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 6 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
tCDR
TEST CONDITION
CE# ≧ VCC - 0.2V
or CE2 ≧ 0.2V
-SL
VCC = 1.5V
-SLE/-SLI
CE# ≧ VCC - 0.2V
or CE2 ≧ 0.2V
-LL
others at 0.2V or Vcc-0.2V -LLE/-LLI
See Data Retention
Waveforms (below)
MIN.
TYP.
MAX.
UNIT
1.5
-
5.5
V
-
0.5
0.5
0.5
0.5
8
8
12
30
µA
µA
µA
µA
0
-
-
ns
tRC*
-
-
ns
tR
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
V DR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
V IH
tR
CE# ≧ V cc-0.2V
V IH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
V DR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE2
tR
CE2 ≦ 0.2V
V IL
OCTOBER/2007, V 1.a
V IL
Alliance Memory Inc.
Page 7 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
E1
e
L
L1
S
y
?
OCTOBER/2007, V 1.a
INCH.(BASE)
MM(REF)
0.118 (MAX)
0.004(MIN)
0.111(MAX)
0.016(TYP)
0.008(TYP)
0.817(MAX)
0.445 ±0.005
0.555 ±0.012
0.050(TYP)
0.0347 ±0.008
0.055 ±0.008
0.026(MAX)
0.004(MAX)
o
o
0 -10
2.997 (MAX)
0.102(MIN)
2.82(MAX)
0.406(TYP)
0.203(TYP)
20.75(MAX)
11.303 ±0.127
14.097 ±0.305
1.270(TYP)
0.881 ±0.203
1.397 ±0.203
0.660 (MAX)
0.101(MAX)
o
o
0 -10
Alliance Memory Inc.
Page 8 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
32 pin 600 mil P-DIP Package Outline Dimension
UNIT
SYM.
A1
A2
B
D
E
E1
e
eB
L
S
Q1
INCH(BASE)
MM(REF)
0.001 (MIN)
0.150 ± 0.005
0.018 ± 0.005
1.650 ± 0.005
0.600 ± 0.010
0.544 ± 0.004
0.100 (TYP)
0.640 ± 0.020
0.130 ± 0.010
0.075 ± 0.010
0.070 ± 0.005
0.254 (MIN)
3.810 ± 0.127
0.457 ± 0.127
41.910 ± 0.127
15.240 ± 0.254
13.818 ± 0.102
2.540 (TYP)
16.256 ± 0.508.
3.302 ± 0.254
1.905 ± 0.254
1.778 ± 0.127
Note : D/E1/S dimension do not include mold flash.
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 9 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
O
OCTOBER/2007, V 1.a
INCH(BASE)
MM(REF)
0.047 (MAX)
0.004 ±0.002
0.039 ±0.002
0.008 + 0.002
- 0.001
0.005 (TYP)
0.724 ±0.004
0.315 ±0.004
0.020 (TYP)
0.787 ±0.008
0.0197 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ～5
1.20 (MAX)
0.10 ±0.05
1.00 ±0.05
0.20 + 0.05
-0.03
0.127 (TYP)
18.40 ±0.10
8.00 ±0.10
0.50 (TYP)
20.00 ±0.20
0.50 ±0.10
0.08 ±0.10
0.076 (MAX)
o
o
0 ～5
Alliance Memory Inc.
Page 10 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
cL
12° (2x)
32
16
17
12° (2x)
b
E
e
1
"A"
Seating Plane
D
y
12° (2X)
16
17
0.254
A2
c
A
GAUGE PLANE
A1
0
SEATING PLANE
"A" DATAIL VIEW
1
L
12° (2X)
L1
32
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
O
OCTOBER/2007, V 1.a
INCH(BASE)
MM(REF)
0.049 (MAX)
0.005 ±0.002
0.039 ±0.002
0.008 ±0.01
0.005 (TYP)
0.465 ±0.004
0.315 ±0.004
0.020 (TYP)
0.528±0.008
0.0197 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ～5
1.25 (MAX)
0.130 ±0.05
1.00 ±0.05
0.20±0.025
0.127 (TYP)
11.80 ±0.10
8.00 ±0.10
0.50 (TYP)
13.40 ±0.20.
0.50 ±0.10
0.8 ±0.10
0.076 (MAX)
o
o
0 ～5
Alliance Memory Inc.
Page 11 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
36 ball 6mm × 8mm TFBGA Package Outline Dimension
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 12 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
ORDERING INFORMATION
Alliance
Organization
VCC
Range
AS6C1008-55SIN
128K x 8
2.7 - 5.5V
32 pin 450mil SOP
Industrial ~ -40 C - 85 C
55
AS6C1008-55TIN
128K x 8
2.7 - 5.5V
32 pin TSOP-1(8x20mm)
Industrial ~ -40 C - 85 C
55
AS6C1008-55STIN
128K x 8
2.7 - 5.5V
32 pin stSOP (8x13.3mm)
Industrial ~ -40 C - 85 C
55
Package
Speed
ns
Operating Temp
PART NUMBERING SYSTEM
AS6C
SRAM prefix
1008
Device Number
10 = 1M
08 = x8
OCTOBER/2007, V 1.a
-55
Access
Time
X
Package Option
32 pin 450mil SOP
32 pin TSOP-1(8x20mm)
32 pin stSOP (8x13.3mm)
Alliance Memory Inc.
X
Temperature
Range
I = Industrial
(-40 to + 85 C)
N
L
N = Lead Free
RoHS
compliant part
super low power
Page 13 of 14
OCTOBER
2007
January 2007
AS6C1008
X 8 BIT
LOW
POWER CMOS SRAM
128K X 8 BIT SUPER512K
LOW POWER
CMOS
SRAM
®
Alliance Memory, Inc
511 Taylor Way,
San Carlos, CA 94070, USA
Phone: 650-610-6800
Fax: 650-620-9211
Copyright © Alliance Memory
All Rights Reserved
www.alliancememory.com
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance.
All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents
Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any
express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to inAlliance's Terms and Conditions of Sale (which are available
from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from
Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or
third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be
expected to result in significant injury to the user, and the inclusion ofAlliance products in such life-supporting systems implies that the manufacturer assumes
all risk of such use and agrees to indemnify Alliance against allclaims arising from such use.
OCTOBER/2007, V 1.a
Alliance Memory Inc.
Page 14 of 14
