AS6C1016-55ZIN

AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Alliance Memory, Inc. Rev. 1.4 Description Initial Issue Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised PACKAGE OUTLINE DIMENSION in page 11 Revised VDR to 1.5V Revised ORDERING INFORMATION in page 12 Revised typo in PRODUCT FAMILY page 1 Deleted E Grade 0 Issue Date Nov.19.2008 May.6.2010 Aug.30.2010 Oct.4.2010 Aug.9.2011 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION  Fast access time : 55ns  Low power consumption: Operating current : 20mA (TYP.) Standby current : 2A (TYP.)  Single 2.7V ~ 5.5V power supply  All outputs TTL compatible  Fully static operation  Tri-state output  Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15)  Data retention voltage : 1.5V (MIN.)  Green package available  Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The AS6C1016 is a 1,048,576-bit low power CMOS static random access memory organized as 65,536 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C1016 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C1016 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C1016(I) Operating Temperature -40 ~ 85℃ Vcc Range Speed 2.7 ~ 5.5V 55/70ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A15 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 2µA 20/18mA SYMBOL DESCRIPTION A0 - A15 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 64Kx16 MEMORY ARRAY COLUMN I/O CONTROL CIRCUIT Alliance Memory, Inc. Rev. 1.4 1 CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM PIN CONFIGURATION 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CE# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 AS6C1016 A4 DQ7 16 29 DQ8 WE# 17 28 NC A15 18 27 A8 A14 19 26 A9 A13 20 25 A10 A12 21 24 A11 NC 22 23 NC TSOP II A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 NC A7 DQ3 Vcc E Vcc DQ12 NC NC DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE# DQ7 A10 H A2 NC A8 A9 A11 1 2 3 4 5 TFBGA NC NC 6 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Alliance Memory, Inc. Rev. 1.4 2 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H X L L L L L L L L X X H H L L L X X X WE# LB# X X H H H H H L L L X H L X L H L L H L UB# X H X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. ICC CE# = VIL , II/O = 0mA - 55 Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs ICC1 CE# = 0.2V , II/O = 0mA Other pins at 0.2V or VCC - 0.2V CE# ≧VCC - 0.2V Standby Power ISB1 Others at 0.2V or LL/LLI Supply Current VCC - 0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V Alliance Memory, Inc. Rev. 1.4 3 MIN. 2.7 2.4 - 0.2 -1 TYP. 3.0 - *4 MAX. 5.5 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.4 - 2.7 - 0.4 V V - 20 60 mA - 4 10 mA - 2 50 µA AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* tBW AS6C1016-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - UNIT AS6C1016-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 50 - UNIT *These parameters are guaranteed by device characterization, but not production tested. Alliance Memory, Inc. Rev. 1.4 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT pF pF AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Alliance Memory, Inc. Rev. 1.4 5 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din Alliance Memory, Inc. Rev. 1.4 tDH Data Valid 6 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Alliance Memory, Inc. Rev. 1.4 7 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time MIN. 1.5 TYP. - MAX. 5.5 UNIT V IDR VCC = 1.5V CE# ≧ VCC - 0.2V LL/LLI Others at 0.2V or VCC-0.2V - 0.5 20 µA tCDR See Data Retention Waveforms (below) 0 - - ns tRC* - - ns tR DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ¡Ù Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (LB#, UB# controlled) VDR ¡Ù 1.5V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# Alliance Memory, Inc. Rev. 1.4 VIH tR LB#,UB# ¡Ù Vcc-0.2V 8 VIH AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION θ 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ Alliance Memory, Inc. Rev. 1.4 DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 0 3 6 9 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension Alliance Memory, Inc. Rev. 1.4 10 AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM ORDERING INFORMATION Alliance Operating Temp Package Speed ns Organization VCC Range AS6C1016-55ZIN 64K x 16 2.7V – 5.5V 44pin TSOP II Industrial ~ -40°C - 85°C 55 AS6C1016-55BIN 64K x 16 2.7V – 5.5V 48ball TFBGA Industrial -40°C - 85°C 55 PART NUMBERING SYSTEM AS6C 1016 -55 Low power SRAM prefix Device Number 10 = 1M 16 = x16 Access Time Alliance Memory, Inc. Rev. 1.4 X X Package Options: T = 44 pin TSOP II B = 48 ball TFBGA Temperature Range: I = Industrial (-40°C to +85°C) 11 N N = Lead Free ROHS Compliant Part AS6C1016 64K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Alliance Memory, Inc. Rev. 1.4 12