AS6C1616-55TIN

APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION The AS6C1616 is a 16,777,216-bit low power CMOS static random access memory organized as 1,048,576 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. Fast access time : 55ns Low power consumption: Operating current : 45/30mA (TYP.) Standby current : 10µA (TYP.) LL-version 4µA (TYP.) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.2V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I The AS6C1616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C1616 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C1616(I) Operating Temperature -40 ~ 85℃ Vcc Range 2.7 ~ 3.6V FUNCTIONAL BLOCK DIAGRAM DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# 55ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 10µA (LL)/4µA(SL) 45/30mA PIN DESCRIPTION Vcc Vss A0-A19 Speed SYMBOL DESCRIPTION A0 - A19 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 1024Kx16 MEMORY ARRAY CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT APRIL/2010 V1.b ALLIANCE MEMORY PAGE 1 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM PIN CONFIGURATION A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# CE2 NC UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AS6C1616 A16 NC Vss DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 TSOP-I ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 TA -40 to 85(I grade) TSTG PD IOUT -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. APRIL/2010 V1.b ALLIANCE MEMORY PAGE 2 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM TRUTH TABLE MODE CE# CE2 OE# WE# LB# UB# H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L Standby Output Disable Read Write Note: H = VIH, L = VIL, X = Don't care. I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High – Z High – Z ISB,ISB1 High – Z High – Z High – Z High – Z High – Z High – Z ICC,ICC1 High – Z High – Z High – Z DOUT ICC,ICC1 High – Z DOUT DOUT DOUT High – Z DIN ICC,ICC1 High – Z DIN DIN DIN DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. CE# = VIL and CE2 = VIH ICC - 55 II/O = 0mA Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V ICC1 II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL ISB Other pins at VIL or VIH ISB1 CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V *5 SLI TYP. 3.0 - *4 MAX. 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 45 60 mA - 8 16 mA - 0.3 2 mA - 10 100 µA 25℃ - 4 6 µA 40℃ - 4 6 µA - 4 40 µA LLI Standby Power Supply Current MIN. 2.7 2.2 - 0.2 -1 SLI Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. APRIL/2010 V1.b ALLIANCE MEMORY PAGE 3 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM 4. Typical values are included for reference only and are not guaranteed or tested. CC A Typical values are measured at VCC = VCC(TYP.) and T = 25℃ 5. This parameter is measured at V = 3.0V CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. AS6C1616-55 tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH tBA tBHZ tBLZ SYM. AS6C1616-55 UNIT tWC tAW tCW tAS tWP tWR tDW tDH tOW tWHZ tBW *These parameters are guaranteed by device characterization, but not production tested. APRIL/2010 V1.b ALLIANCE MEMORY PAGE 4 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tBLZ tCLZ Dout High-Z tOLZ tOE tOH tOHZ tBHZ tCHZ Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. APRIL/2010 V1.b ALLIANCE MEMORY PAGE 5 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din APRIL/2010 V1.b tDH Data Valid ALLIANCE MEMORY PAGE 6 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tCW tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. APRIL/2010 V1.b ALLIANCE MEMORY PAGE 7 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V MIN. 1.2 TYP. - MAX. 3.6 UNIT V - 4 80 µA 25℃ - 2.5 5 µA 40℃ - 2.5 5 µA - 2.5 40 µA 0 - - ns tRC* - - ns LLI Data Retention Current IDR VCC = 1.2V CE# ≧VCC-0.2V or CE2≦0.2V other pins at 0.2V or VCC-0.2V SLI SLI Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR tR See Data Retention Waveforms (below) DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 VIL tR CE2 ≦ 0.2V VIL Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# APRIL/2010 V1.b VIH tR LB#,UB# ≧ Vcc-0.2V ALLIANCE MEMORY VIH PAGE 8 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension APRIL/2010 V1.b ALLIANCE MEMORY PAGE 9 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM ORDERING INFORMATION Alliance Organization AS6C1616-55TIN 1024K x 16 VCC Range Package Operating Temp Speed ns 2.7 - 3.6V 48pin TSOP-I Industrial ~ -40 F - 85 F 55 PART NUMBERING SYSTEM AS6C 1616 -55 X X N Temperature Device Number low power SRAM prefix APRIL/2010 V1.b 16 =16M 16 =x16 Range Access Time Package Option 48pin TSOP-I ALLIANCE MEMORY I = Industrial (-40 to + 85 C) N = Lead Free RoHS compliant part PAGE 10 of 11 APRIL 2010 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM Alliance Memory, Inc 551 Taylor Way, Suite 1 San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2010 Alliance Memory, Inc. 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