AS6C1616-55TINLTR

AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 REVISION HISTORY Revision Rev. 1.0 Description Initial Issue Issue Date Jan. 09. 2012 Alliance Memory, Inc. 0 AS6C1616-55TINL Rev. 1.0 16M Bits LOW POWER CMOS SRAM FEATURES The AS6C1616 is a 16,777,216-bit low power CMOS static random access memory organized as 1,048,576 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.  Fast access time : 55ns  Low power consumption: Operating current : 45mA (TYP.) Standby current : 4A (TYP.) SL-version  Single 2.7V ~ 3.6V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data byte control : LB# controlled DQ0 ~ DQ7 UB# controlled DQ8 ~ DQ15  Data retention voltage : 1.2V (MIN.)  Green package available  Package : 48-pin 12mm x 20mm TSOP-I The AS6C1616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C1616 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible GENERAL DESCRIPTION PRODUCT FAMILY Product Family AS6C1616(I) Operating Temperatur e -40 ~ 85℃ Power Dissipation Vcc Range Speed 2.7 ~ 3.6V 55ns FUNCTIONAL BLOCK DIAGRAM Standby(ISB1,TYP.) Operating(Icc,TYP.) 4µA(SL) 45mA PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A19 Address Inputs(word mode) A-1 - A19 Address Inputs(byte mode) DQ0 – DQ15 Data Inputs/Outputs Alliance Memory, Inc. 1 CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 PIN CONFIGURATION ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V -40 to 85(I grade) ℃ -65 to 150 1 50 ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Alliance Memory, Inc. 2 AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 TRUTH TABLE MODE Standby Output Disable Read Write Byte# Read Byte # Write Note: CE# CE2 BYTE# OE# H X X L L L L L L L L L X L X H H H H H H H H H X X H H H L H H H H H H L H L H I/O OPERATION DQ0-DQ7 DQ8-DQ14 DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z High – Z DOUT DOUT DOUT DOUT DOUT DIN High – Z High – Z High – Z DIN DIN DIN DIN DIN SUPPLY CURRENT WE# LB# UB# X X X H H H L L L X X X X X X H H H H H H L L L X X H L X X L H L L H L X X H X L X H L L H L L L L H X X Dout High – Z A-1 ICC,ICC1 L X L X X Din High – Z A-1 ICC,ICC1 ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. CE# = VIL and CE2 = VIH ICC - 55 II/O = 0mA Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V ICC1 II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL ISB Other pins at VIL or VIH 25℃ CE# ≧VCC-0.2V Standby Power *5 SLI Supply Current or CE2≦0.2V 40℃ ISB1 Other pins at 0.2V SLI or VCC-0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V Alliance Memory, Inc. 3 MIN. 2.7 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 45 60 mA - 8 16 mA - 0.3 2 mA - 4 4 10 10 µA µA - 4 40 µA AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* tBW AS6C1616 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - UNIT AS6C1616 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 45 - UNIT *These parameters are guaranteed by device characterization, but not production tested. Alliance Memory, Inc. 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT pF pF AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Alliance Memory, Inc. 5 AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Alliance Memory, Inc. 6 AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Alliance Memory, Inc. 7 AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. VCC for Data Retention VDR 1.2 CE# ≧ VCC - 0.2V or CE2≦0.2V SL 25℃ VCC = 1.2V SLI 40℃ Data Retention Current IDR CE# ≧VCC-0.2V or CE2≦0.2V SL Other pins at 0.2V or VCC-0.2V SLI Chip Disable to Data See Data Retention tCDR 0 Retention Time Waveforms (below) Recovery Time tR tRC* tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ¡Ù 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ¡Ù Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ¡Ù 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 ¡Ø 0.2V VIL VIL Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) VDR ¡Ù 1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# VIH tR LB#,UB# ¡Ù Vcc-0.2V Alliance Memory, Inc. 8 VIH TYP. 2.5 2.5 2.5 2.5 MAX. 3.6 10 10 30 40 UNIT V µA µA µA µA - - ns - - ns AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 PACKAGE OUTLINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension Alliance Memory, Inc. 9 AS6C1616-55TINL 16M Bits LOW POWER CMOS SRAM Rev. 1.0 ORDERING INFORMATION Alliance Organization VCC Range Package AS6C1616-55TINL 1024K x 16 2.7V – 3.6V 48pin TSOP I Alliance Memory, Inc. 10 Operating Temp Industrial ~ -40°C - 85°C Speed ns 55