AUGUST
2007
January 2007
AS6C2008A
X8
BIT SRAM
LOW POWER CMOS SRAM
256K X 8 BIT LOW512K
POWER
CMOS
FEATURES
GENERAL DESCRIPTION
Fast access time : 55ns
Low power consumption:
Operating current : 20/18mA (TYP.)
Standby current : 2µA (TYP.)
Single 2.7V ~ 5.5V power supply
All outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 2.0V (MIN.)
Lead free and green package available
Package : 32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
32-pin 450 mil SOP
32-pin 600 mil P-DIP
36-ball 6mm x 8mm TFBGA
The AS6C2008A is a 2,097,152-bit low power
CMOS static random access memory organized as
262,144 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C2008A is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The AS6C2008A operates from a single power
supply of 2.7V ~ 5.5V and all outputs are fully TTL
compatible
PRODUCT FAMILY
Product
Family
AS6C2008A(LLI)
Operating
Temperature
-40 ~ 85℃
Vcc Range
2.7 ~ 5.5V
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A17
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
AUGUST/2007, V 1.0
256Kx8
MEMORY ARRAY
Speed
55ns
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
2µA(LL)
20/18mA
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A17
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#, CE2
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Alliance Memory Inc.
Page 1 of 15
!5'534
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1
32
Vcc
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE#
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
13
DQ1
DQ2
Vss
AS6C2008A
A17
25
A11
24
OE#
23
A10
22
CE#
21
DQ7
20
DQ6
14
19
DQ5
15
18
DQ4
16
17
DQ3
A11
A9
A8
A13
WE#
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS6C2008A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
TSOP-I/STSOP
SOP/P-DIP
!
!
!
#%
!
!
!
"
$1
!
7%
!
!
$1
#
$1
.#
!
$
6SS
6CC
%
6CC
6SS
&
$1
.#
!
'
$1 /%
#%
!
!
$1
!
!
!
!
(
!
!
4&"'!
$1
$1
!5'534 6
!LLIANCE-EMORY)NC
0AGEOF
AUGUST
2007
January 2007
AS6C2008A
X8
BIT SRAM
LOW POWER CMOS SRAM
256K X 8 BIT LOW512K
POWER
CMOS
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
SYMBOL
VT1
VT2
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
UNIT
V
V
TA
-40 to 85(I grade)
℃
TSTG
PD
IOUT
-65 to 150
1
50
260
℃
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
TSOLDER
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
CE2
OE#
WE#
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
X
X
H
H
L
I/O OPERATION
High-Z
High-Z
High-Z
DOUT
DIN
SUPPLY CURRENT
ISB1
ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
H = VIH, L = VIL, X = Don't care.
AUGUST/2007, V 1.0
Alliance Memory Inc.
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39-"/,
4%34#/.$)4)/.
0!2!-%4%2
Supply Voltage
VCC
*1
Input High Voltage
VIH
*2
Input Low Voltage
VIL
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
Output Leakage
VCC ≧ VOUT ≧ VSS,
ILO
Output Disabled
Current
Output High Voltage
VOH IOH = -1mA
Output Low Voltage
VOL
IOL = 2mA
Cycle time = Min., II/O = 0mA - 55
ICC
CE# =0.2V and CE2=VCC-0.2V
other pins at 0.2V or VCC-0.2V - 70
Average Operating
Power supply Current
Cycle time = 1µs, II/O = 0mA
ICC1 CE#≦0.2V and CE2≧VCC-0.2V,
other pins at 0.2V or VCC-0.2V
CE# ≧VCC-0.2V
Standby Power
ISB1
or CE2≦0.2V
Supply Current
other pins at 0.2V or VCC-0.2V
*4
-). 490 -!8
2.7
3.0
5.5
0.7* VCC
VCC+0.3
- 0.2
0.6
-1
1
5.)4
V
V
V
µA
-1
-
1
µA
2.4
-
2.7
-
0.4
V
V
-
20
60
mA
-
18
50
mA
-
4
10
mA
-
2
50
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
#!0!#)4!.#% 4! O#F -(Z
0!2!-%4%2
Input Capacitance
Input/Output Capacitance
39-"/,
CIN
CI/O
-).
-
-!8
6
8
5.)4
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
!#4%34#/.$)4)/.3
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
!5'534 6
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA
!LLIANCE-EMORY)NC
0AGEOF
AUGUST
2007
January 2007
AS6C2008A
X8
BIT SRAM
LOW POWER CMOS SRAM
256K X 8 BIT LOW512K
POWER
CMOS
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
AS6C2008A-55
UNIT
SYM.
AS6C2008A-55
UNIT
tRC
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW
tWHZ
*These parameters are guaranteed by device characterization, but not production tested.
AUGUST/2007, V 1.0
Alliance Memory Inc.
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2%!$#9#,%(Address Controlled) (1,2)
T2#
!DDRESS
T!!
$OUT
T/(
0REVIOUS$ATA6ALID
$ATA6ALID
2%!$#9#,%(CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
!5'534 6
!LLIANCE-EMORY)NC
0AGEOF
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T7#
!DDRESS
T!7
#%
T#7
#%
T!3
T70
T72
7%
T7(:
$OUT
4 /7
(IGH
:
T$7
$IN
T$(
$ATA6ALID
72)4%#9#,% (CE# and CE2 Controlled) (1,2,5,6)
T7#
!DDRESS
T!7
#%
T!3
T72
T#7
#%
T70
7%
T7(:
$OUT
(IGH
:
T$7
$IN
T$(
$ATA6ALID
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
!5'534 6
!LLIANCE-EMORY)NC
0AGEOF
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0!2!-%4%2
39-"/,
4%34#/.$)4)/.
CE#
VCC - 0.2V
VDR
or CE2 0.2V
VCC = 2.0V
CE#
VCC - 0.2V
IDR
or CE2
0.2V
other pins at 0.2V or VCC-0.2V
See Data Retention
tCDR
Waveforms (below)
tR
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
-).
490
-!8
5.)4
2.0
-
5.5
V
-
0.5
20
µA
0
-
-
ns
tRC*
-
-
ns
$!4!2%4%.4)/.7!6%&/2-
,OW6CC$ATA2ETENTION7AVEFORM (CE# controlled)
VDR
Vcc
2.0V
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE#
Vcc-0.2V
VIH
,OW6CC$ATA2ETENTION7AVEFORM (CE2 controlled)
VDR
Vcc
2.0V
Vcc(min.)
Vcc(min.)
tCDR
CE2
tR
CE2
0.2V
VIL
!5'534 6
VIL
!LLIANCE-EMORY)NC
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PINMMXMM43/0
)0ACKAGE/UTLINE$IMENSION
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
/
!5'534 6
INCH(BASE)
MM(REF)
0.047 (MAX)
0.004 ±0.002
0.039 ±0.002
0.008 + 0.002
- 0.001
0.005 (TYP)
0.724 ±0.004
0.315 ±0.004
0.020 (TYP)
0.787 ±0.008
0.0197 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ～5
1.20 (MAX)
0.10 ±0.05
1.00 ±0.05
0.20 + 0.05
-0.03
0.127 (TYP)
18.40 ±0.10
8.00 ±0.10
0.50 (TYP)
20.00 ±0.20
0.50 ±0.10
0.08 ±0.10
0.076 (MAX)
o
o
0 ～5
!LLIANCE-EMORY)NC
0AGEOF
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HD
cL
12° (2x)
32
16
17
12° (2x)
b
E
e
1
"A"
Seating Plane
D
y
12° (2X)
16
17
0.254
A2
c
A
GAUGE PLANE
A1
0
SEATING PLANE
"A" DATAIL VIEW
1
L
12° (2X)
L1
32
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
O
AUGUST 6
INCH(BASE)
MM(REF)
0.049 (MAX)
0.005 ±0.002
0.039 ±0.002
0.008 ±0.01
0.005 (TYP)
0.465 ±0.004
0.315 ±0.004
0.020 (TYP)
0.528±0.008
0.0197 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ～5
1.25 (MAX)
0.130 ±0.05
1.00 ±0.05
0.20±0.025
0.127 (TYP)
11.80 ±0.10
8.00 ±0.10
0.50 (TYP)
13.40 ±0.20.
0.50 ±0.10
0.8 ±0.10
0.076 (MAX)
o
o
0 ～5
!LLIANCE-EMORY)NC
0AGEOF
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UNIT
SYM.
A
A1
A2
b
c
D
E
E1
e
L
L1
S
y
/
!5'534 6
INCH.(BASE)
MM(REF)
0.118 (MAX)
0.004(MIN)
0.111(MAX)
0.016(TYP)
0.008(TYP)
0.817(MAX)
0.445 ±0.005
0.555 ±0.012
0.050(TYP)
0.0347 ±0.008
0.055 ±0.008
0.026(MAX)
0.004(MAX)
o
o
0 -10
2.997 (MAX)
0.102(MIN)
2.82(MAX)
0.406(TYP)
0.203(TYP)
20.75(MAX)
11.303 ±0.127
14.097 ±0.305
1.270(TYP)
0.881 ±0.203
1.397 ±0.203
0.660 (MAX)
0.101(MAX)
o
o
0 -10
!LLIANCE-EMORY)NC
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$)00ACKAGE/UTLINE$IMENSION
UNIT
SYM.
A1
A2
B
D
E
E1
e
eB
L
S
Q1
INCH(BASE)
MM(REF)
0.001 (MIN)
0.150 ± 0.005
0.018 ± 0.005
1.650 ± 0.005
0.600 ± 0.010
0.544 ± 0.004
0.100 (TYP)
0.640 ± 0.020
0.130 ± 0.010
0.075 ± 0.010
0.070 ± 0.005
0.254 (MIN)
3.810 ± 0.127
0.457 ± 0.127
41.910 ± 0.127
15.240 ± 0.254
13.818 ± 0.102
2.540 (TYP)
16.256 ± 0.508.
3.302 ± 0.254
1.905 ± 0.254
1.778 ± 0.127
Note : D/E1/S dimension do not include mold flash.
AUGUST 6
!LLIANCE-EMORY)NC
0AGEOF
!5'534
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+8")4,/70/7%2#-/332!-
#-/3 32!-
BALLMM§MM4&"'!0ACKAGE/UTLINE$IMENSION
!5'534 6
!LLIANCE-EMORY)NC
0AGEOF
!5'534
*ANUARY
!3#!
+ 8 ") 4 ,/7 0/7%2
+8")4,/70/7%2#-/332!-
#-/3 32!-
/2$%2).').&/2-!4)/.
0!24.5-"%2).'3934%-
AS6C
2008
-55
Device
Number
low power
SRAM prefix
20 = 2M
08 = x8
!5'534 6
Access
Time
X
X
Package Option
S = 32pin 450 mil SOP
Temperature
Range
ST = 32pin sTSOP(8 x 13.4)
I = Industrial
T = 32pin TSOP - 1(8 x 20mm)
(-40 to + 85 C)
!LLIANCE-EMORY)NC
N
N = Lead Free
RoHS
compliant part
0AGEOF
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¸
Alliance Memory, Inc
511 Taylor Way,
San Carlos, CA 94070, USA
Phone: 650-610-6800
Fax: 650-620-9211
#OPYRIGHT¹!LLIANCE-EMORY
!LL2IGHTS2ESERVED
www.alliancememory.com
./6%-"%2 6
!LLIANCE-EMORY)NC
0AGEOF
