AS6C4008-55STIN

AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operating current : 30 mA (TYP.) Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation Tri-state output Data retention voltage :1.5V (MIN.) All products ROHS Compliant Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 36-ball 6mm x 8mm TFBGA 32-pin 400 mil TSOP-II The AS6C4008 is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C4008 is well designed for very low power system applications, and particularly well suited for battery back-up non-volatile memory application. The AS6C4008 op erates from a sing le p owe r sup p ly of 2.7V~ 5.5Vand all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C4008 Operating Temperature -40 ~ +85 ℃ Vcc Range 2.7 ~ 5.5V FUNCTIONAL BLOCK DIAGRAM DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# WE# OE# CONTROL CIRCUIT AUG/09, v 1.4 55ns Power Dissipation Standby(ISB1TYP.) Operating(Icc,TYP.) 4µA(LL) 30mA PIN DESCRIPTION** Vcc Vss A0-A18 Speed 512Kx8 MEMORY ARRAY SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection COLUMN I/O Alliance Memory Inc Page 1 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE# A7 5 28 A13 27 A8 26 A9 AS6C4008 A18 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 25 A11 24 OE# 23 A10 A11 A9 A8 A13 WE# A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AS6C4008 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 TSOP-I/STSOP SOP/ P-DIP A18 1 32 VCC A16 2 31 A15 A14 3 30 A17 4 29 5 28 6 27 7 26 8 25 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 9 AS6C4008 10 24 23 11 22 12 21 13 20 14 19 15 18 16 17 W E# A13 A8 A9 A11 OE# A A0 A1 NC A3 A6 A8 A10 B DQ4 A2 WE# A4 A7 DQ0 CE# C DQ5 NC A5 D Vss E Vcc F DQ6 A18 A17 G DQ7 OE# CE# A16 A15 DQ3 A12 A13 A14 5 6 DQ7 DQ6 Vcc Vss DQ2 DQ5 DQ4 H DQ3 TSOP-II AUG/09, v 1.4 DQ1 Alliance Memory Inc A 9 A10 1 2 A11 3 4 TFBGA Page 2 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS SYMBOL VTERM RATING -0.5 to 6.5 UNIT V 0 to 70(C grade) Operating Temperature Co TA -40 to 85(I grade) Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) TSTG PD IOUT Co -65 to 150 1 50 260 TSOLDER W mA Co *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write CE# H L L L OE# X H L X WE# X H H L SUPPLY CURRENT ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 I/O OPERATION High-Z High-Z DOUT DIN Note: H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage SYMBOL VCC VIH*1 VIL*1 ILI ILO VOH VOL ICC Average Operating Power supply Current ICC1 Standby Power Supply Current ISB1 TEST CONDITION Vcc: 4.5 ~ 5.5V Vcc: 2.7 ~ 4.5V Vcc: 4.5 ~ 5.5V Vcc: 2.7 ~ 4.5V VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -1mA IOL = 2mA Cycle time = Min. - 55 CE# = 0.2V, II/O = 0mA other pins at 0.2V or VCC - 0.2V Cycle time = 1µs CE# = 0.2V, II/O = 0mA other pins at 0.2V or VCC - 0.2V -LL CE# ≧VCC - 0.2V -LLE/-LLI MIN. 2.7 2.4 TYP. 3.0 - *3 MAX. UNIT 5.5 V VCC+0.3 V 2.2 - VCC+0.3 V - 0.2 - 0.8 V - 0.2 -1 - 0.6 1 V µA -1 - 1 µA 2.4 - - 0.4 V V - 30 60 mA - 4 10 mA - 4 4 50 *4 50 *4 µA µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 2. Over/Undershoot specifications are characterized, not 100% tested. 3. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25? 4. 25µA for special request AUG/09, v 1.4 Alliance Memory Inc Page 3 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH AS6C4008-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 - UNIT AS6C4008-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. AUG09 v1.4 Alliance Memory Inc Page 4 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tCLZ Dout High-Z tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than tCLZ , tOHZ is less than tOLZ. AUG09 v1.4 Alliance Memory Inc Page 5 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# TOW tWHZ Dout High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tWP tCW WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. AUG09 v1.4 Alliance Memory Inc Page 6 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V -LL IDR CE# ≧ VCC - 0.2V -LLE/-LLI See Data Retention tCDR Waveforms (below) tR MIN. 1.5 - TYP. 2 2 MAX. 5.5 30 30 UNIT V µA µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧ 1.5V Vcc(min.) Vcc(min.) Vcc tCDR VIH tR CE# ≧ Vcc-0.2V VIH CE # AUG09 v1.4 Alliance Memory Inc Page 7 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 32 pin 450 mil SOP Package Outline Dimension UNIT SYM. A A1 A2 b c D E E1 e L L1 S y Θ AUG09 v1.4 INCH.(BASE) MM(REF) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 ±0.005 0.555 ±0.012 0.050(TYP) 0.0347 ±0.008 0.055 ±0.008 0.026(MAX) 0.004(MAX) o o 0 -10 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 ±0.127 14.097 ±0.305 1.270(TYP) 0.881 ±0.203 1.397 ±0.203 0.660 (MAX) 0.101(MAX) o o 0 -10 Alliance Memory Inc Page 8 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ AUG09 v1.4 INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.50 ±0.10 0.08 ±0.10 0.076 (MAX) o o 0 ～5 Alliance Memory Inc Page 9 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 32 16 17 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 16 17 0.254 c A2 A GAUGE PLANE A1 0 SEATING PLANE L 12° (2X) L1 "A" DETAIL VIEW 1 32 UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ AUG09 v1.4 INCH(BASE) MM(REF) 0.049 (MAX) 0.005 ±0.002 0.039 ±0.002 0.008 ±0.01 0.005 (TYP) 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 1.25 (MAX) 0.130 ±0.05 1.00 ±0.05 0.20±0.025 0.127 (TYP) 11.80 ±0.10 8.00 ±0.10 0.50 (TYP) 13.40 ±0.20. 0.50 ±0.10 0.8 ±0.10 0.076 (MAX) o o 0 ～5 Alliance Memory Inc Page 10 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension AUG09 v1.4 Alliance Memory Inc Page 11 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32-pin 400mil TSOP-Ⅱ Package Outline Dimension AUG/09, v 1.0.a Alliance Memory Inc Page 12 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32 pin 600 mil P-DIP Package Outline Dimension UNIT SYM. A1 A2 B D E E1 e eB L S Q1 INCH(BASE) MM(REF) 0.015 (MIN) 0.155 ± 0.005 0.018 ± 0.005 1.650 ± 0.005 0.600 ± 0.010 0.545 ± 0.005 0.100 (TYP) 0.640 ± 0.020 0.130 ± 0.010 0.075 ± 0.010 0.070 ± 0.005 0.381 (MIN) 3.937 ± 0.127 0.457 ± 0.127 41.910 ± 0.127 15.240 ± 0.254 13.843 ± 0.127 2.540 (TYP) 16.256 ± 0.508. 3.302 ± 0.254 1.905 ± 0.254 1.778 ± 0.127 Note : D/E1/S dimension do not include mold flash. AUG09 v1.4 Alliance Memory Inc Page 13 of 14 AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION Alliance Organization VCC Package AS6C4008-55PCN 512k x 8 5V 32pin 600mil DIP AS6C4008-55SIN 512k x 8 5V 32pin 450mil SOP AS6C4008-55TIN 512k x 8 5V 32pin TSOP 1 (8 x 20 mm) AS6C4008-55STIN 512k x 8 5V 32pin sTSOP (8 x 13.4 mm) AS6C4008-55BIN 512k x 8 5V 36pin TFBGA (6mm x 8mm) AS6C4008-55ZIN 512k x 8 5V 32-pin 400mil TSOP 11 Operating Temp Commercial ~ 0º C to 70º C Industrial ~ -40ºC to 85º C Industrial ~ -40ºC to 85º C Industrial ~ -40ºC to 85º C Industrial ~ -40ºC to 85º C Industrial ~ -40ºC to 85º C Speed ns 55 55 55 55 55 55 PART NUMBERING SYSTEM AS6C 4008 - 55 X Package Options: P = 32 pin 600 mil P-DIP S = 32 pin 450 mil SOP T = 32 pin TSOP 1 (8mm x 20 mm) low Device Z = 32-pin 400mil TSOP 11 power Number SRAM 40 = 4M Access ST = 32 pin sTSOP (8mm x 13.4 mm) prefix 08 = by 8 Time B = 36 pin TFBGA (6mm x 8mm) AUG09 v1.4 Alliance Memory Inc X N Temperature Range: C = Commercial N = Lead (0ºC to +70º C) Free ROHS I = Industrial Compliant (-40º to +85º C) Part Page 14 of 14