AS6C4008A-55TINTR

AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 REVISION HISTORY Revision Rev. 1.12 Description Initial Issue Issue Date May 15, 2012 Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 0 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 FEATURES GENERAL DESCRIPTION  Fast access time : 55ns  Low power consumption: Operating current : 30mA (TYP.) Standby current : 1A (TYP.) SL-version  Single 2.7V ~ 3.6V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data retention voltage : 1.5V (MIN.)  Green package available  Package : 32-pin 450 mil SOP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 36-ball 6mm x 8mm TFBGA 32-pin 600 mil P-DIP 32-pin 400 mil TSOP-II The AS6C4008A is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C4008A is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The AS6C4008A operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C4008A Operating Temperature -40 ~ 85℃ Vcc Range Speed 2.7 ~ 3.6V 55ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A18 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# WE# OE# CONTROL CIRCUIT Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 1µA(SL) 30mA 512Kx8 MEMORY ARRAY COLUMN I/O PIN CONFIGURATION Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 1 SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ0 DQ1 AS6C4008A A18 26 A9 25 A11 24 OE# 23 A10 22 CE# 21 DQ7 13 20 DQ6 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 A11 A9 A8 A13 WE# A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AS6C4008A OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 TSOP-I/STSOP SOP/P-DIP 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 DQ1 A3 9 24 OE# Vcc A2 10 23 A10 Vss A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 A A0 A1 NC A3 A6 A8 B DQ4 A2 WE# A4 A7 DQ0 C DQ5 NC A5 D Vss E Vcc F DQ6 A17 DQ2 G DQ7 OE# CE# A16 A15 DQ3 H A9 1 A18 A10 2 A11 A12 3 4 TFBGA A13 5 AS6C4008A A18 A14 6 TSOP-II Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 2 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L H = VIH, L = VIL, X = Don't care. Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 3 I/O OPERATION High-Z High-Z DOUT DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. CE# = VIL and ICC - 55 II/O = 0mA Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE#≦0.2V and ICC1 II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL, ISB other pins at VIL or VIH Standby Power Supply Current ISB1 *5 CE# ≧VCC-0.2V Others at 0.2V or VCC - 0.2V MIN. 2.7 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 30 40 mA - 4 5 mA - 0.3 1.25 mA 25℃ - 1 3 µA 40℃ - 1 3 µA - 1 12 µA SLI SLI Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 4 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. AS6C4008A-55 UNIT MIN. MAX. tRC 55 ns tAA 55 ns tACE 55 ns tOE 30 ns tCLZ* 10 ns tOLZ* 5 ns tCHZ* 20 ns tOHZ* 20 ns tOH 10 ns SYM. AS6C4008A-55 MIN. MAX. tWC 55 tAW 50 tCW 50 tAS 0 tWP 45 tWR 0 tDW 25 tDH 0 tOW * 5 tWHZ* 20 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 5 UNIT pF pF AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 6 High-Z AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 7 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V 25℃ Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR VCC = 1.5V SLI CE# ≧ VCC - 0.2V 40℃ Other pins at 0.2V or VCC-0.2V SLI See Data Retention Waveforms (below) tR DATA RETENTION WAVEFORM VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≦ Vcc-0.2V VIH Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 8 MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 0.5 2.5 µA - 0.5 2.5 µA - 0.5 10 µA 0 - - ns tRC* - - ns AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 PACKAGE OUTLINE DIMENSION 32 pin 450 mil SOP Package Outline Dimension UNIT SYM. A A1 A2 b c D E E1 e L L1 S y Θ INCH.(BASE) 0.120(MAX) 0.004(MIN) 0.116(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445±0.006 0.555±0.025 0.050(TYP) 0.033±0.017 0.055±0.008 0.026(MAX) 0.004(MAX) o o 0 -10 Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 9 MM(REF) 3.048(MAX) 0.102(MIN) 2.946(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303±0.152 14.097±0.635 1.270(TYP) 0.838±0.432 1.397±0.203 0.660(MAX) 0.101(MAX) o o 0 -10 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.009 ±0.002 0.006 ±0.002 0.724 ±0.008 0.315 ±0.008 0.020 (TYP) 0.787 ±0.008 0.024 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 10 MM(REF) 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.22 ±0.05 0.155 ±0.055 18.40 ±0.20 8.00 ±0.20 0.50 (TYP) 20.00 ±0.20 0.60 ±0.10 0.08 ±0.10 0.08 (MAX) o o 0 ～5 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 32 pin 8mm x 13.4mm STSOP Package Outline Dimension UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) 0.049 (MAX) 0.004 ±0.002 0.039 ±0.002 0.009 ±0.002 0.006 ±0.002 0.465 ±0.008 0.315 ±0.008 0.020 (TYP) 0.528±0.008 0.02 ±0.008 0.031 ±0.005 0.003 (MAX) o o 0 ～5 Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 11 MM(REF) 1.25 (MAX) 0.10 ±0.05 1.00 ±0.05 0.22 ±0.05 0.155 ±0.055 11.80 ±0.20 8.00 ±0.20 0.50 (TYP) 13.40 ±0.20. 0.50 ±0.20 0.8 ±0.125 0.076 (MAX) o o 0 ～5 AS6C4008A Rev. 1.12 512K X 8 BIT LOW POWER CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 12 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 32 pin 600 mil P-DIP Package Outline Dimension UNIT SYM. A1 A2 B D E E1 e eB L S Q1 INCH(BASE) MM(REF) 0.015(MIN) 0.155±0.005 0.018±0.005 1.650±0.01 0.600±0.010 0.545±0.005 0.100(TYP) 0.650±0.020 0.158±0.043 0.075±0.010 0.070±0.005 0.381(MIN) 3.937±0.127 0.457±0.127 41.910±0.254 15.240±0.254 13.843±0.127 2.540(TYP) 16.510±0.508. 4.013±1.092 1.905±0.254 1.778±0.127 Note : D/E1/S dimension do not include mold flash. Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 13 AS6C4008A Rev. 1.12 512K X 8 BIT LOW POWER CMOS SRAM 32-pin 400mil TSOP-Ⅱ Package Outline Dimension Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 14 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 ORDERING INFORMATION Operating Temp Package Speed ns Alliance Organization VCC AS6C4008A-55PCN 512k x 8 3V 32pin 600mil DIP Commercial 0°C to 70°C 55 AS6C4008A-55SIN 512k x 8 3V 32pin 450mil SOP Industrial -40°C to 85°C 55 AS6C4008A-55TIN 512k x 8 3V 32pin TSOP 1 (8 x 20 mm) Industrial -40°C to 85°C 55 AS6C4008A-55STIN 512k x 8 3V 32pin sTSOP (8 x 13.4 mm) Industrial -40°C to 85°C 55 AS6C4008A-55BIN 512k x 8 3V 36pin TFBGA (6mm x 8mm) Industrial -40°C to 85°C 55 AS6C4008A-55ZIN 512k x 8 3V 32pin 400mil TSOP 11 Industrial -40°C to 85°C 55 PART NUMBERING SYSTEM AS6C 4008 -55 X X Low power SRAM prefix Device Number 40 = 4M 08 = by 8 Access Time Package Options: P = 32 pin 600 mil P-DIP S = 32 pin 450 mil SOP T = 32 pin TSOP 1 (8mm x 20mm) Z = 32 pin 400 mil TSOP 11 ST = 32 pin sTSOP (8mm x 13.4mm) B = 36 pin TFBGA (6mm x 8mm) Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 15 Temperature Range: C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) N N = Lead Free ROHS Compliant Part