AS6C6416-55BINTR

AS6C6416-55BIN Revision History 4M x 16 bit Low Power CMOS SRAM AS6C6416-55BIN 48ball FBGA PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date June 08 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN FEATURE GENERAL DESCRIPTION n Fast access time : 55ns n Low power consumption: Operating current : 12mA (TYP.) Standby current : 12µA (TYP.) n Single 2.7V ~ 3.6V power supply n All inputs and outputs TTL compatible n Fully static operation n Tri-state output n Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) n Data retention voltage : 1.2V (MIN.) n ROHS Compliant n Package : 48-ball 8mm x 10mm TFBGA The AS6C6416-55BIN is a 67,108,864-bit low power CMOS static random access memory organized as 4,194,304 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C6416-55BIN is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C6416-55BIN operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family Power Dissipation Operating Temperature VCC Range Speed -40 ~ 85℃ 2.7 ~ 3.6V 55ns AS6C6416-55BIN FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A21 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# Confidential DECODER I/O DATA CIRCUIT 4M x16 MEMORY ARRAY Standby(ISB1,TYP. ) Operating(ICC,TYP.) 12µA 12mA PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A21 Address Inputs DQ0 - DQ15 Data Inputs/Outputs CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT - 2 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN PIN CONFIGURATION A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc DQ12 A21 A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 A8 A9 A10 A18 A11 CE2 AS6C6416-55BIN XXXXXXXX XXXXXXXX H A2 A20 TFBGA(Top View) 1 2 3 4 5 6 TFBGA(See through with Top View) ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V TA -40 to 85(I grade) ℃ TSTG PD IOUT -65 to 150 1 50 ℃ W mA Operating Temperature Storage Temperature Power Dissipation DC Output Current *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# CE2 OE# WE# LB# UB# H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0 - DQ7 DQ8 - DQ15 High-Z High-Z ISB1 High-Z High-Z High-Z High-Z High-Z High-Z ICC,ICC1 High-Z High-Z DOUT High-Z ICC,ICC1 High-Z DOUT DOUT DOUT DIN High-Z ICC,ICC1 High-Z DIN DIN DIN H= VIH, L= VIL, X= Don't care. Confidential - 3 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = MIN. ICC CE#≦0.2V and CE2≧VCC-0.2V,II/O = 0mA Other pins at 0.2V or VCC-0.2V Average Operating Cycle time = 1µs Power supply Current ICC1 CE#≦0.2V and CE2≧VCC-0.2V,II/O = 0mA Other pins at 0.2V or VCC-0.2V Standby Power Supply Current ISB1 CE#≧ VCC-0.2V or CE2≦ 0.2V Other pins at 0.2V or VCC-0.2V MIN. 2.7 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. UNIT 3.6 V VCC+0.3 V 0.6 V 1 µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 12 20 mA - 3 5 mA 40℃ - 12 36 µA 85℃ - - 160 µA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values, measured at VCC = VCC(TYP.) and TA = 25℃, are included for reference only and are not guaranteed or tested. CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX. 15 20 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. Confidential - 4 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* AS6C6416-55BIN MIN. MAX. 55 55 55 30 10 5 20 20 10 55 20 10 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW AS6C6416-55BIN MIN. MAX. 55 50 50 0 45 0 25 0 5 20 50 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Confidential - 5 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Confidential - 6 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout tOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din Confidential tDH Data Valid - 7 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5) tWC Address tAW tWR CE# tCW tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Confidential - 8 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time IDR tCDR MIN. 1.2 VCC = 1.2V CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V TYP. MAX. UNIT 3.6 V 40℃ - 10 36 µA 85℃ - - 160 µA 0 - - ns tRC* - - ns See Data Retention Waveforms (below) tR DATA RETENTION WAVEFORM Low VCC Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Low VCC Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 VIL tR CE2 ≦ 0.2V VIL Low VCC Data Retention Waveform (3) (LB#, UB# controlled) VDR ≧1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# Confidential VIH tR LB#,UB# ≧ Vcc-0.2V - 9 of 11 - VIH Rev.1.0 June. 2017 AS6C6416-55BIN PACKAGE OUTLINE DIMENSION 48-ball 8mm × 10mm TFBGA Package Outline Dimension Confidential - 10 of 11 - Rev.1.0 June. 2017 AS6C6416-55BIN ORDERING INFORMATION AS6C SRAM 6416 55 6416=4M x 16 Access Time 55=55ns Bit B B = FBGA I N I=Industrial Indicates Pb and (-40° C~+85° C) Halogen Free XX Packing Type None:Tray TR:Reel Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 11 of 11 - Rev.1.0 June. 2017